JPS6257263B2 - - Google Patents
Info
- Publication number
- JPS6257263B2 JPS6257263B2 JP56204886A JP20488681A JPS6257263B2 JP S6257263 B2 JPS6257263 B2 JP S6257263B2 JP 56204886 A JP56204886 A JP 56204886A JP 20488681 A JP20488681 A JP 20488681A JP S6257263 B2 JPS6257263 B2 JP S6257263B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- nitride film
- silicon nitride
- silicon oxide
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、MNOS不揮発メモリの製造方法に関
する。従来MNOS素子の製造に関しては、シリコ
ン酸化膜を50〜100Å形成し、その上にシリコン
窒化膜を500Å程度形成し、このシリコン酸化膜
とシリコン窒化膜の界面補獲準位に電荷をトラツ
プし、これによりしきい値電圧をシフトさせデン
タを記録する不揮発メモリーとしている。ところ
が、実際のシリコン窒化膜には、多くの準位が膜
内に広く分布するため、シリコン酸化膜をトンネ
ル効果で通過した電荷（主に電子）は、シリコン
酸化膜―シリコン窒化膜界面だけでなくこのシリ
コン窒化膜内の準位に多くトラツプされる。この
ことは、消去時、つまりゲート電極とシリコン基
板層間に、電圧を印加しても、ゲート電極近傍に
トラツプされている電子は、基板へ逃げにくくな
り、結果的に消去特性の悪い不揮発メモリーとな
り、問題となつている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing MNOS nonvolatile memory. Conventionally, in manufacturing MNOS devices, a silicon oxide film is formed with a thickness of 50 to 100 Å, and a silicon nitride film of approximately 500 Å is formed on top of the silicon oxide film. This is a non-volatile memory that records data by shifting the threshold voltage. However, in an actual silicon nitride film, many levels are widely distributed within the film, so the charges (mainly electrons) that pass through the silicon oxide film due to the tunnel effect are only transmitted at the silicon oxide film-silicon nitride film interface. Instead, many of them are trapped in levels within this silicon nitride film. This means that during erasing, even if a voltage is applied between the gate electrode and the silicon substrate layer, electrons trapped near the gate electrode will have difficulty escaping to the substrate, resulting in a nonvolatile memory with poor erasing characteristics. , has become a problem.
従来これらの欠点を除く方法として、シリコン
酸化膜―シリコン窒化膜界面に、金属層とか、金
属酸化物層を非常に薄くコーテイングすることが
試みられているが、可動イオン等の混入がさけら
れず、ゲート電極へのリークが生じ易くなり、信
頼性に欠けるものであつた。 Conventionally, as a method to eliminate these drawbacks, attempts have been made to coat the silicon oxide film-silicon nitride film interface with a very thin metal layer or metal oxide layer, but the incorporation of mobile ions etc. cannot be avoided. , leakage to the gate electrode is likely to occur, resulting in a lack of reliability.
そこで、本発明はトンネル効果により、侵入し
てきた電荷を、効率よくシリコン酸化膜―シリコ
ン窒化膜界面に、捕獲し、しかも、従来の方法に
みられる。ゲート電極へのリークなどのない
MNOS不揮発メモリの製造方法を提供するもので
ある。 Therefore, the present invention uses the tunnel effect to efficiently trap the invading charges at the silicon oxide film-silicon nitride film interface, which is different from the conventional method. No leakage to gate electrode
A method for manufacturing MNOS nonvolatile memory is provided.
次に、本発明の製造方法をＰチヤネルアルミゲ
ートMNOS素子を実施例として詳述する。第１図
が、工程断面図である。まずＮ型基板に、ソー
ス、ドレイン１０２を形成し、ゲート部に、200
〜500Åの厚さのシリコン酸化膜１０３を形成す
る。（第１図ａ）
アルミニア、窒素雰囲気で、前記のシリコン酸
化膜１０３を、50〜100Å残すようにして、熱窒
化を行い、シリコン窒化膜１０４を形成する。シ
リコン窒化膜の膜厚が不足の場合は、プラズマ
CVD法などの方法をもつて、もう一層シリコン
窒化膜１０５を形成し、水素シンタによる熱処理
を行い欠陥を少なくする。（第１図ｂ）
最後に、ゲート電極１０６として、アルミニウ
ムを形成し、MNOS素子は完成する。 Next, the manufacturing method of the present invention will be explained in detail using a P-channel aluminum gate MNOS device as an example. FIG. 1 is a cross-sectional view of the process. First, a source and a drain 102 are formed on an N-type substrate, and a 200
A silicon oxide film 103 with a thickness of ~500 Å is formed. (FIG. 1a) The silicon oxide film 103 is thermally nitrided in an aluminium and nitrogen atmosphere, leaving a thickness of 50 to 100 Å, to form a silicon nitride film 104. If the silicon nitride film is insufficiently thick, plasma
Another layer of silicon nitride film 105 is formed using a method such as CVD, and heat treatment is performed using hydrogen sintering to reduce defects. (FIG. 1b) Finally, aluminum is formed as the gate electrode 106, and the MNOS element is completed.
次に、本発明によつて製造した素子の特長を挙
げる。 Next, the features of the device manufactured according to the present invention will be listed.
(1) 従来の方法では、ゲート酸化膜を、50〜100
Åと非常に薄くしかもピンホール等欠陥のない
膜を形成する必要があつたが、本発明では、
200〜500Åとかなり厚いゲート酸化膜を形成す
ればよく制御性が非常に高くなる。(1) In the conventional method, the gate oxide film is
It was necessary to form a film that was as thin as 1.5 Å and free from defects such as pinholes, but in the present invention,
Controllability is very high by forming a fairly thick gate oxide film of 200 to 500 Å.
(2) 熱窒化によつて作られたシリコン窒化膜は、
欠陥が少なく信頼性が高い。(2) Silicon nitride film made by thermal nitriding is
High reliability with few defects.
(3) シリコン酸化膜―シリコン窒化膜界面が、非
常に安定しすぐれている。(3) The silicon oxide film-silicon nitride film interface is extremely stable and excellent.
以上のような特長点から、従来の製造方法にみ
られた消去特性の悪さ、ゲート電極へのリークな
どによる信頼性の低さが、全て一掃できる。 Due to the above-mentioned features, the poor erase characteristics and low reliability caused by leakage to the gate electrode, which were observed in conventional manufacturing methods, can be completely eliminated.
第１図ａ，ｂ，ｃは本発明の実施例である。 FIGS. 1a, b, and c show embodiments of the present invention.
Claims (1)
Semiconductor）素子の製造に於いてシリコン酸
化膜を形成し、該シリコン酸化膜の一部を熱窒化
してシリコン窒化膜とし、その上に、気相成長法
あるいは、プラズマ推積法などにより異なるシリ
コン窒化膜を形成することを特徴とする半導体装
置の製造方法。1 MNOS (Metal―Nitride―Oxide
(Semiconductor) During device manufacturing, a silicon oxide film is formed, a portion of the silicon oxide film is thermally nitrided to form a silicon nitride film, and a different silicone A method for manufacturing a semiconductor device, comprising forming a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204886A JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204886A JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58106873A JPS58106873A (en) | 1983-06-25 |
| JPS6257263B2 true JPS6257263B2 (en) | 1987-11-30 |
Family
ID=16498019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56204886A Granted JPS58106873A (en) | 1981-12-18 | 1981-12-18 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58106873A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4342621B2 (en) | 1998-12-09 | 2009-10-14 | 株式会社東芝 | Nonvolatile semiconductor memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1491205A (en) * | 1973-11-07 | 1977-11-09 | Ici Ltd | Flameless heaters |
| JPS5733700B2 (en) * | 1974-05-08 | 1982-07-19 |
-
1981
- 1981-12-18 JP JP56204886A patent/JPS58106873A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58106873A (en) | 1983-06-25 |
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