JPS6257266B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor device including a field effect transistor in which ions are implanted using a gate electrode as a mask, eliminating problems such as disconnection of upper layer wiring, and improving gate withstand voltage. The present invention relates to an improvement in a manufacturing method of the gate electrode, other electrodes, and first layer wiring patterns, which realizes the above.

(2) Background of the Technology In semiconductor devices, especially integrated circuits, wiring patterns that connect electrodes or extraction electrodes of transistors, diodes, etc. are often formed from the same conductive film as some of the electrodes. Further, it is often necessary for one of these wirings to cross another wiring, and in this case, the electrode/wiring pattern is usually formed using two or more layers of conductor films.

That is, first, the first layer of conductive film is patterned to form a first layer of electrode/wiring patterns, and then an interlayer of silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), etc. is formed on top of that. An insulating film is formed and required openings are provided therein. Next, a second layer of conductive film is provided and required patterning is performed to form a second layer of electrode/wiring patterns, thereby insulating the intersecting wires with the interlayer insulating film and making the necessary connections through the interlayer insulating film. An electrode/wiring pattern is formed in the opening.

(3) Prior art and problems When the electrodes and wiring patterns intersect as described above, the electrodes and wiring in the first layer create a step in the interlayer insulating film formed thereon, and the wiring pattern in the second layer Since the shape generally crosses this step, a cross section of the second layer wiring pattern is likely to occur at the edge of the step.

As a countermeasure against this disconnection, there is a method called the resin film coating method in which uneven parts of the interlayer insulating film are filled with an insulating film to eliminate the level difference, or the interlayer insulating film is made of phosphosilicate glass containing germanium oxide (GeO ₂ ). Conventionally, a method has been practiced in which the shape is smoothed by forming the shape and subjecting it to high-temperature heat treatment to make the shape smooth.

These already known methods involving high-temperature heat treatment can be easily utilized when the semiconductor material is silicon (Si), which is relatively resistant to high-temperature heat treatment, but for example, when using compound semiconductor materials such as gallium arsenide (GaAs). In the manufacturing process of semiconductor devices using
Since it is very difficult to perform high-temperature heat treatment at a temperature of about 0.degree.

Furthermore, Schottky barrier field effect transistor elements are often used in compound semiconductor devices such as GaAs, and their characteristics can be improved by a self-alignment method in which impurity ions are implanted into the source and drain regions using the gate electrode as a mask. In this case, the slope of the side end surfaces of the gate electrode becomes a particular problem.

In other words, when impurity implantation is performed using a gate electrode with a trapezoidal cross section as a mask, a portion of the impurity passes through the bottom part of the gate electrode, and a region with an incomplete mask effect is formed continuously in the intended impurity implantation region. ,
The source region and the drain region become unclear and blurred, resulting in a reduction in gate withstand voltage after the semiconductor device is completed.

However, since it is important to prevent damage to the semiconductor substrate in the etching process for patterning electrodes and wiring, physical etching methods such as ion milling are not used, but wet etching or reactive ion etching is used instead. However, in these methods, side etching progresses under the mask completely or almost isotropically, and even in reactive ion etching, which is easier to obtain directionality than wet etching, the pattern cross section has a top edge. The trapezoid is narrower than the mask and has a wider bottom edge than the top edge, causing the above-mentioned problem.

(4) Purpose of the Invention The present invention relates to a semiconductor device including a field effect transistor element in which ions are implanted using a gate electrode as a mask, in which the gate electrode and a first layer wiring pattern serving as a lower layer wiring of a three-dimensional intersection are made of the same conductor. This method proposes a manufacturing method in which the gate electrode and wiring pattern are formed from a film, but by giving the gate electrode and wiring pattern an optimal cross-sectional shape, which have different conditions, it is possible to prevent disconnections in the upper layer wiring without performing high-temperature heat treatment in the subsequent manufacturing process. The purpose of this invention is to eliminate obstacles and solve problems such as the reduction in gate withstand voltage mentioned above.

(5) Structure of the Invention The above object of the present invention is to perform anisotropic first etching on the conductor film, which has a large effect in the vertical direction, using a first mask provided on the conductor film on a semiconductor substrate. and forming openings for impurity ion implantation regions to be used as the gate pattern and source and drain of the field effect transistor element, and removing the first mask and etching the conductive film with anisotropic etching. A step of performing a second etching to strengthen the etching, making the slope of the side end face of the gate pattern steep, and making the shoulder part into a rounded and smooth shape, and ion implantation of the required impurity into the opening. a step of forming a second mask that selectively covers the region of the conductor film to be used as an electrode and/or wiring, the gate pattern and the opening; and a step of etching the conductor film different from the first etching step. performing a third etching with a weakened orientation to form an electrode and/or a first layer wiring pattern having a shoulder angle between the top surface and the side end surface larger than that of the gate pattern;
Achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of depositing an interlayer insulating film with a required opening on the semiconductor substrate, and forming a second layer wiring pattern on the interlayer insulating film. be done.

(6) Examples of the invention The present invention will be specifically described below using examples with reference to the drawings.

1 to 10 are cross-sectional views showing an embodiment of the present invention in a GaAs integrated circuit, and the same reference numerals indicate the same parts throughout the figures. Further, FIGS. 11 and 12 are schematic diagrams each illustrating the etching of a gate electrode and a wiring pattern according to the present invention.

As shown in FIG. 1, a mask 2 made of, for example, SiO ₂ is provided on a semi-insulating GaAs substrate 1, and selective ions such as Si or tin (Sn) are implanted at a temperature of 700°C.
15°C to 900°C in an oxygen-free atmosphere
A heat treatment is performed for about a minute to form an n-type active layer 3.

Next, as shown in FIG. 2, the mask 2 used for the selective ion implantation is removed, and the entire surface of the substrate 1 is covered with a high melting point metal silicide, such as titanium/tungsten, which will be the material for the gate electrode and the first layer wiring. - A first conductor film 4 made of silicide is formed to a thickness of about 600 nm by sputtering, MO-CVD, or the like.

Next, as shown in FIG. 3, a mask 5 of SiO ₂ or the like is formed on the conductor film 4 to form openings for a gate pattern and impurity ion implantation regions to be used as sources and drains. This mask 5 is formed by using a resist mask (not shown in the figure) on the SiO ₂ film formed by CVD method etc.
dry or wet etching.

Next, the conductor film 4 is etched to form the gate pattern 6 and the ion implantation window 7.
As mentioned above, it is important to prevent the cross-sectional shape of the gate pattern from becoming a trapezoid with a wide base.
In addition, the present invention intends that the shoulder portion has a rounded and smooth shape.

In order to realize such a cross-sectional shape, in the present invention, as schematically shown in FIGS. 11a and 11b, two anisotropic etching processes having different characteristics are performed as follows. In order to control the etching characteristics in this manner, the most suitable method is the reactive ion etching method, which has a reactive etching effect based on a chemical reaction and an anisotropic etching effect, which is a characteristic of ion etching technology.

A parallel plate type device is suitable for this reactive ion etching process, and the conductor film 4
_In this example, titanium/tungsten silicide is used as
A gas containing as the main component is suitable as an etchant.

In other words, in the first etching process, the gas pressure is usually not so low considering the etching speed.
By increasing the bias voltage, the anisotropy in the vertical direction is strengthened, and as shown in FIG. 11a, there is less side etching than in the prior art, but it still forms a trapezoid with a widened base.

Next, in a second etching process, the vertical anisotropy is further strengthened using high vacuum reactive ion etching technology, and the mask 5 is removed.
As shown in FIG. 11b, the bottom portion of the gate pattern 6 is removed and the shoulder portion thereof is etched. Note that in consideration of damage to the semiconductor substrate, the bias voltage is usually lower than that in the first etching.

That is, in this embodiment, the first etching process for forming the gate pattern 6 and the ion implantation window 7 from the conductor film 4 as shown in FIG. Carry out the process to the extent that side etching does not progress too much.

Etching gas composition: CF ₄ + H ₂ = 80 sccm + 20 sccm Etching gas pressure: 2 pa Self-bias voltage: 140 V High frequency power: 100 W Etching rate: Approximately 200 Å/min Next, as shown in FIG. The second etching is performed for a short time under certain conditions to remove or reduce the incomplete area of the mask effect at the bottom of the gate pattern 6, and to remove the shoulder ( The cross-sectional shape is shaped by removing sharp edges or corners to create a rounded and smooth shape.

Etchant gas composition: CF ₄ =100 sccm Etchant gas pressure: 0.5 pa Self-bias voltage: 100 V High frequency power: 50 W Etching rate: Approximately 100 Å/min Next, the source and drain high concentration regions are formed by impurity ion implantation. That is, selective ion implantation of Si or the like is performed using the conductor film 4 on which the gate pattern 6 and the ion implantation window 7 are formed as a mask, and then, as shown in FIG. 6, the entire surface is protected with SiO ₂ or the like. After providing the film 8, the same heat treatment as described above is performed to reduce the carrier concentration to 3 on the surface.
A high concentration source region 9 and a high concentration drain region 10 of approximately ×10 ¹⁷ cm ^-3 are formed.

Next, as shown in FIG. 7, for example, the protective film 8 is used to form a mask for the first-layer wiring pattern, and the protective film 8 is also left for the gate pattern 6 and the ion implantation window 7, and the conductor is used as a mask. A third etching process is performed on the film 4 to form a first layer wiring pattern 11.

In this third etching, as shown in the schematic diagram in FIG. 12, the side end surface of the first layer wiring pattern 11 is gently inclined with respect to the substrate, and the angle of the shoulder between the top surface and the side end surface is initially adjusted. In order to make the gate pattern larger than that of , when reactive ion etching is used, the gas pressure is set higher and the bias voltage is set lower than the first etching conditions in the preceding stage, for example, as described below, to approximate isotropy.

Etchant gas composition: CF ₄ + O ₂ = 90 sccm + 10 sccm Etchant gas pressure: 5 pa Self-bias voltage: 120 V High frequency power: 100 W Etching rate: Approximately 500 Å/min During this etching, since the gate pattern 6 is masked, there is no reduction in cross-sectional area. , there is no increase in gate resistance.

Next, as shown in FIG. 8, after removing the protective film 8 that was used as a mask when forming the first layer wiring pattern 11, the electrodes 12 and 13, etc., which are in ohmic contact with the source and drain regions, are made of, for example, gold or germanium. Consists of money.

Next, as shown in FIG. 9, an interlayer insulating film 14 is provided.

This interlayer insulating film 14 is formed by, for example, the CVD method.
It is made of SiO ₂ and has a thickness of about 600 nm. In this embodiment, as explained above, the shoulder part of the gate pattern 6 is shaped into a rounded and smooth shape,
Since the wiring pattern 11 has a gently sloped side end face and a large obtuse angle at the shoulder, the interlayer insulating film 1
4 has a smooth shape even in the stepped portion on the gate pattern 6 or the wiring pattern 11.

Next, as shown in FIG. 10, the interlayer insulating film 14
After providing necessary openings, for example 15 and 16, by lithography, a second layer of conductive film is formed,
Required patterning is performed to obtain the second layer wiring pattern 17.

Although the formation of the second layer wiring pattern 17 can be carried out using conventional techniques, it is necessary to further prepare the cross-sectional shape of the second layer wiring pattern 17, such as by providing a third layer wiring pattern. In some cases, the same method and conditions as those for etching the first layer wiring pattern 11 are used.

(7) Effects of the Invention As explained above, the present invention applies two anisotropic etching treatments with different characteristics to a conductor film in the manufacturing process of a semiconductor device including a field effect transistor element in which ions are implanted using a gate electrode as a mask. In particular, in the second process, the anisotropy was strengthened and the mask was removed to create a gate pattern with a smooth shape with rounded shoulders and steep side edges, and a source/drain ion implantation window. After forming and implanting impurity ions, a third near-isotropic etching process is performed to form a first-layer wiring pattern whose side end surfaces are gently inclined and whose shoulder angle between the top surface and the side end surfaces is larger than that of the gate pattern. By forming the interlayer insulating film from the conductive film, the interlayer insulating film becomes smooth even at the stepped portion, and problems such as disconnection of the second layer of the electrode/wiring pattern formed thereon are eliminated. It does not require high-temperature heat treatment as in the prior art and has a wide range of applications.

Furthermore, since the side end faces of the gate electrode pattern of the field effect transistor element are steep, the high concentration regions of the source and drain where ions are implanted using this as a mask become clear, and effects such as improved gate withstand voltage can be obtained.

[Brief explanation of the drawing]

FIGS. 1 to 10 are cross-sectional views showing embodiments of the present invention, and FIGS. 11 and 12 are schematic cross-sectional views illustrating etching of a gate electrode pattern and a first layer wiring pattern according to the present invention, respectively. . In the figure, 1 is a substrate, 2 is a mask, 3 is an n-type active layer, 4 is a conductor film, 5 is a mask, 6 is a gate electrode pattern, 7 is an ion implantation window, 8 is a protective film, 9
10 is a source high concentration region, 10 is a drain high concentration region, 11 is a wiring pattern of the first layer, 12 is a source electrode, 13 is a drain electrode, 14 is an interlayer insulating film,
15 is an opening, 16 is an opening, and 17 is a second layer wiring pattern.

Claims (1)

[Claims] 1. Using a first mask provided on a conductor film on a semiconductor substrate, the conductor film is subjected to first anisotropic etching with a large effect in the vertical direction, thereby forming a field effect transistor element. forming gate patterns and openings for impurity ion implantation regions to be used as sources and drains, and removing the first mask and etching a second etching layer on the conductor film, which has stronger anisotropy than the first etching process. a step of etching the gate pattern to steepen the slope of the side end face and give the shoulder portion a rounded and smooth shape; a step of ion-implanting a required impurity into the opening; forming a second mask that selectively covers the region of the film to be used as an electrode and/or wiring, the gate pattern and the opening, and etching the conductor film with a second mask having weaker anisotropy than the first etching. Step 3: performing etching to form an electrode and/or a first layer wiring pattern having a shoulder angle between the top surface and the side end surface larger than that of the gate pattern, and forming an interlayer insulating film with a required opening into the semiconductor A method for manufacturing a semiconductor device, comprising the steps of: depositing on a substrate; and forming a second layer wiring pattern on the interlayer insulating film.