JPS6258151B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly preferably to the structure of an ultra-small semiconductor device.

In conventional semiconductor technology, in order to improve the high frequency characteristics of semiconductor devices, the junction area is reduced to reduce the parasitic capacitance component, and the distance between the junction and the electrode is reduced to reduce the parasitic resistance component. Efforts have been made to reduce the However, in the conventional technology, in addition to the minimum spacing determined by the processing accuracy of each pattern, a certain distance between patterns is required in order to relatively match each pattern, and therefore the bonding area and the distance between one bonding electrode are Both had to be larger than the minimum unit that could be achieved with machining accuracy.

An object of the present invention is to provide a novel structure that enables an ultra-small semiconductor device having a small junction area.

The semiconductor device of the present invention includes a first insulating film provided on a semiconductor substrate, one opening provided in the first insulating film, and a portion of the semiconductor substrate inside the one opening. first and second semiconductor regions containing different impurities located therein; and a first semiconductor layer extending over the first insulating film and in ohmic contact with the first semiconductor region within the one opening. and a second insulating film converted from a material to the first semiconductor layer adjacent to a side surface of the first semiconductor layer, the second insulating film covering a portion of the semiconductor substrate portion within the one opening. a second semiconductor layer that is in ohmic contact within the one opening with a portion of the second semiconductor region not covered by the first insulator film and the second insulator film; It is characterized by having the following.

In conventional semiconductor devices of this type, only one ohmic contact exists in one opening provided in the first insulating film, and other ohmic contacts exist in other openings. A second insulating coating converted from the contact material and adjacent to its side is provided only on the first insulating coating. Therefore, in order to provide ohmic contacts to different impurity regions on the substrate, a first opening and a second opening are formed in the first insulating film.
The contact material layer placed on top of the openings must have a spacing that takes into account the alignment between the openings, and the contact material layer that is placed on top of the openings must have an electrode portion that covers the first and second openings and is larger than that, taking alignment into account. This is necessary, and the portion of the gap between the openings that is larger than the width of the second insulator becomes a useless dimension.

In contrast, in the present invention, the first semiconductor layer and the second semiconductor layer are ohmically connected to different impurity regions within one opening provided in the first insulating film, and Since the second insulating film adjacent to the side surface and converted from that material also covers the surface of the substrate within the same opening, it is highly effective in miniaturization and reduction in the number of alignments.

Next, the present invention will be explained using the drawings.

First, referring to FIG. 1B, the basic configuration of the present invention is that a semiconductor substrate 1 of one conductivity type covered with an oxide film (first insulating film) 2 having an opening has one conductivity on the surface exposed at the opening. It has a shaped semiconductor substrate region and an opposite conductivity type region 7, and has polycrystalline silicon electrode wiring paths 5, 6 and silicon oxide 4 in ohmic contact with regions 7 and 1, respectively, in this opening. . In this configuration, as shown in FIG. 1A, a polycrystalline silicon thin film 3 is provided inside and outside the opening, and then selectively oxidized, impurity atoms of the opposite conductivity type are introduced into the semiconductor substrate through a desired electrode portion 5. It can be formed by introducing the opposite conductivity type region 7 into the inside. With this configuration, the regions 1 and 7 and the electrode wirings 5 and 6 for each region are relatively arranged with a minimum distance between them, so that an essentially extremely small semiconductor device can be obtained.

Next, an example in which the present invention is applied to a bipolar transistor will be described as a preferred embodiment of the present invention with reference to FIGS. 2A to 2J. The structure of this embodiment is made, for example, by the following steps.

An N-type silicon substrate 11 is thermally oxidized to form a silicon oxide film 12, and an opening 13 reaching the substrate surface is provided at a desired portion (FIG. 2A). Next, a silicon thin film 14 with a thickness of 0.5 microns is formed and deposited over the entire surface of the substrate exposed by the silicon oxide film 12 and the opening 13 by a gas phase reaction (FIG. 2B), and boron atoms are introduced through the silicon thin film 14. is introduced into the semiconductor substrate 11 by a thermal diffusion method. At this time, since the silicon oxide film 12 has a masking effect on the boron atoms, the boron atoms cover the entire silicon thin film 14 and the opening 13 of the semiconductor substrate.
The P-type base region 15 is formed (FIG. 2C). Next, a 0.2 micron thick silicon nitride film 16 is formed and deposited on the surface of the silicon thin film 14 by a vapor phase reaction (Fig. 2D), and a photoresist is used to remove the areas that will become future electrode wiring paths. All silicon nitride film portions are removed (FIG. 2E). It is preferable to use Freon gas plasma reaction for selectively removing the silicon nitride film. Next, the silicon thin film is converted into silicon oxide 17 by thermal oxidation treatment. At this time, due to the masking effect of the silicon nitride film, the portions covered with the silicon nitride films 16, 16' are not oxidized and remain as silicon thin films, and the side surfaces are converted into oxides so that they are mutually separated. Separate electrode wiring paths 14, 14' are formed (FIG. 2F).
Next, only the silicon nitride film portion 16' covering the silicon thin film 14' in a portion corresponding to the future emitter electrode wiring path is selectively removed, and neighboring atoms are introduced by thermal diffusion. At this time, since the silicon oxide films 12 and 17 and the silicon nitride film 16 have a masking effect on the neighboring atoms, the neighboring atoms are exposed to the silicon thin film portion 14' and the silicon thin film portion 14' from which the silicon nitride film has been removed. N is introduced into the semiconductor substrate area where it will be bonded to the semiconductor substrate, and by keeping the concentration of phosphorus higher than the previously introduced boron
The emitter region 18 converted into a shape and the emitter electrode wiring path 1 ohmically connected to the emitter region
4' is obtained (Fig. 2G). Next, after removing all the remaining silicon nitride film, oxidation treatment is performed again to form a silicon oxide film 17' on the surface of the silicon thin films 14 and 14' (FIG. 2H), and an opening 19 is formed in the silicon oxide film at a desired portion. (FIG. 2 I) and a metal electrode 20 for external connection (FIG. 2 J) to complete the bipolar NPN transistor. Note that before forming the silicon thin film 14 in the steps shown in FIGS. 2A to 2C, the base region 15 may be formed by diffusion or ion implantation, and then the silicon thin film 14 doped with P-type impurities may be deposited. According to this embodiment, the silicon thin films 14 and 1 are in ohmic contact with the P-type base 15 and the N-type emitter, respectively, at the opening of the first insulating film 12.
A structure is provided in which 4' and its oxide film are in contact with the surface of the semiconductor substrate at the opening.

Next, an example in which the present invention is applied to a bipolar transistor in a semiconductor integrated circuit will be described as still another embodiment of the present invention with reference to FIGS. 3 to 3F.

First, an N-type collector region 43 is provided in a P-type semiconductor substrate 41, and a silicon thin film 44 is deposited on the substrate in contact with the collector region 43 through a window formed in an oxide film 42 covering the surface of the substrate (see FIG. 3). A). In order to obtain this structure, a method similar to that described for the steps of FIGS. 2A to 2C in the previous embodiment is used, that is, a silicon thin film 44 is preliminarily formed, and a silicon thin film 44 is formed in advance and the substrate is The collector region 43 may be formed by introducing N-type impurities into the substrate 41 from the portion in contact with the oxide film 41, or by vapor phase diffusion or ion implantation of impurities into the substrate 41 in advance through the window of the oxide film 42. A collector region 43 is formed by etching, and then a silicon thin film 4 doped with an N-type impurity or not doped with an impurity is formed so as to be in contact with this region 43.
4 may be applied. Next, the silicon thin film 44
The silicon nitride films 46, 46' are formed on the surface of the silicon nitride film 46, 46' except for at least a portion that should become a region 47' that insulates between the collector electrode wiring path and other electrode wiring paths.
Using the silicon nitride films 46, 46' as masks, the exposed portions of the silicon thin film 44 are converted to silicon oxide films 47', 47 over their entire thickness by thermal oxidation or anodic oxidation (FIG. 3B). ). Here, a portion 47 of the silicon thin film outside the device periphery is also oxidized;
7 may be masked with silicon nitride 46, 46' and exposed and oxidized during the second oxidation step (FIG. 3D). In this example, as shown in FIG. 3B, the collector electrode wiring path 4 is insulated from other electrode wiring paths 44' by the first oxidation process.
4 is formed. Next, the silicon nitride covering the surface of the collector electrode wiring path 44 is left as it is, and the other silicon nitride 46' is removed, and the P-type impurity is introduced into the collector region 4 through the exposed other electrode wiring path 44'.
3 to form a P-type base region 45 (FIG. 3C). Thereafter, the surface of the partially oxidized silicon thin film is exposed so that at least a portion of the surface of the silicon thin film that is to become a region 47' that insulates between the base electrode wiring path and the emitter electrode wiring path is exposed, and at least the portion of the surface of the collector, base, and emitter electrode Wiring path 44, 4
4′, 44″ are covered with silicon nitride films 46, 4
A second oxidation treatment is performed to remove the entire thickness of the exposed silicon thin film.
This is converted into a silicon oxide film 47'' (FIG. 3D). As a result, mutually insulated base and emitter wiring paths 44' and 44'' are formed. Next, the surface of the emitter wiring path 44'' is exposed, and N-type impurities are introduced into the base region 45 through the emitter wiring path 44'' to form an N-type emitter region 48 (FIG. 3E). If the initially formed silicon thin film (44 in FIG. 3A) is not doped with impurities, or if you want to ensure collector contact, the collector wiring path 44'' should be used in addition to the emitter wiring path 44''. The surface of the N + type region 4 is also exposed, and N type impurities are introduced through both to form the N ⁺ type region 4 in the collector region 43 at the same time as the emitter region 48 is formed.
9 (Fig. 3 E'). Next, each electrode wiring path 44, 44', 44'' is covered with a silicon oxide film 47'' formed by oxidation or an insulating film formed by vapor phase growth, etc.
A window is opened in the necessary portion and the upper layer wiring or bonding pad 50 is connected (FIG. 3F).
The NPN bipolar transistor 52 is connected to the substrate 4.
1 and the collector region 43, other elements provided in the substrate 41, such as 5
2 and similar transistors.

Although the embodiments have been described above, the technical scope of the present invention is not limited to the above embodiments.
The rights to this invention extend to all devices listed in the claims.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views of the device for explaining the basic configuration of the present invention, FIGS. 2A to 2-J are cross-sectional views of the device for explaining the configuration of one embodiment of the present invention, and FIG. 3A ~F are cross-sectional views of still other embodiments of the present invention. In the figure, 1, 11, 21, 41...semiconductor substrate,
2, 12, 22, 42... Oxide film, 3, 14,
24, 44... Silicon thin film, 4, 17, 27,
47...Silicon oxide film.

Claims (1)

[Scope of Claims] 1. A first insulating film provided on a semiconductor substrate, one opening provided in the first insulating film, and a semiconductor substrate portion within the one opening. first and second semiconductor regions containing different impurities located therein; and a first semiconductor layer extending over the first insulating film and in ohmic contact with the first semiconductor region within the one opening. a second insulating film converted from the material of the first semiconductor layer adjacent to a side surface of the first semiconductor layer; and a second insulating film formed by the first insulating film and the second insulating film a second semiconductor layer that is in ohmic contact within the one opening with a portion of the second semiconductor region that is not covered by the second semiconductor layer and extends over the first insulating film; 2. A semiconductor device, wherein the semiconductor device includes an impurity in the first semiconductor region and an impurity in the second semiconductor region. 2. A first insulating film provided on a semiconductor substrate, one opening provided in the first insulating film, and a first insulating film containing impurities located in the semiconductor substrate portion within the one opening. a first semiconductor layer that is in ohmic contact with the first semiconductor region within the one opening and extends over the first insulating film; a second insulating film converted from the material of the first semiconductor layer adjacent to a side surface of the second semiconductor layer not covered by the first insulating film and the second insulating film; a second semiconductor layer in ohmic contact with a portion of the region within the one opening and extending over the first insulating film but not overlapping the first semiconductor layer; 2. A semiconductor device, wherein the semiconductor layer and the second semiconductor layer are formed by converting a part of a single semiconductor layer into the second insulating film.