JPS6258596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a system in which a signal in which character or graphic patterns are decomposed or a coded signal is multiplexed and transmitted and received as a binary signal during the vertical retrace period of a television signal. The present invention provides a device that can reproduce a good sampling clock on the receiver side.

An example of the above system is
There are TELETEXT systems, ANTIOPE systems, etc., and in Japan there is a television teletext system. This method applies to any 1st to 2nd period from the 16th H to the 21st H during the vertical retrace period, and any 1st to 2nd period from the 279th H to the 284th H.
This is a system that sends and receives text information signals during the 2H period.

FIG. 1A shows the signal waveform of the character information signal, and FIG. 1B shows an enlarged view of the header section. In the figure,
1 is called the header section, 2 is the character information data section of the binary signal, and 3 is called the clock run-in signal16
4 is an 8-bit framing code signal, 5 is an 8-bit packet identification code signal, and 6 and 7 are program channel code signals.

Now, in this system, the character information signal is sent in the signal format shown in Figure 1, and is played back on the receiving side. , it is necessary to accurately reproduce the sampling clock for sampling each subsequent signal.

First, FIG. 2 shows a block diagram of an example of a circuit that directly reproduces a sampling clock from a pilot signal such as a clock run-in signal. In the figure, 11
1 is an input terminal that receives a character information signal as an input signal as shown in FIG. 1, 12 is a bandpass filter whose pass band is the repetition frequency of the clock run-in signal as a pilot signal, and 13 is a clock run-in signal and a portion thereof. 14 is an analog multiplier, 15 is a resonant circuit including a crystal resonator whose resonant frequency is twice the repetition frequency, 16 is a waveform shaping circuit, and 17 is an output terminal. It is.

FIG. 3 shows the waveforms of each part of the block diagram shown in FIG. 2, where A is the signal applied to the input terminal 11, and B
shows the waveforms of the output signal of the wave generator 12, C the output signal of the multiplier 14, D the output signal of the resonant circuit 15, and E the output signal of the output terminal 17.

Next, its operation will be explained. First, wave device 12
By setting the frequency characteristics appropriately narrow,
The wave generator 12 removes harmonic components of the repetition frequency of the clock run-in signal from the signal applied to the input terminal 11, and the analog gate circuit 13 extracts only the clock run-in signal and a portion slightly after it. The signal is converted into a sinusoidal signal as shown in FIG. 3B, and applied to the analog multiplier 14. The analog multiplier 14 has two input terminals, and the product E ₁ × of two input signals E ₁ and E ₂
This is a circuit that obtains E ₂ as an output signal, and now E ₁ =
If E ₂ = coswt, the output terminal has CoS ² wt = (1 +
2cos2wt)/2, that is, a signal with twice the frequency of the input signal can be obtained. Therefore, when signals as shown in FIG. 3B are applied to the analog multiplier 14 and multiplied by each other, an output signal with twice the frequency as shown in FIG. 3C can be obtained at its output terminal. can. This signal is then supplied to the resonant circuit 15 to generate vibration, and a continuous double frequency vibration signal as shown in FIG. 3D can be obtained at the output terminal 16. By shaping the waveform by clipping or the like, a good sampling clock like E can be obtained.

As described above, the analog multiplier 14 is set to the frequency 2
By using it as a doubler, the S/N of the input signal can be increased.
The resonant circuit 15 accurately transmits the frequency component twice the repetition frequency of the clock run-in signal even under bad conditions.
, and the correct sampling clock can be obtained.

However, it is difficult to maintain the damped vibration caused by the resonant circuit 15 stably for one horizontal period, so the present invention uses the sampling clock obtained from the pilot signal for detecting the framing code signal. The information signals after the packet identification code signal 5 shown in FIG. In this system, the frequency is divided by 1/N so that it is in phase with the sampling clock, and the output signal of the frequency divider is used as the sampling clock to supply a stable clock.

FIG. 4 shows a block diagram of one embodiment. In the figure, 11 is an input terminal for information signals such as characters, 18 is a sampling clock reproducing circuit as shown in FIG. 20 is a serial-to-parallel conversion register 21, a NOT circuit 22, and an AND circuit that sequentially shifts the information signal applied to the input terminal 19 using the output signal of the sampling clock regeneration circuit 18 as a clock. 23 and a flip-flop circuit 24, the detection circuit outputs a detection signal that changes from low level to high level at the 8th bit of the framing code signal; 25 indicates the repetition frequency of the pilot signal;
Oscillator whose oscillation frequency is 2N times the frequency, 26
28 is a 1/N frequency divider made of a flip-flop circuit or the like configured to operate only when the reset signal input terminal 27 is at a high level and to be in the initial state when it is at a low level; 28 is a repeater of the pilot signal. This is an output terminal that outputs a sampling clock signal that has twice the frequency and is in phase with the output signal of the sampling clock recovery circuit 18.

FIG. 5 shows signal waveforms at various parts of the block diagram shown in FIG. 4 when N is set to 5. A is input terminal 1
9, B is the waveform of the output signal of the sampling clock regeneration circuit 18, C is the waveform of the output signal of the oscillator 25, and D is the waveform of the output signal of the detection circuit 20.
E is the waveform of the output signal of the output terminal 28.

To explain its operation, as shown in Figure 5,
Using the sampling clock B having the correct phase with respect to the pilot signal obtained by the reproducing circuit 18, the detection circuit 20 generates a detection output D that changes from a low level to a high level at the fifth bit of the framing code signal 4. obtain. Here, as is clear from FIG. 5, the detection circuit 20 is a serial-to-parallel conversion register using the output signal B of the sampling clock regeneration circuit 18 as a clock, as is clear from FIG. The circuit configuration is such that the information signal received at 21 is converted into an 8-bit parallel signal, and goes from low level to high level when the 8th bit of framing code signal 4 is received. Ignoring the delay time, the timing is in phase with the output signal B of the sampling clock recovery circuit 18. Therefore, if the output signal of the detection circuit 20 is applied to the reset signal input terminal 27 to start the operation of the frequency divider 26, the output terminal 28 receives a signal having the same frequency and phase as the output signal B of the regeneration circuit 18. signal is obtained.

With the above configuration, circuit difficulties can be eliminated and the sampling clock can be reduced to 1H.
can be obtained stably over time.

Furthermore, if the oscillator 24 is constructed using a crystal oscillator, it is of course more stable.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram of an example of a character information signal that is transmitted superimposed on a television signal, Fig. 2 is a block diagram of an example of a circuit that reproduces a sampling clock from the pilot signal, and Fig. 3 is the same. FIG. 4 is a block diagram of a sampling clock reproducing device according to an embodiment of the present invention, and FIG. 5 is a waveform diagram of each part of the circuit. 11...Input terminal, 18...Sampling clock regeneration circuit, 19...Input terminal, 20...Detection circuit, 21...Shift register, 22...NOT
Circuit, 23...AND circuit, 24...Flip-flop, 25...Oscillator, 26...Frequency divider, 27
...Reset terminal, 28...Output terminal.

Claims (1)

[Claims] 1. A receiving circuit that receives an information signal that is transmitted superimposed on a television signal, and a pilot signal that is included in the information signal and indicates the reference phase of each signal to a frequency that is twice the repetition frequency of the pilot signal. a sampling clock regeneration circuit for regenerating the sampling clock of the sampling clock; a detection circuit for detecting a framing code signal in the information signal using the sampling clock obtained by the sampling clock regeneration circuit;
It is equipped with an oscillator whose oscillation frequency is 2N times as high as the oscillation frequency, and a frequency divider that has a reset function and divides the oscillation output signal of the oscillator by 1/N, and the output signal of the detection circuit is used to divide the frequency by the output signal of the detection circuit. A sampling clock regeneration characterized in that the output signal of the frequency divider is synchronized with the framing code signal by resetting the frequency divider, and the output signal of the frequency divider is outputted as a sampling clock for information signals subsequent to the framing signal. Device.