JPS6258668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to C-MOS integrated circuits and methods of using the same.

The fields of application of C-MOS integrated circuits are expanding because of their advantages such as high noise margin, low power consumption, wide operating power supply voltage range, and wide operating temperature range.

Particularly recently, digital/analog mixed LSIs such as DA, AD converters, communication codecs, and analog signal processing LSIs are being developed.

A C-MOS integrated circuit is generally a device that utilizes the surface area of a semiconductor, and a carrier, which is a carrier of a signal, moves in an area of several micrometers in the surface layer of a semiconductor substrate. However, in a C-MOS integrated circuit in which an analog circuit section and a digital circuit section coexist, electrical noise generated in the digital circuit section often affects the analog circuit section. This occurs because the electrical noise, such as a digital high frequency signal, propagates as a carrier through the surface layer of the semiconductor substrate and is absorbed by the analog circuit section.

FIG. 1 is a sectional view of an example of a conventional C-MOS integrated circuit having a digital circuit section and an analog circuit section.

In FIG. 1, a P well 2, an N type diffusion layer 3, a P type diffusion layer 4, an oxide film 5, and an electrode 6 are formed on an N type semiconductor substrate 1, and a digital circuit section 10 and an analog circuit section 20 are formed. has been done.

This digital circuit section 10 and analog circuit section 2
Since there is no special diffusion layer etc. between 0 and 0, for example, electrical noise generated in the digital circuit section 10 propagates in the N-type substrate 1 as a carrier as shown by arrow A, and reaches the P well of the analog circuit section 20. 2, which has the disadvantage of modulating the characteristics of active elements therein.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a C-MOS integrated circuit in which a separation section is provided between a digital circuit section and an analog circuit section to eliminate electrical noise.

Another object of the present invention is to apply the lowest potential to the separation section when the substrate of the C-MOS integrated circuit is an N-type semiconductor substrate, and to apply the lowest potential to the separation section when the substrate of the C-MOS integrated circuit is a P-type semiconductor substrate. An object of the present invention is to provide a method of using a C-MOS integrated circuit in which the influence of electrical noise is eliminated by applying the highest potential to the C-MOS integrated circuit.

The C-MOS integrated circuit of the present invention includes a digital circuit section and an analog circuit section formed on a semiconductor substrate of one conductivity type, and the digital circuit section and the analog circuit formed between the digital circuit section and the analog circuit section. The isolation part includes a diffusion layer of an opposite conductivity type for separating the parts from each other, and an electrode connected to the diffusion layer.

Further, the method of using the C-MOS integrated circuit of the present invention includes a digital circuit section formed on a semiconductor substrate of one conductivity type, an analog circuit section, and a digital circuit section formed between the digital circuit section and the analog circuit section. A C-MOS including a separation section having an opposite conductivity type diffusion layer for separating a circuit section and an analog circuit section and an electrode connected to the diffusion layer.
When the semiconductor substrate of one conductivity type of the integrated circuit is an N-type semiconductor substrate, the separation section is kept at the lowest potential of the potential used, and when the semiconductor substrate of one conductivity type is a P-type semiconductor substrate, the separation section is used. The purpose is to use it by keeping it at the highest potential.

FIG. 2 is a sectional view of one embodiment of the present invention.

In FIG. 2, a separation section 30 consisting of a P well 2', a P type diffusion layer 4' and an electrode 6' is formed between the digital circuit section 10 and the analog circuit section 20. When this C-MOS integrated circuit is used, the lowest potential used in this C-MOS integrated circuit is applied to the electrode 6'.

According to such a C-MOS integrated circuit and its usage method, for example, electrical noise generated in the digital circuit section 10 is cut off by the separation section 30 and does not reach the analog circuit section 20. That is, if the electrical noise is composed of positive charges, it will be absorbed by the P-well 2' and extracted to the outside by the electrode 6'. Furthermore, if the electrical noise is composed of negative charges, it will be repelled by the depletion layer formed near the P-well 2' and will not reach the analog circuit section 20.

The above explanation deals with the case where a C-MOS integrated circuit is formed on an N-type semiconductor substrate.
When a MOS integrated circuit is formed on a P-type semiconductor substrate, the influence of electrical noise can be eliminated in the same manner as described above by keeping the electrodes of the isolation portion at the highest potential used.

As explained in detail above, according to the present invention,
C-, which has a separation section between the digital circuit section and the analog circuit section to eliminate electrical noise.
Depending on the type of MOS integrated circuit and the substrate of this C-MOS integrated circuit, a method of using a C-MOS integrated circuit that eliminates the influence of electrical noise can be obtained by keeping the electrode of the isolation part at the lowest or highest potential used. So the effect is big.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an example of a conventional C-MOS integrated circuit having a digital circuit section and an analog circuit section, and FIG. 2 is a sectional view of an embodiment of the present invention. 1... N type semiconductor substrate, 2, 2'... P well, 3... N type diffusion layer, 4, 4'... P type diffusion layer, 5... Oxide film, 6, 6'... Electrode, 10...
Digital circuit section, 20...Analog circuit section, 3
0... Separation part.

Claims (1)

[Claims] 1. A digital circuit section and an analog circuit section formed on one conductivity type semiconductor substrate, and the digital circuit section and the analog circuit section formed between the digital circuit section and the analog circuit section. C--, characterized in that it includes a separation section having an opposite conductivity type diffusion layer for separation and an electrode connected to the diffusion layer.
MOS integrated circuit. 2. A digital circuit section and an analog circuit section formed on a semiconductor substrate of one conductivity type, and an opposite conductivity formed between the digital circuit section and the analog circuit section for separating the digital circuit section and the analog circuit section. A C-MOS comprising a type diffusion layer and a separation section having an electrode connected to the diffusion layer.
When the semiconductor substrate of one conductivity type of the integrated circuit is an N-type semiconductor substrate, the separation portion is kept at the lowest potential of the used potential, and when the semiconductor substrate of one conductivity type is a P-type semiconductor substrate, the separation portion is kept at the lowest potential of the use potential. A method of using a C-MOS integrated circuit characterized by maintaining it at the highest potential.