JPS6259336B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a buffer control method in a data processing device for performing data transfer processing between a data transmission line and a main memory in a main processing device. In particular, the present invention relates to a buffer control method that allows more efficient transfer processing when the length of data blocks received from a transmission path is variable.

[Background of the invention]

In the transmission line connected to the computer, for example, HDLC
Data blocks are transferred based on the system, and this transmission path and the main memory of the computer are connected by a data processing device (also called a channel). This data processing device usually uses a microcomputer, but since the computer input/output path and the microcomputer bus inside the data processing device have different interfaces, the received data is temporarily stored in the buffer memory inside the data processing device. After that, it is transferred to main memory. In this case, the data processing device must receive the data block sent from the transmission path without losing it, so the transfer speed between the reception buffer and the main memory must be faster than the transmission speed of the data transmission path. However, even if this condition is met, the following problems still occur. In other words, if the length of the transmitted data to be received is variable and the difference between the maximum length and the minimum length of the data is extremely large, two reception It is necessary to use a high-speed DMA control circuit to alternately use buffers and keep the time to transfer the longest received data to main memory less than the transmission time of the minimum length transmission path data, which requires a large amount of hardware. The disadvantage is that it increases. On the other hand, if a method is used in which the transfer with the main memory is performed by intervening a microprogram, the
The amount of hardware can be reduced compared to the DMA method, but after receiving the maximum length data, while transferring it to the main memory, multiple variable length blocks of data successively sent from the data transmission path are received. You will need a buffer to do this. The number of buffers for this purpose can be determined from the relationship between the transfer time of maximum length data to main memory and the transmission time of minimum length data, but the size of each reception buffer cannot be predicted before receiving variable length data. , has to be configured with the maximum size, therefore, a large number of maximum length buffers are required, and there is a disadvantage that large capacity buffers with poor usage efficiency must be provided in the data processing device.

[Purpose of the invention]

An object of the present invention is to provide a data processing device that is connected to a data transmission path and has a function of receiving data in blocks sent from a partner device onto the data transmission path and transferring the data in blocks to the main memory of a computer. Therefore, the present invention provides a microprogram-controlled buffer control method that can transfer variable-length block unit data to main memory without losing it using a small amount of buffer memory.

[Summary of the invention]

A feature of the present invention is that by allocating two types of buffer lengths to a group of receive buffers within a data processing device and defining how each receive buffer is used, it is possible to achieve extremely high usage efficiency using a limited buffer memory capacity. This is because buffer control is performed. That is, at least two or more buffers capable of storing data blocks of the maximum received data length are prepared as a first buffer group, and a plurality of dedicated buffer groups capable of storing only short data are prepared as a second buffer group.

Since the length of the received data from the data transmission path cannot be predicted in advance, one of the first buffer groups that can always receive the maximum data length is assigned as the reception buffer, and the data length is detected after data reception is completed. However, if the buffer length is smaller than the buffer length of the second buffer group, the received data is copied from the first receive buffer group to a second dedicated buffer group that can store only short data, and the main buffer of these short receive block data is Transfer to storage uses a second dedicated buffer group. If the received data is larger than the second buffer length, it is not copied to the second dedicated buffer group, and the first buffer group is directly used for transfer with the main memory.

[Embodiments of the invention]

An embodiment of the present invention will be shown below. FIG. 1 shows a data transmission path 2, a main processing device 3, and a main memory 4 connected via a data processing device 1 according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a system in which a CPU input/output bus 5 is connected. FIG. 2 is a block diagram showing an embodiment of the data processing device 1. The EDLC control circuit 17 assembles the received data bit-serially input from the data transmission path 2 into byte units and outputs them to the microcomputer bus 16. This received data in bytes is sent to the DMAC circuit 1 which controls the address and number of stored bytes.
5, the reception buffer memory 18
stored at high speed. Microcomputer 1
2 performs various controls to realize the functions of this data processing device by means of microprograms stored in the ROM 13. The bus interface control circuit 11 is a reception data buffer memory 1 that temporarily stores the reception data from the HDLC control circuit 17.
8 is transferred to the main memory of the main processing unit via the CPU input/output bus 5. The reception data buffer memory 18 includes a first reception buffer group 181,1 having a buffer length equal to the maximum length of reception data.
82, a management table 183 for managing reception completion and free space, and a second reception buffer group 184 having a buffer length equal to the minimum length of reception data.
- 186 and a management table 187 for managing their reception completion and availability. Also ROM1
3 includes a block reception completion processing microprogram 131 for processing received data stored in the reception buffer memory 18 from the HDLC control circuit 17 in block units under the control of the DMAC 15;
There is a received buffer main memory transfer processing microprogram 132 for transferring the received data stored in the received data buffer memory 18 to the main memory of the main processing unit in block units. control signal 12
0, 121, and 122 release the internal microcomputer data bus 16 from the microprogram operation and leave it to the control of the DMAC 15 when storing the received data in units of bytes from the HDLC control circuit 17 in the reception data buffer memory 18 at high speed. This is a control signal necessary for the clock reception completion interrupt 14.
is for communicating this to the microcomputer 12 when the HDLC control circuit 17 detects a flag pattern indicating the end of the received data block in the HDLC system.

Prior to the detailed operation of the data processing apparatus described above, the global operation of this apparatus will be explained with reference to the time chart shown in FIG. First, the data block received from data transmission path 2 is B ₁ (long),
The order is B ₂ (short), B ₃ (short), B ₄ (short), B ₅ (long). These data blocks are sequentially transferred to DMAC1.
5 to any long data buffer in the reception data buffer memory 18, and the block reception completion processing microprogram 131 and received buffer main memory transfer processing, which will be explained later with reference to FIGS. 4 and 6, are performed. Processed by microprogram 132. That is, since block B ₁ is a long data block, it is stored as is in the buffer 181 of the first receiving buffer group that received it from the data transmission path, and is transferred from the buffer 181 by interrupt 14 when the reception of this data block B ₁ is completed. It is transferred to the main memory 4 at transfer time _T1 . Thereafter, short data blocks _B2 to _B4 are successively received from the data transmission path 2, but since the data processing device cannot know in advance that the data block length is short, they are all received from the first long receiving buffer group. These are temporarily stored in the free buffer 182, and then
Upon completion of reception of each of B ₂ , B ₃ , and B ₄ , the data processing device learns that the currently received data block is short by the interruption of the block reception completion signal 14 , and transfers these blocks from the buffer 182 to the second block. The received buffers 184 to 186 are successively copied. These copied data blocks are then transferred to the main memory 4 during transfer times _T2 to _T4 . The following operations are similar, but here, if _{the second data} block is
If it is decided not to copy data to the short receiving buffer group, a large amount of the first long buffer group must be reserved even though short data block groups are being sent continuously, and a large capacity buffer memory is required. will be wasted.

FIG. 4 is a flowchart of buffer control by the block reception completion processing microprogram 131, which is controlled by the interrupt signal 14 sent from the HDLC control circuit 17 every time the reception of a data block from the transmission path 2 is completed, as described above. will be activated. In this program, first the received data block length is
Calculate DC in steps 200 and 201. DMAC15
First, when inputting the received data to one of the long buffers BL, the data length n ₀ of the long buffer is set as the initial value, and the received data length is subtracted to count the remaining data length n. In step 201, the received data length DC is calculated from DC=n ₀ -n. Next, step 202 calculates the second reception buffer length _m0 and reception data length DC.
If DC≦m ₀ , refer to the empty management table 187 of the second buffer group and select one of the empty buffers.
The BS is extracted in step 203, the data in the buffer BL is copied therein in step 204, and the buffer BS is registered in the received management table 187 in step 205 to mark it as received. Furthermore, in order to make the data transmission path 2 receivable, the starting address and number of stored bytes of the first buffer BL used up to now are set in the DMAC 15 in step 206. If the received data length DC is greater than or equal to the second received buffer length _m0 in step 202, the first received buffer BL is registered in the received management table 183 in step 207 without copying the received data, and another The start address and number of stored bytes of one data buffer are set in the DMAC 15 in step 208, and the interrupt operation is completed. FIG. 5 shows a configuration example of the management tables 183 and 187 indicating the empty status and received status of the reception data buffers in the first data buffer group and the second data buffer group, and the reception buffers.

FIG. 6 shows a flowchart of the microprogram 132 for transferring data from the buffer to the main memory that is determined to have been received by the program processing of FIG. This microprogram operates with interrupts canceled at all times in order to operate simultaneously with the block reception completion processing microprogram 131, and transfers the received data buffer data from the first or second receive buffer group to the bus interface control circuit 11. Main memory 4 of the main processing unit via
Transfer to. That is, in steps 300 and 301, the management tables 183 and 187 are referred to to find out whether there is a received data buffer and which buffer it is, and in either case, step 302 or
In step 303, the contents of the buffer are transferred to the main memory, and then in step 304 or 305, the received buffer is returned to the empty management table of management table 183 or 187, and the status of the next received data buffer is continued to be monitored. Data transfer is performed continuously.

〔Effect of the invention〕

According to the present invention, in a data processing device such as an HDLC communication device that has the function of transmitting and receiving data in blocks, the received data can be transferred using a small amount of buffer without the need to particularly speed up the transfer capability with the main memory in the main processing device. This has the advantage that efficient buffer control can be performed without loss of performance, and the amount of hardware in the device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram to which the data processing device of the present invention is connected, FIG. 2 is a block diagram showing an embodiment of the data processing device of the present invention, and FIG. 3 is a diagram showing reception from the data transmission path by the device. A time chart showing the method of transferring data to the main memory, Figure 4 is a flowchart of the microprogram for storing received data in each buffer, Figure 5 is an explanatory diagram of the reception buffer management table, and Figure 6 is the main This is a flowchart of a microprogram for data transfer to and from memory. 1...Data processing device, 4...Main memory, 12...
...Microprocessor, 13...ROM, 18...
...Reception buffer, 181, 182, 184, 18
5,186...Buffer, 183,187...Management table, 131...Block reception completion processing microprogram, 132...Received buffer main memory transfer processing microprogram.

Claims (1)

[Claims] 1. In a buffer control method within a data processing device configured to receive data sent from the outside in variable-length blocks once into its internal buffer memory and then transfer it to the main storage device, each a first buffer group in which the buffers have a length capable of storing a maximum length data block; and a second buffer group in which each buffer has a buffer length shorter than the buffer length of the first buffer group. , a reception completion processing means, and a transfer processing means are provided, and once the input data block is received in one of the empty buffers of the first buffer group, the length of the received data block is set as above. When the buffer length of the second buffer group is not exceeded, the received data block is transferred to one of the empty buffers of the second buffer group and the reception is completed, and the length of the received data block is equal to the length of the buffer of the second buffer group. When the buffer length of the second buffer group is exceeded, the reception completion processing means is controlled to complete the reception without performing the above transfer, and furthermore, when there is a buffer whose reception has been completed, the data stored in the buffer is 1. A buffer control method, characterized in that the transfer processing means is controlled to transfer a block to a main storage device and make the buffer an empty buffer.