JPS6259396B2 - - Google Patents
Info
- Publication number
- JPS6259396B2 JPS6259396B2 JP54011165A JP1116579A JPS6259396B2 JP S6259396 B2 JPS6259396 B2 JP S6259396B2 JP 54011165 A JP54011165 A JP 54011165A JP 1116579 A JP1116579 A JP 1116579A JP S6259396 B2 JPS6259396 B2 JP S6259396B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- control means
- signal
- control
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】
〈技術分野〉
本発明は電子機器内の記憶装置としてダイナミ
ツクメモリ（ダイナミツクRAM）を装備する場
合の該メモリリフレツシユの為の駆動装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a drive device for memory refresh when a dynamic memory (dynamic RAM) is installed as a storage device in an electronic device.
特に本発明は前記ダイナミツクメモリのリフレ
ツシユを通常の動作モードと電池によるバツクア
ツプ時のモードとではその制御系を変え、個々の
モードで最適な回路を構成させ、小型の電池でも
長期のメモリバツクアツプを可能とし、該ダイナ
ミツクメモリの応用範囲の拡大に奇与できるよう
にしたものである。 In particular, the present invention changes the control system for refreshing the dynamic memory between the normal operating mode and the battery backup mode, configures an optimal circuit for each mode, and enables long-term memory backup even with a small battery. This makes it possible to expand the range of applications of the dynamic memory.
〈従来技術〉
最近、ダイナミツクメモリとしてのダイナミツ
クRAM（ランダムアクセスメモリ）はその他の
RAM（スタテイク、Ｃ−MOS等）に較べてメモ
リ容量が大きく、低価格化によつて比較的小型の
電子機器にも用いられるようになつたが、その性
質上データ保持のためのメモリリフレツシユが必
要であること、そのための周辺回路が複雑である
こと、またダイナミツクRAM自体の消費電力が
Ｃ−MOS RAMに較べて非常に大きいために殆
どの用途がメモリバツクアツプ（BACKUP）を
必要としない外部メモリ若しくはそのバツフアメ
モリに限定されて使用されていた。<Prior art> Recently, dynamic RAM (random access memory) has been used as a dynamic memory.
It has a larger memory capacity than RAM (static, C-MOS, etc.), and as prices have fallen, it has come to be used in relatively small electronic devices, but due to its nature, memory refresh for data retention is required. Most applications do not require memory backup (BACKUP) because the peripheral circuitry required for it is complex, and the power consumption of dynamic RAM itself is much larger than that of C-MOS RAM. Its use was limited to external memory or its buffer memory.
一方、メモリバツクアツプを必要とする使用の
場合にはこのダイナミツクRAM周辺回路に必要
な電源のAC入力をOFFしない方式（常時AC入
力をダイナミツクRAM周辺回路の電源部に供給
させる方式）、或いは大容量の電池によつて装置
全体のバツクアツプを行つているのが一般的であ
つた。 On the other hand, in cases where memory backup is required, a method that does not turn off the AC input of the power supply required for this dynamic RAM peripheral circuit (a method that constantly supplies AC input to the power supply section of the dynamic RAM peripheral circuit), or a method that It was common for the entire device to be backed up by a high-capacity battery.
この前者のものではダイナミツクRAM周辺回
路に装置（機器）のAC電源入力と別個に今一つ
のAC電源入力を必要として回路構成が複雑化し
高価にもなる。また後者についてはその概略構成
を第１図に示し、今少し説明する。 In the former case, the dynamic RAM peripheral circuit requires an AC power input separate from the device's AC power input, making the circuit configuration complicated and expensive. Regarding the latter, its schematic configuration is shown in FIG. 1, and will be briefly explained.
この第１図において、装置１にはAC側電源２
が電力供給されていると共にこのAC側電源２の
動作状態を検出手段４で検出している。そして、
装置１はこの演算制御部（CPU）５によつて制
御され、該演算制御部（CPU）５の動作に従つ
てダイナミツクRAM７の制御回路６がデータの
書込み、読出時のRAM選択やアドレス指定、メ
モリリフレツシユ等の動作を行う。 In this Figure 1, the device 1 includes an AC power source 2.
is being supplied with power, and the operating state of this AC side power supply 2 is detected by the detection means 4. and,
The device 1 is controlled by the arithmetic control unit (CPU) 5, and according to the operation of the arithmetic control unit (CPU) 5, the control circuit 6 of the dynamic RAM 7 performs RAM selection and address designation during data writing and reading. Performs operations such as memory refresh.
また、上記装置１には電池電源３からも電源供
給されるようになつており、上記検出手段４が
AC側電源２が非動作状態になつた時に電池電源
３を動作させて該電源３から装置１に電力供給し
そして演算制御部（CPU）５のもとにダイナミ
ツクRAM７をリフレツシユさせるものである。 Further, the device 1 is also supplied with power from a battery power source 3, and the detection means 4 is
When the AC side power source 2 becomes inactive, the battery power source 3 is activated, power is supplied from the power source 3 to the device 1, and the dynamic RAM 7 is refreshed under the control of the arithmetic and control unit (CPU) 5.
〈従来技術の問題点〉
従つて、このものでは電池電源３によるバツク
アツプ時に装置１全体のバツクアツプを必要とす
るので大容量の電池を必要とし、しかも高価にな
るという問題を有している。<Problems with the Prior Art> Accordingly, this method requires backup of the entire device 1 when backed up by the battery power source 3, which requires a large capacity battery and is also expensive.
〈発明の目的〉
本発明は上記した電池電源でバツクアツプさせ
る場合に、特にダイナミツクメモリのリフレツシ
ユタイミング信号の出力時のみ電力供給させるよ
うになし、その結果バツクアツプ時に不要な回路
に電力供給をすることなく、小型電池でも長期の
メモリバツクアツプを可能としたものである。<Object of the Invention> The present invention is designed to supply power only when a dynamic memory refresh timing signal is output when backing up using the above-mentioned battery power supply, and as a result, power is supplied to unnecessary circuits during backup. This enabled long-term memory backup even with a small battery.
〈実施例〉
以下本発明について説明すると、第２図は本発
明に係るブロツク回路図を示しており、図におい
て２１は各種制御信号を発生し、データ処理を行
なう演算制御部（CPU）であつてデータバスラ
インL9を介してダイナミツクRAM２７と接続
し、また該制御部には本体電源（AC電源）２２
と、この電源の異常状態を検出する電源異常検出
回路２３、第１の制御手段２４、第３の制御手段
２６更には後述する検出回路３０がそれぞれ接続
されている。<Embodiment> To explain the present invention below, FIG. 2 shows a block circuit diagram according to the present invention. The controller is connected to the dynamic RAM 27 via the data bus line L9 , and the control unit is connected to the main body power supply (AC power supply) 22.
A power supply abnormality detection circuit 23, a first control means 24, a third control means 26, and a detection circuit 30, which will be described later, are connected to the power supply abnormality detection circuit 23, which detects an abnormal state of the power supply.
上記第１の制御手段２４は本体電源２２の電力
供給により動作状態となり、上記演算制御部２１
の動作と相俟つて即ち演算制御部２１からの制御
バスラインL3を介する制御信号に応答してダイ
ナミツクRAM２７に対するデータの書込み或い
はデータの読出し時のRAM選択・メモリリフレ
ツシユ等のタイミング信号の発生及び書込み、読
出し制御を行うものであつて、たとえばライン
L1にリフレツシユ信号を出力し、ラインL11に書
込み、読出しの指示信号を出力し、また、ライン
L2にメモリアクセス或いはメモリリフレツシユ
のタイミング信号を出力し、更にラインL8にク
ロツク信号を出力する。 The first control means 24 is brought into operation by power supply from the main body power supply 22, and the arithmetic control section 21
In conjunction with the operation of , that is, in response to a control signal from the arithmetic control unit 21 via the control bus line L3 , timing signals for RAM selection, memory refresh, etc. are generated when writing data to or reading data from the dynamic RAM 27. and performs write and read control, for example, line
A refresh signal is output to line L1 , a write/read instruction signal is output to line L11 , and a refresh signal is output to line L11.
A timing signal for memory access or memory refresh is output to line L2 , and a clock signal is further output to line L8 .
一方、上記第３の制御手段２６の場合、本体電
源２２の電力供給により動作状態となつた時（通
常モード時と称す。）は、上記演算制御部２１、
第１の制御手段２４及び第２の制御手段２５から
ラインL2，L3，L6を介して転送されてくるメモ
リアクセス或いはメモリリフレツシユのタイミン
グ信号、メモリアクセスのアドレス制御信号、メ
モリリフレツシユのアドレス制御信号等に応答し
てラインL4にメモリアクセス或いはメモリリフ
レツシユのアドレス信号を出力するように動作し
また電池電源（DC電源）２９の電力供給により
動作状態となつた時（バツクアツプモード時と称
す。）は、第２の制御手段２５からラインL5，L6
を介して転送されてくるメモリリフレツシユのタ
イミング信号及びメモリリフレツシユのアドレス
制御信号に応答してラインL4にメモリリフレツ
シユアドレス信号を出力するように動作するもの
である。 On the other hand, in the case of the third control means 26, when the main body power supply 22 supplies power to the operating state (referred to as normal mode), the arithmetic control section 21,
Memory access or memory refresh timing signals, memory access address control signals, and memory refresh signals transferred from the first control means 24 and the second control means 25 via lines L 2 , L 3 , and L 6 It operates to output a memory access or memory refresh address signal to line L4 in response to an address control signal, etc. of mode), the lines L 5 and L 6 are connected from the second control means 25.
It operates to output a memory refresh address signal to line L4 in response to a memory refresh timing signal and a memory refresh address control signal transferred via the memory refresh address control signal.
ここで、第３の制御手段２６への電池電源２９
の電力供給は上記第２の制御手段２５が出力する
メモリリフレツシユのタイミング信号の出力時の
みとなつており、この制御は該タイミング信号を
導入する電源制御手段２８によつて行われる。 Here, the battery power supply 29 to the third control means 26
Power is supplied only when the second control means 25 outputs the memory refresh timing signal, and this control is performed by the power supply control means 28 which introduces the timing signal.
第２の制御手段２５は本体電源２２或いは電池
電源２９の電力供給により動作状態となるが、本
体電源２２によつて動作状態となつた時は第１の
制御手段２４からのクロツク信号をラインL8を
介して受入し、ラインL6にメモリリフレツシユ
のアドレス制御信号を出力し、また電池電源２９
により動作状態となつた時はラインL5，L6，L7
にそれぞれメモリリフレツシユのタイミング信
号、メモリリフレツシユのアドレス制御信号及び
メモリリフレツシユ信号を出力するように動作す
るものである。従つて、後述するように第２の制
御手段２５は発振器とタイミングカウンターを含
み、前記カウンターは本体電源２２の電源供給時
にはラインL8よりのクロツク信号に基づいて動
作しまた電池電源２９の電力供給時に発振器から
の信号に基づいて動作するようになつている。 The second control means 25 is brought into operation by power supply from the main power supply 22 or battery power supply 29. When the second control means 25 is brought into operation by the main power supply 22, the clock signal from the first control means 24 is sent to line L. 8 , outputs the memory refresh address control signal to line L 6 , and also outputs the memory refresh address control signal to line L 6.
When the operating state is reached, lines L 5 , L 6 , L 7
It operates to output a memory refresh timing signal, a memory refresh address control signal, and a memory refresh signal, respectively. Therefore, as will be described later, the second control means 25 includes an oscillator and a timing counter, and the counter operates based on the clock signal from the line L 8 when the main body power supply 22 is supplied with power, and when the battery power supply 29 is supplied with power. Sometimes they operate based on signals from an oscillator.
また、本体電源２２の異常状態（OFF状態）
を検出する電源異常検出回路２３の検出出力に応
答して動作する演算制御部２１のその動作状態信
号（演算制御部２１のラインL10の出力）に応答
して“Ｈ”レベル又は“Ｌ”レベルの検出信号
を出力する検出回路３０を備えている。上
記検出信号は演算制御部２１、第１の制御
手段２４のリセツト或いはリセツト解除信号とな
り、また第２の制御手段２５の両モード時におけ
る制御動作切換用に寄与する。 Also, the main power supply 22 is in an abnormal state (OFF state).
“H” level or “L” level in response to the operation status signal (output of line L10 of the arithmetic control unit 21) of the arithmetic control unit 21 which operates in response to the detection output of the power supply abnormality detection circuit 23 that detects It includes a detection circuit 30 that outputs a level detection signal. The detection signal serves as a reset or reset release signal for the arithmetic control unit 21 and the first control means 24, and also contributes to switching the control operation of the second control means 25 in both modes.
以上の構成から、まず本体電源２２がON状態
の時（通常モード時）には演算制御部２１、第１
の制御手段２４、第２の制御手段２５及び第３の
制御手段２６が上記電源２２からの電力供給によ
り動作してダイナミツクRAM２７に対するデー
タの書込み、読出し制御或いはリフレツシユ制御
が成され、更に上記本体電源２２がOFF状態の
時（バツクアツプモード時）にはバツクアツプ用
電源即ち電池電源２９によつて第２の制御手段２
５、第３の制御手段２６が動作してダイナミツク
RAM２７のリフレツシユを実行するのが理解で
きるであろう。 From the above configuration, first, when the main body power supply 22 is in the ON state (in the normal mode), the arithmetic control section 21 and the first
The control means 24, the second control means 25, and the third control means 26 are operated by the power supply from the power supply 22 to perform data writing, read control, or refresh control on the dynamic RAM 27, and the main body power supply 22 is in the OFF state (backup mode), the second control means 2 is controlled by the backup power supply, that is, the battery power supply 29.
5. The third control means 26 operates to dynamically
It will be understood that the RAM 27 is refreshed.
次に具体的な回路構成及び各種信号のタイムチ
ヤートを第３、第４図に示し、今少し説明すると
まず第３図において〓で示すものはダイナミツク
RAM（図示せず）への信号、Ｖは本体電源２
２、ＶBはバツクアツプ用電池電源２９を示す。 Next, the specific circuit configuration and time charts of various signals are shown in Figs. 3 and 4. To explain a little more, first of all, in Fig.
Signal to RAM (not shown), V is main unit power supply 2
2. V B indicates a backup battery power source 29.
そこで今、第４図１に示すように本体電源Ｖが
動作状態にある通常モード区間では演算制御部
（CPU）２１、第１の制御手段（CS−
CONTROL回路）２４、第２の制御手段
（REFRESH−CONTROL回路）２５及び第３の
制御手段（ADRESS−MULTIPLEXER回路）２
６が上記本体電源Ｖの電力供給により動作状態に
ある。なお第４図において、２は電池電源ＶB、
４は第１の制御手段２４への供給電源、５は第２
の制御手段２５への供給電源、７は第３の制御手
段２６への供給電源のタイムチヤートを示す。 Therefore, as shown in FIG.
CONTROL circuit) 24, second control means (REFRESH-CONTROL circuit) 25, and third control means (ADRESS-MULTIPLEXER circuit) 2
6 is in an operating state due to the power supply from the main body power source V. In addition, in FIG. 4, 2 is a battery power source V B ,
4 is a power supply to the first control means 24, and 5 is a power supply to the second control means 24.
7 shows a time chart of the power supply to the third control means 26.
一方、この時には電源異常検出回路２３におい
て本体電源Ｖの異常が検出されないから、上記
CPU２１からの状態信号に基づいて本体電源Ｖ
の動作状態を検出する検出回路３０からは第４図
３に示すように“Ｈ”の検出信号が出力さ
れ、この検出信号はCPU２１、第１の制御
手段（CS−CONTROL回路）２４、第２の制御
手段（REFRESH−CONTROL回路）２５及び
アンドゲート３７にそれぞれ印加される。該検出
信号を導入したCPU２１ではリセツト状態
が解除され、更に発振器とこの発振器出力により
動作するタイミングカウンターにて構成される第
２の制御手段（REFRESH−CONTROL回路）
２５では第１の制御手段（CS−CONTROL回
路）２４からラインL8を介して送られてくるク
ロツク信号に基づいてカウンターが動作するよう
に切換制御される。 On the other hand, at this time, the power supply abnormality detection circuit 23 does not detect any abnormality in the main body power supply V.
Based on the status signal from the CPU21, the main body power supply V
As shown in FIG. 4, the detection circuit 30 which detects the operating state of the circuit outputs an "H" detection signal, and this detection signal is sent to the CPU 21, the first control means (CS-CONTROL circuit) 24, and the second control means (CS-CONTROL circuit). is applied to the control means (REFRESH-CONTROL circuit) 25 and the AND gate 37, respectively. The reset state is released in the CPU 21 into which the detection signal is introduced, and a second control means (REFRESH-CONTROL circuit) consisting of an oscillator and a timing counter operated by the output of this oscillator is activated.
At 25, switching control is performed so that the counter operates based on a clock signal sent from the first control means (CS-CONTROL circuit) 24 via line L8 .
したがつてCPU２の制御動作に伴つて制御バ
スラインL3を介する制御信号に基づき第１の制
御手段（CS−CONTROL回路）２４はラインL1
を介してアンドゲート３７にリフレツシユ信号を
出力し、この出力タイミングでノアゲート３８か
らダイナミツクRAMに対してリフレツシユ信号
を導出すると共に、ラインL11，L8，L2にそ
れぞれ書込み、読出しの指示信号、クロツク信
号、メモリリフレツシユ或いはメモリアクセスの
タイミング信号を出力する。一方第２の制御手段
（REFRESH−CONTROL回路）２５はラインL6
にメモリリフレツシユのアドレス制御信号を出力
するように動作し、更に第３の制御手段
（ADRESS−MULTIPLEXER回路）２６ではラ
インL2，L6，L3を介して転送されてくるメメモ
リリフレツシユ或いはメモリアクセスのタイミン
グ信号、メモリリフレツシユのアドレス制御信
号、メモリアクセスのアドレス制御信号を導入し
てラインL4にメモリアクセス或いはメモリリフ
レツシユのアドレス信号を出力するように動作し
てダイナミツクRAM２７に対するデータの書込
み、読出し制御或いはリフレツシユ制御が実行さ
れる。 Therefore, in accordance with the control operation of the CPU 2, the first control means (CS-CONTROL circuit) 24 operates on the line L1 based on the control signal via the control bus line L3 .
A refresh signal is output to the AND gate 37 through the output timing, and at this output timing, a refresh signal is derived from the NOR gate 38 to the dynamic RAM, and write and read instruction signals are sent to the lines L11 , L8 , and L2 , respectively. It outputs a clock signal, memory refresh or memory access timing signal. On the other hand, the second control means (REFRESH-CONTROL circuit) 25 is connected to the line L 6
The third control means ( ADRESS - MULTIPLEXER circuit) 26 operates to output a memory refresh address control signal to It inputs a memory access timing signal, a memory refresh address control signal, and a memory access address control signal, and outputs a memory access or memory refresh address signal to line L4 , thereby controlling the data for the dynamic RAM 27. Write, read control or refresh control is executed.
一方、第４図１のバツクアツプモード区間に示
すように本体電源Ｖが非動作状態になると第４図
４に示すように第１の制御手段（CS−
CONTROL回路）２４への電力供給がストツプ
し、更に第２の制御手段（REFRESH−
CONTROL回路）２３及び第３の制御手段
（ADRESS−MULTIPLEXER回路）２６への電
力供給は電池電源ＶBから行われるようになる
が、まずCPU２１では電源異常検出回路２３に
よつて検出された本体電源Ｖの電源異常信号に基
づいてSTOP命令を実行し、検出回路３０にハル
ト命令を出力する。検出回路３０ではそのハルト
命令によつて第４図３に示すような“Ｌ”の検出
信号を出力し、この検出信号を受けた
CPU２１及び第１の制御手段２４はリセツトさ
れ、更に第２の制御手段（REFRESH−
CONTROL回路）２５は今までクロツク信号に
よつて動作していたカウンターを発振器の出力で
動作するように切換制御される。 On the other hand, when the main body power supply V becomes inactive as shown in the backup mode section of FIG. 4, the first control means (CS-
The power supply to the CONTROL circuit) 24 is stopped, and the second control circuit (REFRESH-
CONTROL circuit) 23 and the third control means (ADRESS-MULTIPLEXER circuit) 26 are now supplied with power from the battery power supply VB . A STOP command is executed based on the power supply abnormality signal of V, and a HART command is output to the detection circuit 30. The detection circuit 30 outputs an "L" detection signal as shown in FIG. 4 according to the Hart command, and receives this detection signal.
The CPU 21 and the first control means 24 are reset, and the second control means (REFRESH-
CONTROL circuit 25 is controlled so that the counter, which has been operated by the clock signal, is now operated by the output of the oscillator.
したがつて上記第２の制御手段（REFRESH−
CONTROL回路）２５はラインL6，L5，L7にそ
れぞれメモリリフレツシユのアドレス制御信号、
メモリリフレツシユのタイミング信号（第４図６
を参照）及びメモリリフレツシユ信号を出力す
る。そしてメモリリフレツシユ信号はノアゲート
３８に印加され、該ノアゲートからはメモリリフ
レツシユ信号が出力してダイナミツクRAM
に転送される。 Therefore, the second control means (REFRESH-
CONTROL circuit) 25 has address control signals for memory refresh on lines L 6 , L 5 , and L 7 , respectively.
Memory refresh timing signal (Fig. 4 6)
) and outputs a memory refresh signal. The memory refresh signal is applied to the NOR gate 38, and the memory refresh signal is output from the NOR gate to update the dynamic RAM.
will be forwarded to.
一方、第３の制御手段（ADRESS−
MULTIPLEXER回路）２６では上記第２の制御
手段２５が出力するメモリリフレツシユのタイミ
ング信号（第４図６参照）の出力時のみ電池電源
ＶBの電力がアンドゲート３６で構成される電源
制御手段２８から供給されて動作状態となり（第
４図６と７を参照）、このとき転送されてきたメ
モリリフレツシユのアドレス制御信号によつて所
定のメモリリフレツシユのアドレス信号をライン
L4に出力し、このアドレス信号と上記リフレツ
シユ信号によつてダイナミツクRAMのリフレツ
シユ制御が実行されることになる。 On the other hand, the third control means (ADRESS-
In the MULTIPLEXER circuit (MULTIPLEXER circuit) 26, only when the memory refresh timing signal (see FIG. 4, 6) outputted by the second control means 25 is output, the power of the battery power source V (see Figure 4, 6 and 7), and the memory refresh address control signal transferred at this time causes a predetermined memory refresh address signal to be set on the line.
This address signal and the refresh signal are used to perform refresh control of the dynamic RAM.
以上のようにして、本体電源Ｖの動作時はこの
本体電源Ｖの電力にてCPU２１及び上記第１、
第２、第３の各制御手段２４，２５，２６を動作
せしめてデータの書込み、読出し制御或いはダイ
ナミツクRAMのリフレツシユ制御を実行し、一
方、上記本体電源Ｖの非動作時は電池電源ＶBの
電力にて第２の制御手段（REFRESH−
CONTROL回路）２５及び第３の制御手段
（ADRESS−MULTIPLEXER回路）２６のみ動
作せしめてダイナミツクRAMのリフレツシユ制
御を実行することができるわけである。 As described above, when the main body power supply V operates, the CPU 21 and the first,
The second and third control means 24, 25, and 26 are operated to execute data write/read control or dynamic RAM refresh control, while when the main body power supply V is not operating, the battery power supply VB is The second control means (REFRESH-
By operating only the CONTROL circuit 25 and the third control means (ADRESS-MULTIPLEXER circuit) 26, refresh control of the dynamic RAM can be performed.
〈効果〉
以上の様に本発明によれば、ダイナミツクメモ
リのリフレツシユを通常の動作モードと電池によ
るバツクアツプ時のモードとではその制御系を変
え、個々のモードで最適な回路を構成させるよう
にしたので、小型の電池でも長期のメモリバツク
アツプが可能となり、該ダイナミツクメモリの応
用範囲の拡大に寄与できる。特に、バツクアツプ
時における第３の制御手段への電池電源の電力供
給は第２の制御手段が出力するメモリリフレツシ
ユのタイミング信号の出力時のみ行うようにした
のでバツクアツプ用電源の消費電力を極力押える
ことができるという特徴を有する。<Effects> As described above, according to the present invention, the control system for dynamic memory refresh is changed between the normal operation mode and the battery backup mode, and an optimal circuit is configured for each mode. Therefore, long-term memory backup is possible even with a small battery, which can contribute to expanding the range of applications of the dynamic memory. In particular, the battery power supply to the third control means during backup is performed only when the memory refresh timing signal is output from the second control means, thereby minimizing the power consumption of the backup power supply. It has the characteristic of being able to
第１図は従来の駆動装置の回路例、第２図は本
発明に係るブロツク回路例、第３図は同具体的な
回路例、第４図は同各種信号のタイムチヤート例
を示す。
２１は演算制御部、２２は本体電源、２３は電
源異常検出手段、２４は第１の制御手段、２５は
第２の制御手段、２６は第３の制御手段、２７は
ダイナミツクRAM、２８は電源制御手段、２９
は電池電源、３０は検出回路、３６及び３７はア
ンドゲート、３８はノアゲート、Ｖは本体電源、
ＶBは電池電源。
FIG. 1 shows an example of a circuit of a conventional drive device, FIG. 2 shows an example of a block circuit according to the present invention, FIG. 3 shows a specific example of the same, and FIG. 4 shows an example of a time chart of the various signals. 21 is an arithmetic control unit, 22 is a main power supply, 23 is a power supply abnormality detection means, 24 is a first control means, 25 is a second control means, 26 is a third control means, 27 is a dynamic RAM, and 28 is a power supply. control means, 29
is a battery power supply, 30 is a detection circuit, 36 and 37 are AND gates, 38 is a Noah gate, V is a main body power supply,
VB is a battery power source.
Claims (1)
給をうけて動作状態となり、演算制御部
（CPU）の制御に基づいてダイナミツクメモリに
リフレツシユ信号を出力すると共に第３の制御手
段にメモリリフレツシユのタイミング信号を出力
する第１の制御手段と、 前記本体電源或いは電池電源より電力供給をう
けて動作状態となり、本体電源からの電力供給に
基づいて第３の制御手段にメモリリフレツシユの
アドレス制御信号を出力すると共に電池電源から
の電力供給に基づいてダイナミツクメモリにリフ
レツシユ信号を出力しまた第３の制御手段にメモ
リリフレツシユのタイミング信号及びメモリリフ
レツシユのアドレス制御信号を出力する第２の制
御手段と、 前記本体電源或いは電池電源より電力供給をう
けて動作状態となり、本体電源からの電力供給に
基づいて上記第１の制御手段及び第２の制御手段
から、また電池電源からの電力供給に基づいて上
記第２の制御手段のみから、夫々供給されるリフ
レツシユのタイミング信号とアドレス制御信号に
応答してダイナミツクメモリへアドレス信号を出
力する上記第３の制御手段と、 前記第３の制御手段への電池電源の電力供給を
制御する手段であつて、第２の制御手段から出力
されるメモリリフレツシユのタイミング信号に同
期して該タイミング信号の出力時のみ電力供給さ
せる電源制御手段とを備え、 上記本体電源が動作状態にあるときに、上記第
１、第２、第３の制御手段に該本体電源の電力を
供給させてダイナミツクメモリのリフレツシユを
行わせ、他方本体電源が停止状態にあるときに上
記第２、第３の制御手段に電池電源より電力を供
給させると共にこの第３の制御手段に対しては上
記電源制御手段によりメモリリフレツシユのタイ
ミング信号の出力時のみ電力供給させてダイナミ
ツクメモリのリフレツシユを行わせたことを特徴
とするダイナミツクメモリの駆動装置。[Claims] 1. The device enters the operating state by receiving power from the main power supply (AC power supply) of the device main body, and outputs a refresh signal to the dynamic memory based on the control of the arithmetic control unit (CPU), and also outputs a refresh signal to the third a first control means for outputting a memory refresh timing signal to the control means; It outputs a memory refresh address control signal and also outputs a refresh signal to the dynamic memory based on the power supply from the battery power supply, and also outputs a memory refresh timing signal and a memory refresh address control signal to the third control means. a second control means that outputs a second control means; the third control means outputting an address signal to the dynamic memory in response to a refresh timing signal and an address control signal respectively supplied from only the second control means based on power supplied from a battery power supply; , means for controlling power supply from the battery power supply to the third control means, the power supply being synchronized with a memory refresh timing signal output from the second control means only when the timing signal is output. and a power supply control means for refreshing the dynamic memory by supplying power from the main body power supply to the first, second, and third control means when the main body power supply is in an operating state; On the other hand, when the main body power supply is in a stopped state, power is supplied from the battery power supply to the second and third control means, and the memory refresh timing signal is supplied to the third control means by the power supply control means. A dynamic memory drive device characterized in that the dynamic memory is refreshed by supplying power only during output.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116579A JPS55105893A (en) | 1979-01-31 | 1979-01-31 | Driving unit of dynamic memory |
| DE19803003524 DE3003524C2 (en) | 1979-01-31 | 1980-01-31 | Refresh circuit for a dynamic memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1116579A JPS55105893A (en) | 1979-01-31 | 1979-01-31 | Driving unit of dynamic memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55105893A JPS55105893A (en) | 1980-08-13 |
| JPS6259396B2 true JPS6259396B2 (en) | 1987-12-10 |
Family
ID=11770423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1116579A Granted JPS55105893A (en) | 1979-01-31 | 1979-01-31 | Driving unit of dynamic memory |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS55105893A (en) |
| DE (1) | DE3003524C2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63285372A (en) * | 1987-05-14 | 1988-11-22 | Hitachi Metals Ltd | Fluid controlling valve |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61271694A (en) * | 1985-05-27 | 1986-12-01 | Mitsubishi Electric Corp | Memory device |
| JPH03130987A (en) * | 1989-10-16 | 1991-06-04 | Matsushita Graphic Commun Syst Inc | Image communication equipment |
| JP3302847B2 (en) * | 1994-12-02 | 2002-07-15 | 富士通株式会社 | Storage device |
| JPH1115742A (en) * | 1997-06-19 | 1999-01-22 | Kofu Nippon Denki Kk | Memory refresh control circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS568435B2 (en) * | 1972-09-19 | 1981-02-24 | ||
| DE2415029B2 (en) * | 1974-03-28 | 1977-01-20 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | STORAGE SYSTEM SECURED AGAINST VOLTAGE FAILURE |
-
1979
- 1979-01-31 JP JP1116579A patent/JPS55105893A/en active Granted
-
1980
- 1980-01-31 DE DE19803003524 patent/DE3003524C2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63285372A (en) * | 1987-05-14 | 1988-11-22 | Hitachi Metals Ltd | Fluid controlling valve |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55105893A (en) | 1980-08-13 |
| DE3003524C2 (en) | 1985-01-17 |
| DE3003524A1 (en) | 1980-08-07 |
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