JPS6259893B2 - - Google Patents
Info
- Publication number
- JPS6259893B2 JPS6259893B2 JP56157654A JP15765481A JPS6259893B2 JP S6259893 B2 JPS6259893 B2 JP S6259893B2 JP 56157654 A JP56157654 A JP 56157654A JP 15765481 A JP15765481 A JP 15765481A JP S6259893 B2 JPS6259893 B2 JP S6259893B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon film
- melting point
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置およびその製造方法に関
し、抵抗体の抵抗値を測定しつつ容易に制御する
ことが可能な半導体装置における抵抗体を提供す
ることを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method of manufacturing the same, and an object of the present invention is to provide a resistor in a semiconductor device whose resistance value can be easily controlled while measuring the resistance value of the resistor.
抵抗値の均一性が必要な半導体装置たとえば
Ａ／Ｄ変換器などの抵抗値制御は、一般に抵抗体
および配線層を形成後、レーザートリミングによ
り、多結晶硅素膜などの抵抗体を溶融除去するこ
とにより所定の抵抗値を得る方法にて行なわれて
いる。 To control the resistance value of semiconductor devices that require uniformity of resistance value, such as A/D converters, generally, after forming a resistor and wiring layer, the resistor such as a polycrystalline silicon film is melted and removed by laser trimming. This method is used to obtain a predetermined resistance value.
かかる方法では溶融時の発熱および溶融した抵
抗体の飛散・再付着により抵抗体周辺の素子に悪
影響を及ぼすという欠点があつた。 This method has the disadvantage that the heat generated during melting and the scattering and redeposition of the melted resistor have an adverse effect on elements surrounding the resistor.
また、不純物を拡散した多結晶硅素膜にレーザ
ー照射を行ない抵抗値を下げる方法がある。この
方法では不純物拡散量およびパターンサイズによ
り、ほとんど抵抗値が決まつてしまい、レーザー
照射量による抵抗値制御は困難であつた。 Another method is to irradiate a polycrystalline silicon film with impurities diffused with a laser to lower the resistance value. In this method, the resistance value is almost determined by the amount of impurity diffusion and the pattern size, and it is difficult to control the resistance value by changing the amount of laser irradiation.
本発明は、高融点金属膜上に多結晶半導体膜を
形成し、多結晶半導体膜上に金属配線層を形成す
るとともに、多結晶半導体膜の一部を露出し、こ
の露出部分より容易かつ正確な抵抗値制御を可能
とするものである。 The present invention forms a polycrystalline semiconductor film on a high melting point metal film, forms a metal wiring layer on the polycrystalline semiconductor film, exposes a part of the polycrystalline semiconductor film, and easily and accurately This enables precise resistance value control.
本発明の第１の実施例を第１図にもとづいて説
明する。半導体基板１上の絶縁物膜２上に第１の
高融点金属膜３を形成し所定のパターンを形成し
た後、多結晶硅素膜４を重ねて形成し、所定のパ
ターンを形成する。次に、高融点金属膜３と多結
晶硅素膜４の接続領域上を選択的に露出し、か
つ、多結晶硅素膜４と接続する第２の高融点金属
膜５を形成する。次に、高温熱処理により前記第
１および第２の高融点金属膜３および５のシリサ
イド層（図示せず）を形成し、第１の高融点金属
膜３−シリサイド層−多結晶硅素膜４−シリサイ
ド層−高融点金属膜５よりなる部分を抵抗体とし
て用いる。そして、第２の高融点金属膜５形成
後、多結晶硅素膜４と第１の高融点金属膜３の接
続領域に第１図のごとくレーザーＸの照射を行な
い、界面を溶融し、シリサイド層の膜厚を制御し
所定の抵抗値を得る。 A first embodiment of the present invention will be described based on FIG. After forming a first refractory metal film 3 on an insulator film 2 on a semiconductor substrate 1 to form a predetermined pattern, a polycrystalline silicon film 4 is formed overlying it to form a predetermined pattern. Next, a second high melting point metal film 5 is formed which selectively exposes the connection region between the high melting point metal film 3 and the polycrystalline silicon film 4 and connects to the polycrystalline silicon film 4 . Next, silicide layers (not shown) of the first and second high melting point metal films 3 and 5 are formed by high temperature heat treatment, and the first high melting point metal film 3 - silicide layer - polycrystalline silicon film 4 - The portion consisting of the silicide layer and the high melting point metal film 5 is used as a resistor. After forming the second high melting point metal film 5, the connection region between the polycrystalline silicon film 4 and the first high melting point metal film 3 is irradiated with laser X as shown in FIG. 1 to melt the interface and form a silicide layer. The film thickness is controlled to obtain a predetermined resistance value.
第２の実施例を第２図にもとづいて説明する。
半導体基板１上に形成された拡散層よりなる一導
電体６上に絶縁物膜２を形成し、この絶縁物膜２
に選択的に開孔部を形成し、前記導電体層６を露
出する。露出された導電体層６上に高融点金属膜
７および多結晶硅素膜８を重ねて形成する。高融
点金属膜７と多結晶硅素膜８の接続領域上の多結
晶硅素膜を選択的に露出し、かつ多結晶硅素膜８
の一部と接続するアルミニウム、モリブデンなど
の金属配線層９を形成する。次に、多結晶硅素膜
８と高融点金属膜７の接続領域上からレーザー照
射Ｘを行ない第１の実施例と同様にして接続抵抗
を制御し、所定の抵抗値を得る。なお、金属配線
層９としてアルミニウムなどの低融点金属を用い
た場合、多結晶硅素膜中のアルミニウムの拡散速
度が速く、後の熱処理およびレーザー照射による
温度上昇のため、高融点金属７および金属配線層
９と多結晶硅素膜の接続領域の間隔を大きくして
おく必要がある。 A second embodiment will be explained based on FIG.
An insulating film 2 is formed on a conductor 6 made of a diffusion layer formed on a semiconductor substrate 1, and this insulating film 2
An opening is selectively formed in the conductor layer 6 to expose the conductor layer 6. A high melting point metal film 7 and a polycrystalline silicon film 8 are formed over the exposed conductive layer 6. The polycrystalline silicon film on the connection region between the high melting point metal film 7 and the polycrystalline silicon film 8 is selectively exposed, and the polycrystalline silicon film 8
A metal wiring layer 9 made of aluminum, molybdenum, etc. is formed to be connected to a part of the metal wiring layer 9. Next, laser irradiation is performed on the connection region between the polycrystalline silicon film 8 and the high melting point metal film 7, and the connection resistance is controlled in the same manner as in the first embodiment to obtain a predetermined resistance value. Note that when a low melting point metal such as aluminum is used as the metal wiring layer 9, the diffusion rate of aluminum in the polycrystalline silicon film is fast, and the temperature rises due to subsequent heat treatment and laser irradiation. It is necessary to increase the distance between the connection region between layer 9 and the polycrystalline silicon film.
上記第１および第２の実施例において、第３図
に示すように、多結晶硅素膜８上に選択的に開孔
部１０および１１を形成しておき、開孔部に選択
的に、たとえば開孔部１１のみにレーザー照射し
てもよい。電極配線となる高融点金属膜７と金属
配線層９間の抵抗値は、レーザー末照射領域13と
レーザー照射領域14の抵抗の並列接続となり、レ
ーザー照射領域シリサイド層１４および多結晶硅
素膜８の抵抗値変化が大きくても金属配線層間の
抵抗制御は容易である。 In the first and second embodiments described above, as shown in FIG. 3, openings 10 and 11 are selectively formed on the polycrystalline silicon film 8, and selectively, for example, Only the opening 11 may be irradiated with the laser. The resistance value between the high melting point metal film 7 and the metal wiring layer 9, which will become the electrode wiring, is determined by the parallel connection of the resistances of the laser end irradiation area 13 and the laser irradiation area 14, and the resistance value of the laser irradiation area silicide layer 14 and polycrystalline silicon film 8. Even if the change in resistance value is large, it is easy to control the resistance between metal wiring layers.
以上のようにして、本発明によれば導電体層間
に形成した抵抗体の抵抗値をレーザー照射による
シリサイド層の膜厚制御により制御する。シリサ
イド層の抵抗は多結晶硅素膜の抵抗よりも低く、
したがつてレーザー照射により抵抗体の抵抗値を
低い値に制御することができる。また導電体層間
の接続領域でたて方向に抵抗体を形成するため、
半導体装置の面積を増大させることなく実施でき
る。レーザー照射をシリサイド層の形成に使用
し、多結晶硅素膜の除去は行なわないので従来と
異なり抵抗体周辺の素子に悪影響を及ぼすことは
ない。また本発明の方法で、多結晶硅素膜への不
純物導入を行なつた場合は、レーザー照射により
多結晶硅素膜の抵抗値を制御することができる。 As described above, according to the present invention, the resistance value of the resistor formed between the conductive layers is controlled by controlling the thickness of the silicide layer by laser irradiation. The resistance of the silicide layer is lower than that of the polycrystalline silicon film,
Therefore, the resistance value of the resistor can be controlled to a low value by laser irradiation. In addition, since a resistor is formed in the vertical direction in the connection area between conductor layers,
This can be implemented without increasing the area of the semiconductor device. Since laser irradiation is used to form the silicide layer and the polycrystalline silicon film is not removed, unlike the conventional method, there is no adverse effect on the elements surrounding the resistor. Furthermore, when impurities are introduced into a polycrystalline silicon film using the method of the present invention, the resistance value of the polycrystalline silicon film can be controlled by laser irradiation.
第１図、第２図は本発明の一実施例の抵抗体を
説明するための構造断面図、第３図Ａは本発明の
他の実施例の抵抗体の構造断面図、同Ｂは平面図
である。
１……半導体基板、３，５，７……高融点金属
膜、４，８……多結晶硅素膜、９……金属配線
層。
1 and 2 are structural cross-sectional views for explaining a resistor according to one embodiment of the present invention, FIG. 3A is a structural cross-sectional view of a resistor according to another embodiment of the present invention, and FIG. 3B is a plan view. It is a diagram. 1... Semiconductor substrate, 3, 5, 7... High melting point metal film, 4, 8... Polycrystalline silicon film, 9... Metal wiring layer.
Claims (1)
多結晶硅素膜を形成し、前記多結晶硅素膜上の前
記金属配線層を選択的に除去し、前記多結晶硅素
膜を露出した構造を有することを特徴とする半導
体装置。 ２ 高融点金属膜上に多結晶半導体膜を形成し、
前記多結晶半導体膜上に選択的に高融点金属膜を
形成し、前記多結晶硅素膜へのレーザー照射によ
り抵抗値を制御して前記多結晶硅素膜よりなる抵
抗体を形成することを特徴とする半導体装置の製
造方法。[Claims] 1. A polycrystalline silicon film serving as a resistor is formed between a high melting point metal film and a metal wiring layer, and the metal wiring layer on the polycrystalline silicon film is selectively removed. A semiconductor device characterized by having a structure in which a film is exposed. 2 Forming a polycrystalline semiconductor film on the high melting point metal film,
A resistor made of the polycrystalline silicon film is formed by selectively forming a high melting point metal film on the polycrystalline semiconductor film and controlling the resistance value by irradiating the polycrystalline silicon film with a laser. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56157654A JPS5858753A (en) | 1981-10-02 | 1981-10-02 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56157654A JPS5858753A (en) | 1981-10-02 | 1981-10-02 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5858753A JPS5858753A (en) | 1983-04-07 |
| JPS6259893B2 true JPS6259893B2 (en) | 1987-12-14 |
Family
ID=15654445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56157654A Granted JPS5858753A (en) | 1981-10-02 | 1981-10-02 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858753A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59232456A (en) * | 1983-06-16 | 1984-12-27 | Hitachi Ltd | thin film circuit element |
-
1981
- 1981-10-02 JP JP56157654A patent/JPS5858753A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5858753A (en) | 1983-04-07 |
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