JPS6260848B2 - - Google Patents
Info
- Publication number
- JPS6260848B2 JPS6260848B2 JP54004973A JP497379A JPS6260848B2 JP S6260848 B2 JPS6260848 B2 JP S6260848B2 JP 54004973 A JP54004973 A JP 54004973A JP 497379 A JP497379 A JP 497379A JP S6260848 B2 JPS6260848 B2 JP S6260848B2
- Authority
- JP
- Japan
- Prior art keywords
- impedance
- mixing
- signal
- load
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/58—Anti-side-tone circuits
- H04M1/585—Anti-side-tone circuits implemented without inductive element
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は、２つの信号を混合して加算又は減算
する混合加減算回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mixing addition/subtraction circuit that mixes two signals and adds or subtracts the mixture.
本発明の目的は、第１信号に第２信号を混合加
減算するため、第１信号源の負荷に直列に混合用
インピーダンスを接続するにも拘らず、このイン
ピーダンスの直列挿入損失が極めて小さくなるよ
うにするにある。以下、図面を用いて本発明を具
体的に説明する。 An object of the present invention is to mix and subtract a second signal with a first signal, so that although a mixing impedance is connected in series with the load of the first signal source, the series insertion loss of this impedance is extremely small. It's in the middle of the day. Hereinafter, the present invention will be specifically explained using the drawings.
第１図は本発明の原理を示す基本回路図であ
る。図において、V1，V2はそれぞれ第１及び第
２信号源、Z1は第１信号源V1の負荷、Z2は混合用
インピーダンス、Trは混合用トランジスタ、
r1，r2はバイアス用抵抗である。混合用インピー
ダンスZ2は、抵抗であつてもよく、混合用トラン
ジスタTrのエミツタ負荷となるようトランジス
タTrに接続する。すなわち、トランジスタTrは
エミツタホロワ増幅回路となるように構成する。
第２信号源V2は、このエミツタホロワ回路のベ
ース入力となるように接続するが、実用上差支え
ない程度に低インピーダンスであることが必要で
ある。 FIG. 1 is a basic circuit diagram showing the principle of the present invention. In the figure, V 1 and V 2 are the first and second signal sources, respectively, Z 1 is the load of the first signal source V 1 , Z 2 is the mixing impedance, Tr is the mixing transistor,
r 1 and r 2 are bias resistances. The mixing impedance Z 2 may be a resistor and is connected to the transistor Tr so as to serve as an emitter load of the mixing transistor Tr. That is, the transistor Tr is configured to serve as an emitter follower amplifier circuit.
The second signal source V 2 is connected to serve as the base input of this emitter follower circuit, but it needs to have a low impedance to the extent that there is no problem in practical use.
このような構成において、第１信号源V1によ
る信号電流が負荷Z1と混合用インピーダンスZ2と
を流れるが、インピーダンスZ2の両端に現われる
電圧変化はトランジスタTrのベース・エミツタ
間に与えられ、インピーダンスZ2を流れるコレク
タ電流が変化する。すなわち、インピーダンスZ2
には、第１信号源V1による負荷電流とエミツタ
ホロワTrのコレクタ電流とが重畳して流れる。
しかし、そのコレクタ電流は負荷電流が増せば減
少し、減少すれば増加するので、第１信号源V1
の負荷電流に対してインピーダンスZ2の実効イン
ピーダンスは低くなり、インピーダンスZ2を直列
に挿入したことによる損失が極めて少なくなる。
第２信号源V2からの信号はエミツタホロワTrの
ベース入力に加えられ、エミツタ負荷となるイン
ピーダンスZ2の両端にその信号電圧変化が現わ
れ、第１信号と混合される。混合に際し、第２信
号の位相、振幅は適当に選定することができる。
したがつて、本発明によれば、音響信号の混合、
信号の混合による機器の制御などを効率よく行な
うことができるので、その応用範囲は極めて広
い。 In such a configuration, the signal current from the first signal source V1 flows through the load Z1 and the mixing impedance Z2 , but the voltage change appearing across the impedance Z2 is applied between the base and emitter of the transistor Tr. , the collector current flowing through the impedance Z 2 changes. i.e. impedance Z 2
The load current from the first signal source V1 and the collector current of the emitter follower Tr flow in a superimposed manner.
However, the collector current decreases as the load current increases, and increases as the load current decreases, so the first signal source V 1
The effective impedance of impedance Z 2 becomes low with respect to the load current of , and the loss caused by inserting impedance Z 2 in series becomes extremely small.
The signal from the second signal source V 2 is applied to the base input of the emitter follower Tr, and the signal voltage change appears across the impedance Z 2 serving as the emitter load and is mixed with the first signal. During mixing, the phase and amplitude of the second signal can be appropriately selected.
According to the invention, therefore, mixing of acoustic signals;
Since it is possible to efficiently control equipment by mixing signals, its range of applications is extremely wide.
第２図は、本発明を電話機の側音防止回路に応
用した例を示す回路図である。図において、
L1，L2は電話線接続端子、Ｍは送話器、Ｒは受
話機、Tr1は送話増幅用トランジスタ、Tr2はバ
イアス用定電流FET、Tr3は混合用トランジスタ
である。T1は結合兼整合トランス、T2は整合ト
ランス、C1はバイパス・コンデンサ、C2はデカ
ツプリング・コンデンサ、C3は直流阻止コンデ
ンサ、Ｄはリミツタとして働く非直線素子であ
る。r1，r2はバイアス用抵抗、r3はデカツプリン
グ抵抗、r4は混合用抵抗、ｒは出力調節抵抗であ
る。バイアス回路には、信号に対し負荷とならぬ
よう、また、線間直流電圧の変動に影響されぬよ
う、高インピーダンスのFET定電流回路として
Tr2を用いている。また、送話増幅用トランジス
タTr1はバツフアをも兼ねている。 FIG. 2 is a circuit diagram showing an example in which the present invention is applied to a sidetone prevention circuit for a telephone. In the figure,
L 1 and L 2 are telephone line connection terminals, M is a transmitter, R is a receiver, Tr 1 is a transmission amplification transistor, Tr 2 is a bias constant current FET, and Tr 3 is a mixing transistor. T 1 is a coupling and matching transformer, T 2 is a matching transformer, C 1 is a bypass capacitor, C 2 is a decoupling capacitor, C 3 is a DC blocking capacitor, and D is a nonlinear element that functions as a limiter. r 1 and r 2 are bias resistors, r 3 is a decoupling resistor, r 4 is a mixing resistor, and r is an output adjustment resistor. The bias circuit is a high impedance FET constant current circuit so that it does not become a load on the signal and is not affected by fluctuations in line DC voltage.
Tr 2 is used. Furthermore, the transmission amplification transistor Tr 1 also serves as a buffer.
電話線に送話器Ｍと受話機Ｒが並列に接続さ
れ、電話線には送・受話信号が混在しているの
で、受話機Ｒには自己の送話信号が側音として現
われる。そこで、本例では、受話機回路Ｒ，
T2，ｒ，C3に直列に混合用インピーダンスとし
て抵抗r4を接続し、これを混合用トランジスタ
Tr3のエミツタ負荷とするエミツタホロワ回路を
構成する。そして、送話増幅回路Tr1の入力側か
らトランスT1を介して送話信号を取出し、これ
を混合用トランジスタTr3のベース入力に加え
る。そうすると、混合用抵抗r4の両端に混合用送
話信号電圧が現われるので、その位相、振幅を適
当に選定すれば、受話回路に現われる送話信号を
減衰除去することができる。 A transmitter M and a receiver R are connected in parallel to a telephone line, and since transmitting and receiving signals are mixed on the telephone line, the receiver R's own transmitting signal appears as sidetone. Therefore, in this example, the receiver circuit R,
Connect resistor r4 as a mixing impedance in series with T2 , r, and C3 , and connect this to the mixing transistor.
Configure an emitter follower circuit with the emitter load of Tr 3 . Then, a transmitting signal is taken out from the input side of the transmitting amplifier circuit Tr 1 via the transformer T 1 and is applied to the base input of the mixing transistor Tr 3 . Then, since the mixing transmitting signal voltage appears at both ends of the mixing resistor r4 , by appropriately selecting its phase and amplitude, the transmitting signal appearing in the receiving circuit can be attenuated and removed.
本例において、受話信号（側音を含む。）は第
１図の第１信号源V1による信号電流に、受話回
路は同じく負荷Z1に、混合用抵抗r4は同じく混合
用インピーダンスZ2に、混合用トランジスタTr3
は同じく混合用トランジスタTrに、トランスT1
の２次側に現われる自己の送話信号は同じく第２
信号源V2による信号電流にそれぞれ相当する。
したがつて、本例における側音防止回路は、混合
のために受話回路に直列に抵抗を挿入するにも拘
わらず、この挿入抵抗による実効インピーダンス
が低いので、それによる受話信号の減衰量は極め
て少ない。 In this example, the reception signal (including sidetone) is connected to the signal current by the first signal source V 1 in FIG. 1, the reception circuit is connected to the load Z 1 , and the mixing resistor r 4 is connected to the mixing impedance Z 2. In, mixing transistor Tr 3
is also the mixing transistor Tr, and the transformer T 1
The own transmission signal that appears on the secondary side of the
Each corresponds to the signal current due to the signal source V 2 .
Therefore, although the sidetone prevention circuit in this example inserts a resistor in series with the receiving circuit for mixing, the effective impedance due to this inserted resistance is low, so the amount of attenuation of the receiving signal is extremely small. few.
第１図は本発明の原理を示す基本回路図、第２
図は本発明の実施例を示す回路図である。
V1……第１信号源、Z1……第１信号源V1の負
荷、Z2……混合用インピーダンス、Tr……エミ
ツタホロワ増幅回路用トランジスタ、V2……第
２信号源。
Figure 1 is a basic circuit diagram showing the principle of the present invention, Figure 2 is a basic circuit diagram showing the principle of the present invention.
The figure is a circuit diagram showing an embodiment of the present invention. V1 ...first signal source, Z1 ...load of first signal source V1 , Z2 ...mixing impedance, Tr...transistor for emitter follower amplifier circuit, V2 ...second signal source.
Claims (1)
接続し、上記負荷とインピーダンスの接続点にエ
ミツタを接続して上記インピーダンスをエミツタ
負荷とするエミツタホロワ増幅回路を設け、この
エミツタホロワ回路のベース入力に第２信号源を
接続した混合加減算回路。1. An emitter follower amplifier circuit is provided in which an impedance is connected in series to the load of the first signal source, an emitter is connected to the connection point between the load and the impedance, and the impedance is used as the emitter load, and a second emitter follower amplifier circuit is provided at the base input of the emitter follower circuit. Mixing addition/subtraction circuit with signal sources connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP497379A JPS5597767A (en) | 1979-01-19 | 1979-01-19 | Mixing adder-subtracter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP497379A JPS5597767A (en) | 1979-01-19 | 1979-01-19 | Mixing adder-subtracter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5597767A JPS5597767A (en) | 1980-07-25 |
| JPS6260848B2 true JPS6260848B2 (en) | 1987-12-18 |
Family
ID=11598533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP497379A Granted JPS5597767A (en) | 1979-01-19 | 1979-01-19 | Mixing adder-subtracter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5597767A (en) |
-
1979
- 1979-01-19 JP JP497379A patent/JPS5597767A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5597767A (en) | 1980-07-25 |
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