JPS6261182B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed selection communication system in a digital switching network that enables communication at a plurality of speeds by switching the clock supplied from the network to a terminal.

Conventionally, in a digital switching network in which terminals communicate in synchronization with a clock provided by the network, as shown in FIG. Information transmission and reception at the terminal 1 is performed via an information line 7 in synchronization with a clock supplied via a clock line 6 from a clock supply circuit 5 within the terminal termination unit 2. The clock supplied to the terminal 1 by the clock line 6 is fixed at a certain speed corresponding to the speed of the terminal 1 when the terminal 1 is accommodated in the exchange 4. Therefore, it is not possible to switch the communication speed of the terminal 1 or to connect and communicate with another terminal with a different speed. However, for data exchange network users, if they want to change the communication speed depending on the communication content, or if they want to communicate by changing the speed to match the communication speed with the other party because the communication speed with the other party is different, or There may be a case where a line with a certain speed is busy, so you would like to switch speeds and use a line with an available speed for communication. In order to realize speed switching in accordance with the wishes of subscribers, in the conventional technology, as shown in FIG. As shown in FIG. 3, there is a method of accommodating devices 11, 12, 13 and subscriber lines 14, 15, 16 in the exchange 4, and a terminal 17 having communication functions at multiple speeds. line termination devices 11, 12, 13 and subscriber lines 14, 1
5 and 16 are prepared, and a switch 18 is used to switch between the line termination device and the subscriber line corresponding to the selected speed. In FIGS. 2 and 3, numeral 4 denotes a switch, as in FIG. 1.

However, in the above-mentioned conventional technology, it is necessary to connect multiple subscriber lines and line termination devices with different speeds between the terminal and the exchange, which is extremely uneconomical and inconvenient. It was hot.

The present invention is characterized by transmitting and receiving control signals between a line termination device and an exchange in accordance with a request from a terminal or an exchange, and switching the clock supplied from the network to the terminal, and its purpose is to The purpose of the present invention is to economically realize the selection of a communication speed suitable for the subscriber's wishes or the current state of the network during a call or within a call.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, reference numeral 19 denotes a clock supply circuit 21 that supplies a plurality of clocks, and a clock selection circuit 19, which matches the communication speed of the terminal 17. 22 to the terminal 17, and the multiplexer 23 to the information line 7 and the time division multiplex subscriber line 2.
This is a line terminating device that connects 0 to 0. As an example of the transmission format on the time division multiplex subscriber line 20, a configuration using a multiframe 24 according to CCITT recommendation X.50 as shown in FIG. 5 can be considered.
The X.50 multiframe 24 consists of 20 octets 25 (#1 to #20) with a multiframe repetition frequency of 400Hz, and each octet 25 includes synchronization bits Fi (i=1,...,20) 26, data bits
Dj (j=1,...,6) consists of 27 terminal state control bits S28. In order to transmit information from and to the terminal 17 using the multiplex subscriber line 20, it is necessary to allocate a number of octets commensurate with the communication speed of the terminal 17 within the X.50 multiframe. The set of octets allocated at this time is called a channel. By changing the allocation of octets to channels (hereinafter referred to as "channel allocation") in accordance with changes in the communication speed of the terminal, communication at multiple speeds becomes possible.

FIG. 6 shows an example of channel allocation according to speed. FIG. 6a shows an example in which one octet (#1 octet) is allocated within the multiframe 24, and represents a communication speed of 3.2 Kb/S channel. FIG. 6b shows an example where two octets (#1 and #11 octets) are allocated within the multiframe 24, and represents a communication speed channel of 6.4 Kb/S. Figure 6c shows 4 in multiframe 24.
This example shows a communication speed of 12.8 Kb/S channel when three octets (#1, #6, #11, #16) are allocated. FIG. 6d shows an example in which all 20 octets in multiframe 24 are allocated, and represents a communication speed channel of 64 Kb/S.

In FIG. 4, a sequence diagram shows a procedure in which the terminal 17 requests a change in communication speed, changes the channel assignment on the multiplex subscriber line 20 under control from the exchange 4, and switches the clock supplied to the terminal 17. This will be explained using FIG.

In FIG. 7, the terminal 17 is the line termination device 19.
A calling signal 29 is sent in synchronization with the clock supplied from the terminal. When the exchange 4 detects a call from the terminal 17 based on the call signal 29, it connects the channel on the multiple subscriber line 20 assigned to the terminal 17 to the dial receiving circuit, and sends a dialable signal 30 to the terminal 17. do. Terminal 17 has dialable signal 30
When received, it notifies the exchange 4 of a communication speed change request using a dial signal 31 predetermined for speed change. When the exchange 4 receives the dial signal 31 (speed change request signal), it determines the channel allocation on the multiple subscriber line 20 that is compatible with the communication speed requested by the terminal 17. The exchange 4 sends a confirmation signal 32 to the terminal 17 indicating that it has correctly received the speed change request signal. After this, switch 4
sends a disconnection instruction signal 33, and when the terminal 17 receives the disconnection confirmation signal 34, it temporarily disconnects the call. In order to perform the channel allocation determined after receiving the speed change request signal 31, the exchange 4 sends a signal 35 instructing the line termination device 19 to change the allocation, and then the exchange 4 performs the new allocation. Preparations for transmitting and receiving signals with the terminal 17 using the channel are completed. The line termination device 19 changes the channel assigned to the terminal based on the change instruction signal 35 from the exchange 4. When the allocation change is completed, the terminal 17 is supplied with a clock 36 of the new communication speed. Terminal 17 has clock 36
to complete preparations for communication at the new communication speed.

In the above example, a case has been described in which the terminal 17 has a communication function at multiple speeds, but according to the present invention, the terminal can only communicate at one fixed speed,
As shown in FIG. 8, when a plurality of terminals 37 and 38 are switched and used using a changeover switch 39, speed switching can be realized by switching the terminals. In this case, the signal sequence shown in FIG. 7 may be executed using the currently connected terminal.
In the sequence of FIG. 7, the disconnection confirmation signal 34
After sending out the new speed, the changeover switch 39 is switched, and the switched terminal receives the new speed clock 36, and can perform communication in synchronization with this.

FIG. 9 shows a block diagram of a configuration example of a line termination device 19 that implements the communication method according to the present invention. In the figure, 40 is a code conversion circuit that converts the encoding format of the signal on the multiple subscriber line 20 to the encoding format of the signal at the terminal, 41 is a clock extraction circuit, 42 is a multiframe synchronization circuit, and 43 is an octet. 44-1 is a separation circuit, 44-2 is a multiplexing circuit, 45 is an octet assembly/transmission circuit,
46 is a frame pattern generation circuit that generates a multiframe pattern to be inserted at the F bit position of an octet in order to achieve multiframe synchronization on a multiple subscriber line; 47 is a frame pattern generation circuit that converts a transmission signal from a terminal into the code of the signal on the multiple subscriber line; 48 is a control circuit, 49 is a channel allocation memory, and 49-1 is a clock supply circuit. Note that in FIG. 9 and further in FIGS. 10 to 18, the symbols such as , . . . attached to lines indicate that lines with the same number are connected to each other.

In normal communication, a signal transmitted from the multiplex subscriber line 20 is code-converted by a code conversion circuit 40, and a clock extraction circuit 41 extracts a clock necessary for signal transmission and reception.

The multiframe synchronization circuit 42 uses the clock from the clock extraction circuit 41 to identify the beginning of a multiframe (FIG. 5, 24), which is a transmission format on a multiple subscriber line, from the signal from the conversion circuit 40.
A clock necessary for the operation of each block in the line termination device 19 is created. The input signal from the conversion circuit 40 is separated by an octet receiving/separating circuit 43 into data bits (D bits) and signal bits (S bits) constituting an octet. Separation circuit 4
4-1 extracts the above D bit and S bit transmitted on the channel assigned to the terminal,
It is sent to the interface line, R line, and I line with each terminal. The D bit and S bit transferred from the terminal via the interface line, T line, and C line are transferred by the multiplexing circuit 44-2 onto the allocated channel to the terminal specified in the channel allocation memory 49, The octet assembly/transmission circuit 45 assembles the data into octets together with the frame bits output from the frame pattern generation circuit 46. After the octet signal is code-converted by the code conversion circuit 47, it is sent onto the multiplex subscriber line 20. Separation circuit 44-1 and multiplexing circuit 44-
A channel allocation memory 49 controls 2 and allocates channels to terminals. The channel allocation memory 49 is accessed in synchronization with the time slots corresponding to the octets of the multiframe 24 on the multiple subscriber line shown in FIG.
and the multiplexing circuit 44-2.

In order for a terminal to switch speeds, the correspondence between the time slot number (octet number) stored in the channel allocation memory 49 and the terminal speed (sixth
(see figure) must be rewritten based on instructions from the exchange and a new channel corresponding to the terminal speed must be assigned to the terminal.

The control circuit 48 receives an allocation control signal from the exchange, rewrites the contents of the channel allocation memory 49 in accordance with the signal, and provides the terminal with a channel corresponding to the terminal speed. In addition, the control circuit 48
controls the clock supply circuit 49-1, and
A clock corresponding to the terminal speed is selected from the clocks of various speeds created by 9-1, and is supplied to the terminal using the interface line and the S line.

Examples of the configuration of each circuit constituting the line termination device 19 shown in FIG. 9 are shown in FIGS. 10 to 18. Note that the lines marked in Figures 10 to 18 are
, . . . etc. indicate that lines with the same number are connected to each other throughout FIGS. 10 to 18.

FIG. 10 is a diagram showing an example of implementation of the code conversion circuit 40 and clock extraction circuit 41 shown in FIG.
The code conversion circuit 40 converts a bipolar signal (a signal in which the bit representing 1 takes alternately positive and negative values) transmitted on the multiple subscriber line 20 into a unipolar signal (a signal in which the bit representing 1 always takes the same polarity). It is configured by a bipolar/unipolar conversion circuit 401 that converts the signal into a signal). The clock extraction circuit 41 includes a change detection circuit 411, an oscillation circuit 412, a phase comparison circuit 413, and a frequency division circuit 414. The change detection circuit 411 receives a clock pulse from a clock pulse oscillation circuit 412 having a frequency sufficiently higher than the frequency of the input signal, and detects the rising edge of the input signal by sampling the input signal using this clock pulse. The phase comparator circuit 413 compares the phase of the clock pulse having the same frequency as the input signal, which is output from the frequency divider circuit 414, with the phase of the rising point of the input signal, and controls the multiplication of the output pulse. Frequency division circuit 414 receives the phase-controlled signal from phase comparison circuit 413 and divides the frequency.
Generates a clock pulse with the same frequency (64KHz) as the input signal.

FIG. 11 shows an example of implementation of the multi-frame synchronization circuit 42.

The selection circuit 421 extracts bits from the 64 KHz input data signal string at a cycle of 8 KHz using the 8 Kcl of the frequency dividing circuit 428, and inputs them to the shift register via the AND circuit AND422. shift register 42
3. Exclusive OR circuit XOR ₁ 426, decoder 4
24 has the same configuration as the frame pattern generation circuit 46 shown in FIG.
If the input bit string matches the X.50 frame pattern (A1101001000010101110 (A is "1" when normal and "0" when abnormal) generated from the frame pattern generation circuit, the exclusive OR circuit
XOR ₁ 426 output bits and shift register 4
There is a property that the input bits to 23 match. Note that when the decoder 424 detects that the output of the shift register 423 is a specific bit string ("01110"), it outputs "0", and the AND circuit AND422 outputs "0".
The output of the shift register 423 is set to "0", and "0" is input to the shift register 423.

Now, if the output bit of the exclusive OR circuit XOR ₁ 426 and the input bit to the shift register 423 do not match, the exclusive OR circuit XOR ₂ 427 generates a pulse "1". If the output of the exclusive OR circuit XOR ₂ 427 continues to be "1" a predetermined number of times (for example, 8 times) or more, the synchronization protection circuit 425 determines that the extracted bit string is not a frame pattern, and controls the frequency division circuit 428. and shift the phase of the 8KHz clock 8Kcl. The selection circuit 421 extracts bits in the next phase, inputs them to the shift register 423, and compares the output bits of the exclusive OR circuit XOR ₁ 426 with the input bits in the exclusive OR circuit XOR ₂ 427. When both bits match, exclusive OR circuit
If the output of XOR ₂ 427 continues to be “0” a predetermined number of times (for example, 5 times) or more, the synchronization protection circuit 425
determines that the extracted bit string is a frame pattern and that synchronization has been established. At this time, the frequency dividing circuit 42
8 generates an 8KHz clock pulse (8Kcl) synchronized with the frame bits in the input signal train. In addition to this, clock pulses 8Kcl ₁ , 8Kcl ₂ , and 8Kcl ₃ having mutually different phases are also generated.

FIG. 12 shows an example of implementation of the octet reception/separation circuit 43. 431 is a shift register SIPO that inputs signals in series and outputs them in parallel. The shift register SIPO 431 inputs an input data string with a period of 64 KHz and outputs data bits (d ₀ -d ₅ ) and control bit i in an octet in parallel. In addition, the frequency dividing circuit 423 converts the 64KHz clock to 48KHz.
Create a Hz clock 48Kcl.

FIG. 13 shows an example of implementation of the separation circuit 44-1.
In the same figure, 44-11 is the signal to the P ₀ to P ₅ terminals.
Input CP in parallel in synchronization with the clock to the Ps pin.
Shift register PISO that outputs serially to the So terminal according to the clock signal to the terminal, 44-12
is a flip-flop FF which inputs the signal to the D terminal in synchronization with the clock to the CP terminal, and continues to output the input to the output terminal Q until the next clock pulse arrives; 44-13 is an AND circuit. The shift register PISO44-11 clocks the output ( _d0 to _d5 ) of the octet reception/separation circuit 43.
By inputting at ts (described later), the data bit string to be received by the terminal is taken in, and this is serially outputted to the R line via the terminal So at clock tcl. The clock TCL is a clock corresponding to the terminal speed, and the clock TS is a 64Kb/S multiple subscriber line 20.
These are clocks that indicate the channel positions assigned to the terminals above, and both clock supply circuits 49-1
Powered by.

The flip-flop FF44-12 converts the output i from the octet reception/separation circuit 43 into a clock signal.
Matching timing of ts and tcl (AND circuit)
Obtained from AND44-13. ) and output to the I line via terminal Q.

FIG. 14 shows an example of implementing the multiplexing circuit 44-2. In the figure, 44-23 and 44-27 are selectors SEL ₁ and SEL ₂ which select and output input signals according to the value of input S, and 44-24 and 44-28 are selectors SEL
When a pulse is input to the terminal, “1” is input to the Q terminal,
When a pulse is input to the R terminal, “0” is output to the Q terminal.
Flips FF ₁ , FF ₂ , tcl, ts, which output
tbu is a clock supplied from the clock supply circuit 49-1, and b is a signal supplied from the control circuit 48.

The shift register SIPO44-21 clocks the serial signal sent from the terminal on the T line.
It is received in synchronization with , and 6 bits are stored. The shift register PISO 44-22 inputs in parallel the 6-bit information accumulated in the shift register SIPO 44-21 at the clock ts, and outputs the input information from the terminal So at the clock tbu. Selector SEL ₁ 44
-23 selects the output signal of the shift register PISO44-22 when the output Q of the flip-flop _FF144-24 is "0", that is, in synchronization with the clock tbu, and selects the output signal of the shift register PISO44-22 at other timings.
The signal b from the control circuit 48, which is accumulated significantly, is selected and outputted as a 48KHz signal t.

The flip-flop FF ₃ 44-26 extracts and outputs the signal sent from the terminal on the C line in synchronization with the clock TS. Selector SEL ₂ 44-27
is a flip-flop in synchronization with the clock tbu.
The output of FF ₁ 44-26 is selected, and at other timings, a "0" level signal is selected and output as a 48KHz signal C. AND-42-29,
AND42-29' is an AND circuit, and selector SEL ₁ 44-23, selector
Used when controlling SEL ₂ 44-27.

FIG. 15 shows an example of implementation of the octet assembly and transmission circuit 45, the frame pattern generation circuit 46, and the code conversion circuit 47.

In the octet assembly/transmission circuit 45, a shift register SIPO 451 receives the 48 KHz serial signal t which is the output of the multiplexing circuit 44-2, and stores 6 bits. The shift register PISO452 outputs the signal C, _P0 to _P5 outputted from the 6-bit storage information terminal of the shift register SIPO451, and the output of the frame pattern generation circuit 46 using an 8KHz clock 8KCl.
The 8 bits form an octet, which is output in series from the output end _S0 using a 64KHz clock 64KCl. The frame pattern generation circuit 46 includes a shift register 461 and an exclusive OR circuit XOR
463 and a decoder 464.
First, a specific bit string (“00111”) is preset in the 5-stage shift register 461, and the exclusive OR XOR of the output S ₂ of the 2nd stage and the output S ₅ of the 5th stage is fed back to the 1st stage. and continue the shift. The output bit string of this exclusive OR XOR becomes the X.50 multiframe pattern. The decoder outputs "0" only when the output of the shift register 461 detects a specific bit string ("01110") so that the output of the XOR becomes an X.50 multi-frame pattern with a period of 20, and the AND circuit AND462 and inputs “0” to the shift register.

The code conversion circuit 47 converts the unipolar signal into a bipolar signal using the unipolar/bipolar conversion circuit 471 and sends the signal to the subscriber line 20.

FIG. 16 shows an example of implementation of the control circuit 48.

The control circuit 48 inputs the control signals ( _d0 to _d5 ) from the octet reception separation circuit 43 to the reception register 481 at the timing of the channel to which the control signal from the exchange 4 is transferred. decoder 482
decodes the received signal and converts the signal (a ₀ to a ₄ ,
d), b, (S ₁ , S ₂ ) are output. Signal a ₀ ~ a ₄
is the write address to the channel allocation memory 49, signal b is a response signal to the exchange 4 or an appropriate level signal to be inserted into an empty channel of the subscriber line 20, and d is the write data to the memory in the channel allocation memory 49. , S ₁ , S ₂ are clock supply circuit 4
This is a clock selection instruction signal to 9-1.

FIG. 17 shows an example of implementation of the channel allocation memory 49.

In FIG. 17, 8Kcl ₁ , ₂ , and ₃ are 8KHz clocks having different phases, and are supplied from the frequency dividing circuit 428 of the multiframe synchronization circuit 42 .

The channel allocation memory 49 is mainly configured with a 20-word memory 491.
Each address corresponds to 20 time slots making up one X.50 multiframe.
The contents of each address in memory 491 specifies whether the time slot corresponding to the address is assigned to a terminal. Data d to memory 491
Writing is performed by writing data d stored in the register 492 to addresses a ₀ -a ₄ which are given from the control circuit 48 and latched in the address latch register 494. selector 49
3, the output Q of the flip-flop _FF2498 is "0", that is, the contents of the address latch register 494 are selected as the write address to the memory 491 in synchronization with the clock _8Kcl3 , and the flip-flop
When the output of FF ₂ 498 is “1”, that is, the clock
In synchronization with 8Kcl ₁ , the output of the 2decimal counter 495 is selected as the read address from the memory.

"1" is written in the address of the memory 491 corresponding to the channel assigned to the terminal, and "0" is written in the other addresses.

Therefore, the output read from the memory 491 at a cycle of 8KHz (its time length is regulated by the flip-flop FF ₁ 497) and the 48KHz clock 48Kcl are ANDed by the AND circuit AND496, so that the terminal A clock tbu corresponding to the channel assigned to is created.

FIG. 18 shows an example of implementation of the clock supply circuit 49-1.

Frequency divider circuit 49-11 is a 48KHz clock 48Kcl
Divide the frequency to 2.4, 4.8, which corresponds to the terminal speed.
Create 9.6, 48KHz clocks, and 0.4, 0.8, 1.6, and 8KHz clocks by dividing each frequency by 6. The selector 49-12 selects the clock tcl corresponding to the terminal speed and the clock ts obtained by dividing the clock by 6, according to the control signals (S ₁ , S ₂ ) from the control circuit 48. Here, the signals S ₁ , S ₂ are S ₁ ,
By taking the binary values 0, 1, 2, and 3 represented by the bits of _S2 , a clock of the corresponding frequency is selected.

The exchange 4 implementing the speed selective communication system according to the present invention can be a conventional time division exchange.

FIG. 19 shows an example of the configuration of the exchange. In FIG. 19, 50 is a demultiplexer, 51 is an incoming highway, 52 is an outgoing highway, 53 is a memory for temporarily storing information in octet units, and 54 is information transmitted on the incoming highway 51. 55 is a memory that specifies the address of the memory 53 for reading into a required time slot of the outgoing highway 52. 56 is a signal for processing signals from the highway. The processing section 57 is a central control device that controls the exchange.

The memory 54 realizes the correspondence between time slots on the highway and channels assigned to terminals. Therefore, changes in channel allocation due to terminal speed switching are performed by rewriting the memory 54 by the central controller 57. Signal processing section 56
is also used for signal transmission and reception between terminals and exchanges, and between line termination equipment and exchanges.

The above explanation has been made regarding the case where one terminal is connected to the line termination device 19 for communication. By allocating , simultaneous communication of multiple terminals can be realized.

A second embodiment of the invention is shown in FIG. In the figure, 58 is a terminal that can communicate at multiple speeds in synchronization with a clock provided by the network, and 59 is a terminal 5.
8 is a line termination device that supplies a clock at the communication speed required by the terminal, and 60 is a subscriber line that transmits information at a higher speed than the maximum communication speed of the terminal 58. In this embodiment, the transmission format on the subscriber line 60 is as follows.
Regardless of the multi-frame structure according to CCITT Recommendation X.50, as shown in FIG. ”) and is transmitted to the exchange 4 on the subscriber line 60 at high speed. Conversely, the synchronization flag F is deleted from the information from the exchange 4 at the line termination device 59, and the information is transmitted to the terminal 58 at the communication speed of the terminal 58. When there is a speed change request from the terminal 58, the exchange 4 sends a control signal to the line termination device 59 to switch the clock given to the terminal 58. The signal sequence for such a speed change can be realized by a sequence similar to that shown in FIG.

Figure 21 shows the line termination device 59 in Figure 20.
An example of the configuration is shown below. In the figure, 62 is a transmitting buffer that receives information from the terminal and assembles it into a frame, 63 is a receiving buffer that receives information from the exchange and transmits it to the terminal at the communication speed of the terminal, and 64 is a clock that receives the clock from the subscriber line 60. A clock generation circuit 65 extracts and generates a clock at the communication speed required by the terminal, and 65 is a signal transmitting/receiving device for transmitting and receiving control signals to and from the exchange. Note that 40 and 47 are code conversion circuits as in FIG. 9.

Information transmitted from the terminal 58 on the information line T line is received by the transmission buffer 62, a synchronization flag is added, and the code conversion circuit 47 converts the information into the code format on the subscriber line. line 6
Transmitted to 0. After the information sent from the subscriber line 60 to the terminal is code-converted by the code conversion circuit 40,
After the synchronization flag is deleted by the receiving buffer 63, the data is sent to the terminal via the information line R at the communication speed of the terminal. The signal transmitting/receiving device 65 receives a control signal from the exchange when switching the communication speed, controls the clock generation circuit 64 based on the signal, switches the clock supplied to the terminal through the interface line S line, and controls the clock of the terminal. Switch speed.

As explained above, according to the speed selection communication system of the present invention, it is possible to switch the communication speed of a terminal at any time according to a request from the terminal or the exchange, and communication with terminals of various speeds is possible with one subscription. According to the subscriber's request, it is possible to select the speed according to the communication content, such as high speed when transmission within a short time is required, and economic speed when it is not necessary. Furthermore, changing the communication speed makes it possible to utilize empty channels, which has the advantage of improving traffic communication.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a method for accommodating terminals in a digital switching network, Fig. 2 is a diagram showing an example of a method for accommodating terminals capable of switching communication speeds according to the prior art, and Fig. 3 is a diagram showing a conventional method different from Fig. 2. 4 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 5 is a diagram showing the transmission format on the multiple subscriber line in FIG. 4, and FIG. 6 is a diagram showing the implementation of FIG. 4. Figure 7 is a diagram showing the channel allocation on a multiple subscriber line for various speeds in an example, Figure 7 is a diagram showing the speed switching procedure, Figure 8 is a connection diagram when speed switching is realized by terminal switching, and Figure 9 is a diagram showing the 10 is a block diagram of an example of the implementation of the code conversion circuit 40 and clock extraction circuit 41 of FIG. 9, and FIG. 11 is a block diagram of an example of the implementation of the multiframe synchronization circuit 42 of FIG. FIG. 12 is a block diagram of a configuration example of the octet reception/separation circuit 43, and FIG. 13 is a block diagram of a configuration example of the octet reception/separation circuit 43.
FIG. 14 is a block diagram of the configuration example of the multiplexing circuit 44-2, and FIG. 16 is a block diagram of an example of the configuration of the control circuit 48, FIG. 17 is a block diagram of an example of the configuration of the channel allocation memory 49, and FIG. 18 is a block diagram of an example of the configuration of the clock supply circuit 49-1. 19 is a block diagram showing the configuration of a conventional time division switch that can be used in this embodiment, and FIG.
The figure shows the second embodiment of the present invention and the transmission format on the subscriber line in this embodiment, and FIG. It is a diagram. 1, 8, 9, 10, 37, 38, 58... terminal, 2, 11, 12, 13... conventional line termination device, 3, 14, 15, 16, 20, 60... subscriber line, 4 ...Time division switch, 5...Clock supply circuit, 6...Clock line, 7...Information line, 17...
...Terminal with communication function at multiple speeds, 18...
Changeover switch, 19, 59... Line termination device of the present invention, 21... Clock supply circuit, 22... Clock selection circuit, 23... Multiplexer, 24...
X.50 multiframe, 25...octets, 2
6...Synchronization bit, 27...Data bit, 2
8...Terminal status control bit, 29...Call signal,
30...Dial enable signal, 31...Dial signal, 32...Confirmation signal, 33...Disconnect instruction signal,
34...disconnection confirmation signal, 35...allocation change instruction signal, 36...new speed clock, 39...changeover switch, 40...code conversion circuit, 41...clock extraction circuit, 42...multiframe synchronization circuit ,
43...Octet reception/separation circuit, 44-1...
... Separation circuit, 44-2 ... Multiplexing circuit, 45 ...
Octet assembly/transmission circuit, 46... Frame pattern generation circuit, 47... Code conversion circuit, 48...
...Control circuit, 49...Channel assignment memory, 4
9-1...Clock supply circuit, 50...Multiplexer, 51...Input highway, 52...Output highway, 53, 54, 55...Memory, 56...Signal processing section, 57...Central control unit , 62...Transmission buffer, 63...Reception buffer, 64...Clock generation circuit, 65...Signal transmission/reception device.

Claims (1)

[Claims] 1. In a digital switching network in which terminals transmit and receive information in synchronization with a clock provided by the network, a line terminating device that connects the terminal and the subscriber line and supplies the terminal with a synchronization clock from the network is provided with the terminating device. A means for transmitting and receiving control signals to and from the exchange and a means for switching the speed of the synchronization clock supplied to the terminal are provided, and a control signal is transmitted between the terminal device and the exchange based on a communication speed change request from the terminal or the exchange. A speed selective communication system characterized in that a synchronization clock supplied from the line terminating device to the terminal is switched to the speed specified in the change request by a control signal sent from the line terminating device to the line terminating device.