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JPS6261967B2 - - Google Patents
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JPS6261967B2 - - Google Patents

Info

Publication number
JPS6261967B2
JPS6261967B2 JP57023526A JP2352682A JPS6261967B2 JP S6261967 B2 JPS6261967 B2 JP S6261967B2 JP 57023526 A JP57023526 A JP 57023526A JP 2352682 A JP2352682 A JP 2352682A JP S6261967 B2 JPS6261967 B2 JP S6261967B2
Authority
JP
Japan
Prior art keywords
potential
voltage
resistive film
timing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57023526A
Other languages
Japanese (ja)
Other versions
JPS58142493A (en
Inventor
Masayoshi Yurugi
Yasuo Shimizu
Yoshimi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP57023526A priority Critical patent/JPS58142493A/en
Publication of JPS58142493A publication Critical patent/JPS58142493A/en
Publication of JPS6261967B2 publication Critical patent/JPS6261967B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/045Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は抵抗膜を用い、x、y方向に電圧を前
記抵抗膜に時分割的に印加しておき任意の加圧点
の座標を前記抵抗膜の抵抗分割により出力される
電位として検出する座標入力方法の改良に関する
ものである。
Detailed Description of the Invention (Technical Field) The present invention uses a resistive film, applies voltage to the resistive film in the x and y directions in a time-sharing manner, and determines the coordinates of an arbitrary pressure point on the resistive film. This invention relates to an improvement in a coordinate input method that detects potentials output by resistor division.

(背景技術) 従来の座標入力装置のブロツク図を第1図に示
す。
(Background Art) A block diagram of a conventional coordinate input device is shown in FIG.

第1図において1は抵抗膜、2〜5はダイオー
ド群、6,7はスイツチでスイツチ6とスイツチ
7は連動する。又8は直流電源、13はタブレツ
ト部全体の総称、14はアナログ・デイジタルコ
ンバータ(以下ADCという。)、15はペンの如
く構成されている。又、第1図のタブレツト13
の構成を第2図に示す。
In FIG. 1, 1 is a resistive film, 2 to 5 are a group of diodes, 6 and 7 are switches, and switches 6 and 7 are interlocked. Further, 8 is a DC power supply, 13 is a general term for the entire tablet section, 14 is an analog/digital converter (hereinafter referred to as ADC), and 15 is configured like a pen. Also, the tablet 13 in FIG.
The configuration is shown in Figure 2.

第2図において9は絶縁基板、10は感圧ゴ
ム、11は導体膜、12は絶縁膜の如く構成され
ている。
In FIG. 2, 9 is an insulating substrate, 10 is a pressure sensitive rubber, 11 is a conductive film, and 12 is an insulating film.

以下第1図と第2図を参照しつつ従来の座標入
力装置について説明する。従来の座標入力装置は
図に示される如く絶縁基板上に形成された抵抗膜
の左右上下端に端子を設け、各端子には第1図に
示す如くダイオード群2〜5の各ダイオードを1
対1に接続し、ダイオード群2のアノードは共通
接続されスイツチ6のノーマルクローズ接点(以
下NC接点という)に接続され、ダイオード群3
のカソード側は共通接続されスイツチ7のNC接
点に接続される。スイツチ6、スイツチ7のコモ
ン接点(以下COM接点という)はそれぞれ、直
流電源の正電圧側とOV側に接続されているため
第1図は抵抗膜1のy方向に電圧がかかつている
状態を示す。次のタイミングではスイツチ6及び
スイツチ7がノーマルオープン接点(以下NO接
点という)側に同時にきりかえられるため、抵抗
膜1のx方向に電圧がかかり更に次のタイミング
ではスイツチ6及びスイツチ7が図の実線の状態
に戻るためy方向に電圧がかかるという如くx、
y方向に電圧は時分割的に印加されている。
A conventional coordinate input device will be described below with reference to FIGS. 1 and 2. As shown in the figure, terminals are provided at the left and right top and bottom ends of a resistive film formed on an insulating substrate, as shown in the figure, and each terminal is connected to one diode of diode groups 2 to 5 as shown in Figure 1.
The anodes of diode group 2 are connected in common and connected to the normally closed contact (hereinafter referred to as NC contact) of switch 6, and the anodes of diode group 2 are connected to
The cathode sides of are commonly connected and connected to the NC contact of switch 7. The common contacts (hereinafter referred to as COM contacts) of switches 6 and 7 are connected to the positive voltage side and OV side of the DC power supply, respectively, so Figure 1 shows the state in which voltage is applied to the resistive film 1 in the y direction. show. At the next timing, switch 6 and switch 7 are simultaneously switched to the normally open contact (hereinafter referred to as NO contact) side, so a voltage is applied in the x direction of resistive film 1, and at the next timing, switch 6 and switch 7 switch to the normally open contact (hereinafter referred to as NO contact) side. To return to the solid line state, a voltage is applied in the y direction, x,
The voltage is applied in the y direction in a time-division manner.

ここでペン15により絶縁膜12上の一点を加
圧すると絶縁膜12の下部の導体膜11と加圧さ
れた上下方向に対してのみ導通する感圧ゴム10
は抵抗膜1と前記加圧点で導通し抵抗膜1上の抵
抗分割された電位は抵抗膜1より感圧ゴム10、
導体膜11を通つてADC14に導出されデイジ
タル値に変換されるが、抵抗膜1に対してx、y
方向に電圧は時分割的に印加されているため加圧
点におけるx、y両方向の抵抗分割された結果の
電位が得られ結果として加圧点の座標値が得られ
る。ここで1秒間当り150点のサンプルレートで
座標値を入力せんとする場合について更に詳細に
説明する。なお詳細な説明を行なうに当り更に具
体的な説明を加えると、入力盤面がA4版(実効
210×297mm)で座標値の分解能を0.1mmとすると
長手方向は2971点に分割しなければならず、その
ためにはADC14は12ビツトのものが必要であ
る。いまフルレンジ入力がDC10Vのアナログ・
デイジタルコンバータを用いるとするとデイジタ
ル単位量に相当するアナログ電圧は10/4095≒2.
44m Vとなる。したがつて抵抗膜の長手方向には2.44
×2970=7246.8mVの電圧がかかることとなる。
Here, when a point on the insulating film 12 is pressed with the pen 15, the pressure-sensitive rubber 10 is electrically connected to the conductive film 11 under the insulating film 12 only in the vertical direction where the pressure is applied.
is conductive between the resistive film 1 and the pressure point, and the potential divided by the resistance on the resistive film 1 is connected to the pressure sensitive rubber 10,
It is led out to the ADC 14 through the conductor film 11 and converted into a digital value, but the x, y values are
Since the voltage is applied in a time-divisional manner in the directions, the potential resulting from resistance division in both the x and y directions at the pressurizing point is obtained, and as a result, the coordinate values of the pressurizing point are obtained. Here, a case in which coordinate values are input at a sampling rate of 150 points per second will be explained in more detail. To give a more specific explanation, the input panel is A4 size (effective
210 x 297 mm) and the resolution of coordinate values is 0.1 mm, it must be divided into 2971 points in the longitudinal direction, and for this purpose, the ADC 14 needs to be 12 bits. Currently, the full range input is DC10V analog.
If a digital converter is used, the analog voltage corresponding to a digital unit quantity is 10/4095≒2.
44mV. Therefore, the longitudinal direction of the resistive film is 2.44
A voltage of x2970=7246.8mV will be applied.

さて、いまペン15で絶縁膜12の上からある
点Aを加圧中スイツチ6と7が第1図での点線の
状態(COM接点とNO接点が閉じた状態)となつ
たとするとダイオード群4からダイオード群5に
対して直流電源8の電圧がかけられる。この電圧
は先にも説明した通り7.2468Vに、所要電流にお
けるダイオード群4,5のダイオードの順方向電
圧降下の2倍を加算した電圧である。なお短手方
向に対しても同じ電圧を印加し、デイジタル量に
変換後比例的に演算で座標値を求めるものとして
説明を進める。いまx方向の座標成分として、加
圧点Aのx成分の電位(これをAx〔V〕とす
る)がADC14の入力に出現する。いまサンプ
ルプレートは150サンプル/秒のため周期は6.6m
secでありこの間にx、y両方向の座標値が必要
なため3.3msec以内にADC14によりデイジタ
ル量に変換した上で、スイツチ6,7をきりかえ
y方向の成分の電位(これをAy〔V〕とする)
を検出し、ADC14に導びきデイジタル量に変
換する。第1図は模式的に正方形に近く書かれて
いるが長手方向がx、短手方向がyの方向とする
と加圧点Aが抵抗膜1上の右下にある場合Ax
〔V〕は大きな電圧値でありAy〔V〕は小さな電
圧値となる。又抵抗膜は抵抗膜に流す電流を減づ
るため、大きな抵抗値で構成されるためADC1
4の入力部は高インピーダンス状態となつてい
る。その状態に対し、大電圧Axが出現しその3.3
msec後に小電圧Ayとなるため、大電圧Axによ
る電荷が抵抗膜1からADC14に至る迄の間の
浮遊容量内に蓄積され小電圧AyをADC14で変
換するタイミング迄に完全に放電することは困難
であつた。又第2図に示す如くタブレツト13は
各種の基板、ゴム、膜等から構成されるためノイ
ズ電圧もよく発生しこれらノイズの影響を減づる
にはADC14の入力部にサンプルホールド回路
を付加するか、又はノイズ電圧をなまらせる必要
があつた。これらノイズ電圧をなまらせるために
は当然のことながら浮遊容量と導体のもつインピ
ーダンスよりなる積分効果では全く効果がなく、
といつて前記ノイズ電圧に対して積分効果を生む
程の定数のコンデンサを例えばADC14の前に
挿入したのでは浮遊容量でさえも困つている状態
のためより一層蓄積された電荷を放電できないこ
ととなり結果的にサンプルレートをかなり落さざ
るを得ないという本質的な欠点があつた。
Now, if the pen 15 is pressurizing a certain point A from above the insulating film 12 and the switches 6 and 7 are in the state shown by the dotted lines in FIG. 1 (the COM contact and the NO contact are closed), the diode group 4 A voltage from a DC power source 8 is applied to the diode group 5 from the source. As explained above, this voltage is 7.2468V plus twice the forward voltage drop of the diodes of diode groups 4 and 5 at the required current. The explanation will proceed assuming that the same voltage is applied in the lateral direction, and the coordinate values are calculated proportionally after conversion into digital quantities. Now, as a coordinate component in the x direction, the x-component potential of the pressurizing point A (this is referred to as A x [V]) appears at the input of the ADC 14 . Currently, the sample plate is 150 samples/second, so the period is 6.6 m.
sec, and during this time coordinate values in both the x and y directions are required, so they are converted into digital quantities by the ADC 14 within 3.3 msec, switches 6 and 7 are turned on, and the potential of the component in the y direction (this is A y [V )
is detected and led to the ADC 14 where it is converted into a digital quantity. Although FIG. 1 is schematically drawn close to a square, assuming that the longitudinal direction is x and the transverse direction is y, if the pressure point A is at the lower right on the resistive film 1, then A x
[V] is a large voltage value, and A y [V] is a small voltage value. Also, the resistive film is composed of a large resistance value in order to reduce the current flowing through the resistive film, so ADC1
The input section No. 4 is in a high impedance state. For that state, a large voltage A x appears and 3.3
Since the voltage A y becomes small after msec, the charge due to the large voltage A x is accumulated in the stray capacitance from the resistive film 1 to the ADC 14 and is completely discharged by the time the small voltage A y is converted by the ADC 14. That was difficult. Furthermore, as shown in Fig. 2, since the tablet 13 is composed of various substrates, rubber, films, etc., noise voltages are often generated.In order to reduce the influence of these noises, it is recommended to add a sample and hold circuit to the input section of the ADC 14. , or it was necessary to smooth out the noise voltage. Naturally, the integral effect of stray capacitance and conductor impedance is not effective at all in blunting these noise voltages.
However, if a capacitor with a constant value that produces an integral effect on the noise voltage is inserted in front of the ADC 14, for example, even the stray capacitance will be in trouble, making it even more difficult to discharge the accumulated charge. As a result, the essential drawback was that the sample rate had to be reduced considerably.

又、第1図ではスイツチ6とスイツチ7により
抵抗膜1に印加する電圧をx方向とy方向に瞬間
的にきりかえているが瞬間的にトランジスタ等を
用いてきりかえたのでは、スイツチ6とスイツチ
7の動作タイミングのずれ等によりx方向、y方
向だけでなく思わぬ方向に電流が流れ抵抗膜1上
の電位分布を混乱させ全体的にノイジイになるこ
とと合せて、ひいてはADC14に誤つた電位を
出現せしめる恐れがある等の欠点もあり結果的に
所望のサンプルレートを保持することが困難であ
つた。
In addition, in FIG. 1, the voltage applied to the resistive film 1 is instantaneously switched between the x direction and the y direction by switches 6 and 7, but if the voltage is switched instantaneously using a transistor or the like, the switch 6 and Due to a difference in the operation timing of switch 7, current flows not only in the x and y directions but also in unexpected directions, which confuses the potential distribution on the resistive film 1 and makes it noisy overall. There are also drawbacks such as the risk of causing potential to appear, and as a result, it is difficult to maintain a desired sample rate.

以上述べた欠点は、従来より抵抗膜を用いた座
標入力装置が注目されつつも満足のいく実用化を
困難としてきた諸原因の中でも大きなものであつ
た。
The above-mentioned drawbacks have been one of the major reasons why coordinate input devices using resistive films have been attracting attention, but have been difficult to put into practical use satisfactorily.

(発明の課題) 本発明の目的はこれらの欠点を除去するためタ
ブレツト13の出力部に積分回路を挿入してノイ
ズを除去すると共に、積分回路に蓄積された電荷
を放電する放電回路を設けタブレツト13のx方
向とy方向の座標値を検出するタイミングの間に
新たなる放電タイミングを設け、この放電タイミ
ングに前記放電回路を機能せしめるようにしたも
ので以下詳細に説明する。
(Problems to be solved by the invention) In order to eliminate these drawbacks, the purpose of the present invention is to insert an integrating circuit into the output section of the tablet 13 to remove noise, and to provide a discharge circuit for discharging the charge accumulated in the integrating circuit. A new discharge timing is provided between the timings of detecting coordinate values in the x and y directions of No. 13, and the discharge circuit is made to function at this discharge timing, which will be described in detail below.

(発明の構成および作用) 第3図は本発明の一実施例を示すブロツク図で
あり、16,17は3接点を有するスイツチでス
イツチ16,17は同期して動作する。18は積
分回路、19は放電回路であり第3図に示す如く
スイツチ16,17はタブレツト13内の抵抗膜
のy方向に電圧を印加した後真中の接点を通り、
この時点でタブレツト13及び積分回路18の電
荷を放電回路19により放電し、その後抵抗膜の
x方向に電圧を印加するように作動する。
(Structure and operation of the invention) FIG. 3 is a block diagram showing an embodiment of the invention, in which numerals 16 and 17 are switches having three contacts, and the switches 16 and 17 operate synchronously. 18 is an integration circuit, 19 is a discharge circuit, and as shown in FIG. 3, switches 16 and 17 apply a voltage in the y direction of the resistive film inside the tablet 13, and then pass through the contact point in the middle.
At this point, the charges in the tablet 13 and the integrating circuit 18 are discharged by the discharge circuit 19, and then a voltage is applied to the resistive film in the x direction.

以下作動状況に関して更に詳しく説明する。 The operating conditions will be explained in more detail below.

スイツチ16,17は第1図におけるスイツチ
6,7と同様、回路をタイミング的にきりかえる
ことを模式的に表わしたものであり、実際にはト
ランジスタ等の素子により実現される。いまサン
プルレートを150サンプル/秒に選ぶ場合、周期
は6.6msecでありこの間に電位のサンプル及びア
ナログ・デイジタル変換と放電を各2回づつ行な
う必要があるため電位のサンプル及びアナログ・
デイジタル変換に2.5msecづつ割り当て、放電に
0.8msecづつを割りあてる位が妥当である。積分
回路18の時定数は前記変換のための時間、ここ
では2.5msecから変換時間とデータアクイジジヨ
ンタイムを除き、更に若干の余裕を見た2msec
位にしておく。このような定数を選ぶことにより
ADC14が変換を開始する時はタブレツト13
からの出力電位は落ちつき、小さな外乱ノイズが
入つたとしてもそれは積分回路18によつて押え
られADC14の変換には悪影響を及ぼさない。
このようにして例えばタブレツト13のy方向の
変換を行なつた後、次の0.8msecが放電のための
時間となる。スイツチ16の真中の接点より放電
回路19へ信号を送り放電を作動させる。放電回
路19の時定数は放電時間が0.8msecであるため
余裕をみて0.5msec位に設定することが望まし
い。ただし積分回路18へ蓄えられた電荷を放電
回路19により短時間に放電するため、電流的な
配慮が必要なことはいうまでもない。
Switches 16 and 17, like switches 6 and 7 in FIG. 1, are schematic representations of switching circuits in terms of timing, and are actually realized by elements such as transistors. If we choose the sample rate to be 150 samples/second, the cycle is 6.6 msec, and during this period, it is necessary to sample the potential, perform analog/digital conversion, and discharge twice.
Allocate 2.5 msec each for digital conversion and discharge
It is appropriate to allocate 0.8 msec each. The time constant of the integrator circuit 18 is the time for the conversion, here 2.5 msec, excluding the conversion time and data acquisition time, and 2 msec with some margin added.
I'll leave it at that. By choosing such a constant
When ADC 14 starts conversion, tablet 13
The output potential from the converter is stabilized, and even if a small disturbance noise enters, it is suppressed by the integrating circuit 18 and does not adversely affect the conversion of the ADC 14.
After converting the tablet 13 in the y direction in this way, for example, the next 0.8 msec is the time for discharging. A signal is sent from the middle contact of the switch 16 to the discharge circuit 19 to activate the discharge. Since the discharge time is 0.8 msec, it is desirable to set the time constant of the discharge circuit 19 to about 0.5 msec with some margin. However, since the charges stored in the integrating circuit 18 are discharged in a short time by the discharging circuit 19, it goes without saying that consideration must be given to current considerations.

(発明の効果) 以上説明した様に前記実施例では許されたサン
プル周期を4つに分割し、x、y各成分の電圧の
サンプル及び変換と放電にタイミングを分け、放
電タイミングには回路に蓄えられた電荷の放電の
みを行なう放電回路19を設け同時に積分回路1
8を設けたため、従来の技術のすべての欠点が除
去されるものである。
(Effects of the Invention) As explained above, in the embodiment, the allowed sampling period is divided into four, the timing is divided into sampling and conversion of voltage of each x and y component, and discharge, and the circuit is set at the discharge timing. A discharging circuit 19 for discharging only the stored charge is provided, and at the same time, an integrating circuit 1 is provided.
8, all the drawbacks of the prior art are eliminated.

すなわちサンプル周期をx方向の電位のサンプ
ル及び変換、放電、y方向の電位のサンプル及び
変換、放電と4つのタイミングに分割したため、
抵抗膜1に流れる電流が整然とし結果的に誤つた
電位をサンプルする危険性が極めて少くなるとい
う利点がある。
In other words, since the sampling period is divided into four timings: sampling and converting the potential in the x direction, discharging, sampling and converting the potential in the y direction, and discharging,
There is an advantage that the current flowing through the resistive film 1 is orderly, and as a result, the risk of sampling an incorrect potential is extremely reduced.

又放電回路19を設けたことにより、積分回路
18を設けることが可能となるばかりでなく積分
回路18の電荷も含めてタブレツト13の浮遊容
量等に蓄えられた電荷等を周期的に放電できるた
め回路が安定化するという利点がある。
Furthermore, by providing the discharge circuit 19, it is not only possible to provide the integrating circuit 18, but also the charges accumulated in the stray capacitance of the tablet 13, including the charges of the integrating circuit 18, can be periodically discharged. This has the advantage of stabilizing the circuit.

次に積分回路18を設けることによりノイズを
除去できるだけでなく、タブレツト13よりの出
力電圧をADC14により安定にデイジタル値に
変換するためにはタブレツト13とADC14の
間にサンプルホールド回路が必要であつたが積分
回路18を設けることにより積分回路18がサン
プルホールド回路の機能をも合せ有するため、よ
り安定なデイジタル値への変換が可能となるとい
う利点がある。従つて安定な状態でアナログ電圧
をデイジタル値に変換でき、しかも、サンプル及
び変換の周期も所望の周期が確保できるという利
点があり、結果として抵抗膜を用いた座標入力装
置の実用化に多大なる寄与をするものである。
Next, by providing the integrating circuit 18, not only can noise be removed, but also a sample and hold circuit is required between the tablet 13 and the ADC 14 in order to stably convert the output voltage from the tablet 13 into a digital value by the ADC 14. By providing the integrating circuit 18, the integrating circuit 18 also has the function of a sample and hold circuit, which has the advantage that conversion to a more stable digital value becomes possible. Therefore, it has the advantage of being able to convert an analog voltage into a digital value in a stable state, and also ensuring a desired sampling and conversion cycle, which will greatly contribute to the practical application of coordinate input devices using resistive films. It is something that makes a contribution.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の座標入力装置のブロツク図、第
2図はタブレツト部の構成図、第3図は本発明の
一実施例を示すブロツク図である。 1……抵抗膜、2〜5……ダイオード群、6,
7……スイツチ、8……直流電源、9……絶縁基
板、10……感圧ゴム、11……導体膜、12…
…絶縁膜、13……タブレツト部、14……アナ
ログ・デイジタルコンバータ、15……ペン、1
6,17……スイツチ、18……積分回路、19
……放電回路。
FIG. 1 is a block diagram of a conventional coordinate input device, FIG. 2 is a block diagram of a tablet section, and FIG. 3 is a block diagram showing an embodiment of the present invention. 1...Resistive film, 2-5...Diode group, 6,
7...Switch, 8...DC power supply, 9...Insulating substrate, 10...Pressure sensitive rubber, 11...Conductor film, 12...
...Insulating film, 13...Tablet part, 14...Analog-digital converter, 15...Pen, 1
6, 17...Switch, 18...Integrator circuit, 19
...discharge circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 抵抗膜を有するタブレツトと、該抵抗膜のた
て方向及び横方向に時分割的に電圧を印加する手
段と、抵抗膜上の任意の加圧点の座標を抵抗膜上
における抵抗分割により電位として出力する手段
と、該電位をデイジタル量に変換する手段とを有
する座標入力装置において、抵抗膜の出力に接続
される積分回路及び該積分回路の電荷を放電する
放電回路がもうけられ、加圧点に対応するたて方
向及び横方向のうち一方の前記電位の検出及び該
電位のデイジタル量への変換を行う第1のタイミ
ングと、該タイミングで積分回路に蓄積された電
荷を前記放電回路により放電する第2のタイミン
グと、前記加圧点に対応するたて方向及び横方向
のうち他方の前記電位の検出及び該電位のデイジ
タル量への変換を行う第3のタイミングと、該タ
イミングで積分回路に蓄積された電荷を前記放電
回路により放電する第4のタイミングとが時分割
的に切換えられることを特徴とする座標入力方
法。
1 A tablet having a resistive film, a means for time-divisionally applying voltage in the vertical and horizontal directions of the resistive film, and a voltage potential of the coordinates of an arbitrary pressure point on the resistive film by resistance division on the resistive film. In a coordinate input device having a means for outputting a potential as a first timing for detecting the potential in one of the vertical and horizontal directions corresponding to a point and converting the potential into a digital amount; a second timing for discharging, a third timing for detecting the potential in the other of the vertical and horizontal directions corresponding to the pressurizing point and converting the potential into a digital quantity, and integrating at the timing. A coordinate input method characterized in that a fourth timing for discharging charges accumulated in a circuit by the discharge circuit is switched in a time division manner.
JP57023526A 1982-02-18 1982-02-18 Coordinate inputting method Granted JPS58142493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57023526A JPS58142493A (en) 1982-02-18 1982-02-18 Coordinate inputting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57023526A JPS58142493A (en) 1982-02-18 1982-02-18 Coordinate inputting method

Publications (2)

Publication Number Publication Date
JPS58142493A JPS58142493A (en) 1983-08-24
JPS6261967B2 true JPS6261967B2 (en) 1987-12-24

Family

ID=12112884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57023526A Granted JPS58142493A (en) 1982-02-18 1982-02-18 Coordinate inputting method

Country Status (1)

Country Link
JP (1) JPS58142493A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447974U (en) * 1987-09-21 1989-03-24

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2542953Y2 (en) * 1991-05-07 1997-07-30 グンゼ株式会社 Touch panel device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6447974U (en) * 1987-09-21 1989-03-24

Also Published As

Publication number Publication date
JPS58142493A (en) 1983-08-24

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