JPS626431B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a motor speed control device, which uses a stable frequency such as the output of a crystal oscillator as a speed reference to improve rotational speed stability, and further incorporates speed information into the speed control loop. By inserting an integrating circuit to further improve the stability of the rotational speed relative to the load, we aim to achieve controllability equivalent to the speed-phase control method that uses a phase control loop that includes a phase comparator. It is something.

Conventional motors used in audio equipment such as record players and tape recorders often use speed control motors that use voltage as a reference for their rotational speed, but this method is difficult to control due to changes in ambient temperature and electronic components. It is difficult to create a reference voltage that is sufficiently stable against changes over time, and there are also problems in that speed deviations occur with respect to the load.

To solve this problem, high-end machines add a phase control loop to the speed control loop, and in particular, use a highly stable reference, such as the output of a crystal oscillator, as a comparison reference for the phase control. However, this system consists of two control loops, a speed control loop and a phase control loop, and the operations of these two control loops influence each other, making adjustment complicated.
Further, the configuration becomes complicated, and there are also problems such as the operating points of both shift due to changes in ambient temperature or aging of electronic components, and the phase synchronization range decreases.

The present invention provides a motor speed control device that can completely solve the above-mentioned conventional problems.
One embodiment will be described below based on the drawings.

FIG. 1 is a block diagram illustrating the concept of the present invention. 1 is a motor; 2 is a tachometer generator that generates a signal with a frequency proportional to the number of rotations of the motor 1;
3 is a waveform shaping circuit that shapes the output waveform of the tachometer generator 2; 4 is a reference frequency signal generation circuit including an oscillation circuit having a stable oscillation output such as a crystal oscillator; and 5 is a speed error detection circuit. One of these days,
Reference numeral 6 uses the falling edge of the output signal of the waveform shaping circuit 3 (hereinafter referred to as a rotation pulse) as a trigger signal, and outputs the output signal of the reference frequency signal generation circuit 4 (hereinafter referred to as a clock pulse) into N pieces (N
7 is a first constant pulse width generating circuit mainly composed of an N-adic counter that counts up to an integer) and outputs, for example, a level "1" during counting, and outputs, for example, a level "0" after counting. Triggered by the falling edge of the output signal of the first constant pulse width generating circuit 6, that is, the end of counting N pulses,
An M clock pulse that counts up to M clock pulses (M is an integer) and outputs, for example, a "1" level during counting and, for example, a "0" level after counting.
This is a second constant pulse width generation circuit mainly composed of an advance counter. A first circuit 8 synthesizes the respective output pulses of the first constant pulse width generation circuit 6 and the second constant pulse width generation circuit 7 to generate an amount (for example, pulse width) corresponding to the speed error information of the motor 1. This is a synthesis circuit. The speed error detection circuit 5 is constituted by the first constant pulse width generation circuit 6, the second constant pulse width generation circuit 7, and the first synthesis circuit 8. Next, 9 is a cumulative speed error detection circuit, of which 10 is a gate circuit that uses the output pulse of the first synthesis circuit 8 as a gate signal and passes or cuts off the clock pulse, and 11 is a gate circuit that passes through the gate circuit 10. Cumulatively counts up or down the clock pulses and
It is an L-ary system that stops counting up (in other words, holds the value) after counting up to the number (L is an integer), and stops counting down if it reaches a clear state after counting down. The up-down counter 12 is a second synthesis circuit that synthesizes amounts corresponding to cumulative speed error information of the motor 1 according to the contents of the up-down counter 11. Gate circuit 1 above
0, an up-down counter 11, and a second synthesis circuit 12 constitute the cumulative speed error detection circuit 9. 13 is a filter circuit for smoothing the outputs of the first synthesis circuit 8 and the second synthesis circuit 12 and converting them into DC voltage; 14 is the filter circuit 13;
This is a motor drive circuit that drives the motor 1 by the output of the motor.

The motor 1, tachometer generator 2, described above,
The waveform shaping circuit 3, speed error detection circuit 5, filter circuit 13, and motor drive circuit 14 constitute a speed control loop. Also, the cumulative speed error detection circuit 9
Since there is a function that cumulatively integrates the speed error information, this equivalently gives phase error information, so in addition to the above, a phase control loop is configured by the cumulative speed error detection circuit 9. This means that

Next, the concept of the present invention will be specifically explained using a time chart. Fig. 2 is an operation time chart of the speed error detection circuit 5 of the present invention, Fig. 2a shows when the motor does not reach the reference speed, Fig. 2b shows when the motor reaches the reference speed, and Fig. 2c shows the reference speed. The cases in which the speed is exceeded are shown below. In the figure, A indicates a rotation pulse (the frequency is f _M ). B shows the output of the first constant pulse width generation circuit 6 which is triggered by the falling edge of the rotation pulse and counts N clock pulses to generate a constant width pulse. Therefore, if the period of the clock pulse is τ, the constant pulse width is N.
becomes τ. C shows the output of the second constant pulse width generating circuit 7 which, following B, counts M clock pulses and generates a constant width pulse. This pulse width is Mτ. Since τ is always constant, the sum of Nτ and Mτ is also constant, and here we define a reference frequency f ₀ such that 1/f ₀ = Nτ + Mτ (constant), and compare this with the rotation pulse of the frequency f _M The speed should be the standard. Therefore, speed error information can be given as the difference between f ₀ and f _M . In an actual circuit, it is easy to extract speed error information from the period difference (i.e., the difference between 1/f ₀ and 1/f _M ), and both d and ho in the figure represent this period difference. be. On the circuit, it corresponds to the output of the first synthesis circuit 8 that synthesizes the respective output pulses of the first and second constant pulse width generation circuits 6 and 7. Particularly, D appears when the motor rotation is slower than the reference speed, and E appears when the motor rotation is faster than the reference speed. Note that neither of these appears when the speed is equal to the reference speed. The former will be named an acceleration pulse and the latter a deceleration pulse.

In this way, the output (acceleration pulse and deceleration pulse) of the speed error synthesis circuit 8 corresponds to the speed error information of the motor 1, and is smoothed by the filter circuit 13 and converted into a DC voltage, which is then applied to the motor drive circuit 14. By driving the motor 1 via the motor, speed control of the motor can be realized.

Next, the cumulative speed error detection circuit 9 of the present invention will be specifically explained. First, the gate circuit 10 is a gate that is controlled by the output (acceleration pulse and deceleration pulse) of the first synthesis circuit 8, and allows the clock pulse to pass only during the above pulses. . The up-down counter 11 counts the passing clock pulses cumulatively (without resetting every rotation pulse cycle); for example, it counts up during acceleration pulses and counts down during deceleration pulses. . However, as mentioned above, this L-base up-down counter 11 will stop counting up if it counts up up to L clock pulses, and on the other hand, if it counts down and the contents are cleared, it will continue to count down. Assume that the operation stops. With this configuration, the contents of the up-down counter 11 can cumulatively hold speed error information, and mathematically provide integral speed information. That is, this provides phase error information of the motor 1. The second synthesis circuit 12 synthesizes the up-down counters according to the contents of the up-down counter to provide cumulative speed error information of the motor 1, that is, an amount corresponding to phase error information. A simple example would be a D/A converter.

FIG. 3 shows a model of the characteristics of the up-down counter 11. The vertical axis shows the contents of the counter, and the horizontal axis shows the rotation status of the motor 1. For example, when the motor 1 is started with slow rotation, the counter is counted up to "L". Motor 1
When the rotation increases and exceeds the reference speed, a countdown is performed, so the contents are gradually decreased, and finally they are all cleared to "0".
It changes linearly from "L" to "0". In FIG. 3, the lines are connected by straight lines, but in reality they change in steps (the number of steps is "L"). As can be seen from this figure, the cumulative speed error detection circuit 9 including the up-down counter 11 not only has an effect completely equivalent to that of a phase comparator that has been widely used in the past, but also has the characteristics of a so-called saturated Because it is a type, its phase synchronization pull-in characteristics are extremely excellent.

Next, specific examples of the present invention will be given. FIG. 4 shows an embodiment of the speed error detection circuit 5 of the present invention. 21 in the figure is the clock pulse input terminal
It is an N-ary counter with CK, output terminal, and clear terminal CL. 22 is a differentiating circuit that differentiates the falling edge of the rotational pulse and generates a narrow negative differential pulse; 23
is an RS flip-flop which is set by the above negative differential pulse and reset by the above terminal output, and has a positive logic output terminal Q. now,
Assuming that the falling edge of the rotational pulse is given, a narrow negative differential pulse is produced by the differentiating circuit 22, thereby setting the RS flip-flop 23. That is, the Q terminal becomes "1" level. Since the Q terminal is connected to the CL terminal of the N-ary counter 21, the clearing (resetting) of the N-ary counter 21 is canceled and counting starts. When N clock pulses are counted, the instantaneous terminal changes from the "1" level to the "0" level, and as a result, the RS flip-flop 23 is reset.
The Q terminal changes from "1" level to "0" level.
This is maintained until a new falling edge of the rotation pulse is applied. Note that when the Q terminal reaches the "0" level, the N-ary counter 21 is cleared (reset) during that time. The above result RS flip-flop 2
The output of the Q terminal of No. 3 will provide the first constant pulse width. Therefore, the N-ary counter 21, the differentiating circuit 22, and the RS flip-flop 23 constitute the first constant pulse width generating circuit 6.

Next, the second constant pulse width generation circuit 7 composed of the M-adic counter 24, the differentiating circuit 25, and the RS flip-flop 26 changes the count number N of the first constant pulse width generation circuit 6 to M, and also performs the differentiation. The operation itself is exactly the same except that the circuit is changed from operating on the falling edge of the rotation pulse to operating on the falling edge of the output pulse of the first constant pulse width generating circuit 6, so a description thereof will be omitted. 27 and 28 are the first
and a logic circuit constituting a first synthesis circuit 8 which synthesizes the output pulses of the second constant pulse width generation circuits 6 and 7 and provides an amount corresponding to the speed error information of the motor 1, and the former is a NOR circuit. The latter is an AND circuit whose output gives an acceleration pulse, and the latter is an AND circuit whose output gives a deceleration pulse.

FIG. 5 shows an embodiment of the cumulative speed error detection circuit 9 of the present invention. In the figure, 10 is a gate circuit that controls passing and blocking of clock pulses using the output (acceleration pulse and deceleration pulse) of the first synthesis circuit 8;
a is an AND gate controlled by an acceleration pulse, and 10b is an AND gate controlled by a deceleration pulse. Reference numeral 11 denotes an L-adic up-down counter having a U terminal for inputting a count-up pulse, a D terminal for inputting a count-down pulse, and a plurality of Y terminals for constantly outputting count contents. Note that the U terminal is
It is connected to the AND gate 10a output, and its D terminal is connected to the AND gate 10b output. Also 1
2 receives the output of the Y terminal and converts it to D/A,
This is a second synthesis circuit composed of a D/A converter for providing an amount corresponding to cumulative speed error information of the motor 1. 15 is an overflow detector for detecting when the up-down counter 11 has counted up to L, and closing the gate 10a to cut off the count-up pulse and stop the count-up operation; 16 is an overflow detector for the up-down counter 11; This is an underflow detector that detects when the countdown countdown to "0" becomes a clear state, closes the gate 10b, cuts off the countdown pulse, and stops the countdown operation.

FIG. 6 shows another embodiment of the cumulative speed error detection circuit 9 of the present invention. The embodiment shown in FIG. 5 includes a D/A converter in part, so as the number of bits in the up-down counter increases, it becomes increasingly difficult and complicated to obtain conversion accuracy (such as linearity). And expensive items are needed. The embodiment shown in FIG. 6 eliminates this drawback by temporarily transferring the contents of the up-down counter 11 to another transfer counter at the end (falling edge) of the acceleration pulse or deceleration pulse.
The purpose is to provide cumulative speed error information based on the time it takes for this transfer counter to count down and its contents to be in the "0" state (clear state). In the figure, parts that are the same as those in the embodiment shown in FIG. 5 are numbered in common to avoid duplication of explanation.
31 is a differentiation circuit that differentiates the falling edge of the acceleration pulse or deceleration pulse and generates a negative differential pulse; 32 is a LOAD terminal that inputs the differential pulse;
Read the contents of 1 in parallel from the DATA terminal,
After that, it is a down counter that counts down by a clock pulse input from the D terminal. The down counter 32 has an output terminal, which outputs a "1" level during countdown, and immediately outputs a "0" level when its contents become a "0" state (clear state). 33 is the differentiation circuit 3
The RS flip-flop is set by a negative differential pulse of a 1 output and reset by a 0 level output from the down counter 32, and has a Q terminal with a positive logic output. Further, the Q terminal is connected to the ENABLE terminal of the down counter 32. Note that the down counter 32 performs a countdown operation only when the input to the ENABLE terminal becomes "1". If the falling edge of the acceleration pulse or deceleration pulse is now given, the differentiator circuit 31
generates a negative differential pulse, which is input to the LOAD terminal of the down counter 32, so that the contents of the up/down counter 11 are transferred to the down counter 32 in parallel at this instant. On the other hand, since the above-mentioned negative differential pulse simultaneously sets the RS flip-flop 33, the output of its Q terminal becomes "1" level. As a result, the down counter 32 starts counting down in accordance with the clock pulse input from the D terminal. The output of the terminal during counting is at the "1" level, and when the count ends and the contents of the down counter 32 reach "0" (clear state), it immediately becomes the "0" level. In response to this
The RS flip-flop 33 is reset, and the output of its Q terminal also changes to the "0" level. As a result, further down-counting is prohibited.

According to the above configuration, the up/down counter 11
The content of is converted into a corresponding pulse width, and the pulse is obtained from the Q terminal of the RS flip-flop 33. Therefore, the differentiating circuit 31, down counter 32, and RS flip-flop 33 constitute the second synthesis circuit 12 shown in FIG.

In this embodiment, in addition to the above, a synthesis auxiliary circuit 17 is additionally added. This is composed of some gate circuits, a K-adic (K is an integer smaller than L, and usually a value near L/2) counter, and an RS flip-flop circuit, and its purpose is to Example second synthesis circuit 12
In this paper, we apply a DC-like offset to the output, that is, the phase error information, and divide it into two pulses: a pulse that advances the phase (hereinafter referred to as a phase-advance pulse) and a pulse that delays the phase (hereinafter referred to as a phase-lag pulse). That's what I say. In general, this is preferable because the phase synchronization point (phase operating point) can be digitally determined accurately, and it also has the advantage of being well balanced with the embodiment of the speed error detection circuit 5 shown in FIG. be. In the figure, 34 is a K with a clock pulse input terminal CK, an output terminal, and a clear terminal CL.
It is a forward counter. 35 is an RS flip-flop which is set by the negative differential pulse of the differentiating circuit 31 and reset by the above terminal output, and has a positive logic output terminal Q, while the Q terminal is connected to the clear terminal CL of the K-ary counter 34. It is connected to the. Now, when the falling edge of the acceleration pulse or deceleration pulse is applied, a negative differential pulse is generated in the differentiator circuit 31, which causes the RS flip-flop 35
is set and the Q terminal goes to the "1" level. Then, the clearing of the K-ary counter 34 is canceled and counting starts. During counting, the output of the terminal is at the "1" level. When K clock pulses are counted, the instantaneous terminal changes from the "1" level to the "0" level. As a result, the RS flip-flop 35 is reset and the Q terminal output changes to the "0" level, so the K-ary counter 34 is cleared (reset). Above results
The Q terminal output of the RS flip-flop 35 provides a pulse with a width of Kτ from the falling edge of the acceleration pulse or deceleration pulse. 36 is an inverter circuit, and the output of the second synthesis circuit 12 of the embodiment (Q terminal output of the RS flip-flop 33)
Invert. 37 and 38 input the output of the inverter circuit 36 and the Q terminal output of the RS flip-flop 35 (that is, a pulse with a width of Kτ).
In the NOR circuit and the AND circuit, if the Q terminal output pulse of the RS flip-flop 33 is
If the pulse is longer than the width of τ, only that long pulse is
It is output from the NOR circuit 37, and if it is shorter, only the shorter amount is output from the AND circuit 38. The former corresponds to an advanced phase pulse for advancing the rotational phase of the motor 1, and the latter corresponds to a slow phase pulse for delaying the rotational phase of the motor 1.

As described above, the purpose of the synthesis auxiliary circuit 17 is to digitally provide the phase operating point with high accuracy, but it is also an essential element because the phase operating point can also be provided analogously at a later stage. isn't it.

In this embodiment, a down counter is used as the transfer counter, but a counter that transfers the complement of its contents from the up-down counter 11 and counts up the data may also be used.

The transfer counter is an up-down counter, and when the transferred content is greater than "K", it counts down to "K", and when it is less than "K", it counts up to "K", and the time required for each is It may also be applied with independent pulse widths. In this case, the synthesis auxiliary circuit 17 becomes unnecessary.

Next, FIG. 7 shows an embodiment of the filter circuit 13 of the present invention. In the figure, reference numerals 41 and 42 are charge pump circuits operated by acceleration pulses, deceleration pulses, leading phase pulses, and slow phase pulses, respectively.
44, transistors 45, 46
given on the basis of. Therefore transistor 45
and 46 turn on only when an acceleration pulse and a phase advance pulse are applied, respectively, and discharge current to an inverting and adding active filter circuit 58 constituted by an operational amplifier 53. On the other hand, the deceleration pulse and the slow phase pulse are applied to the bases of transistors 47 and 48, respectively, and the transistors are turned on only during that time.
However, in both cases, the inverting addition active filter circuit 5
Attract current from 8. The inverting addition active filter circuit 58 has the role of adding speed error information and cumulative speed error information (phase error information) and the role of an active filter. 54, 55, 5
6 is a resistor that determines the addition gain, and 57 is a filter capacitor. In addition, resistance 49,5
0, 51, and 52 are added to prevent leakage current.

By configuring as described above, speed error information and cumulative speed error information can be converted into smooth direct current. Note that this output is connected to the motor drive circuit 14.

FIG. 8 shows a variable pulse width generating circuit which should replace the first constant pulse width generating circuit 6 described above in the present invention in order to change the rotational speed of the motor 1. 6 in the diagram
Reference numeral 1 designates a programmable counter having a preset input terminal, and is configured to output a "0" level from the terminal after counting a value normally set in binary at the preset input X terminals (plurality). Note that 62 is a setting circuit for presetting the count number of the programmable counter 61, and is composed of a switch group 63 and a resistor group 64 for applying a "1" level.

According to this method, the count number of the N-ary counter in the first constant pulse width generating circuit 6 is not fixed and can be changed freely, so that the above-mentioned formula 1/f ₀ =Nτ + Mτ The reference frequency f ₀ determined by can be freely changed, and as a result, the rotation speed of the motor can be changed.

Furthermore, as is clear from the above equation, it goes without saying that the number of revolutions of the motor 1 can be changed even if the count number M of the M-ary counter of the constant pulse width generation circuit 7 is changed. The same effect can be expected even if the counter is replaced with the programmable counter described above. Also, depending on the case, N, N
The same effect can be expected even if both are made variable.

As described above, the characteristics of the motor speed control device according to the present invention can be summarized as follows.

(1) By cumulatively counting the speed error information with an up-down counter and integrating it digitally, the rotational phase of the motor and the phase of the reference pulse can be directly calculated using a conventional phase comparator. It is possible to obtain cumulative speed error information that is completely equivalent to the phase error information obtained by comparing the two, and thereby it is possible to perform phase control of the motor and improve load stability.

(2) Since the above means is composed of a digital circuit mainly consisting of a counter, it is possible to perform phase control with little change in ambient temperature or change over time.

(3) The above cumulative speed error information is the motor rotation speed,
Since it exhibits so-called saturation type characteristics with respect to phase, it has extremely excellent phase synchronization pull-in characteristics.

(4) Since the speed error detection circuit and cumulative speed error detection circuit can all be configured with digital circuits,
Suitable for IC such as ^I2L or C-MOS,
Unlike conventional sample-and-hold error detection methods, external elements such as capacitors are not required, resulting in cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the concept of the present invention.
FIG. 2 is an operation time chart of the speed error detection circuit of the present invention, FIG. 3 is an explanatory diagram modeling the characteristics of an up-down counter, and FIG. 4 is a block diagram showing an embodiment of the speed error detection circuit of the present invention. 5 is a block diagram showing one embodiment of the cumulative speed error detection circuit of the present invention, FIG. 6 is a block diagram showing another embodiment of the cumulative speed error detection circuit of the present invention, and FIG. 7 is a block diagram of the present invention. FIG. 8 is a block diagram showing one embodiment of the filter circuit of the invention. FIG. 8 is a block diagram of a variable pulse width generation circuit to replace the first constant pulse width generation circuit. DESCRIPTION OF SYMBOLS 1...Motor, 2...Tachometer generator, 4...Reference frequency signal generation circuit, 5...Speed error detection circuit, 6
...First constant pulse width generating circuit, 7...Second constant pulse width generating circuit, 8...First synthesis circuit, 9...Cumulative speed error detection circuit, 11...Up-down counter, 12...Second synthesis circuit , 13... Filter circuit, 14... Motor drive circuit, 22... N-ary counter, 24... M-ary counter, 32... Down counter, 34... K-ary counter, 41, 42... Charge pump circuit, 61... Programmable counter.

Claims (1)

[Scope of Claims] 1. A tachometer generator that extracts and outputs a rotation signal with a frequency proportional to the rotation speed of the motor from the motor, and a reference frequency signal generator that outputs a clock signal that is to be a reference for the rotation of the motor; An N-ary counter that is triggered by the rotation signal and starts counting the clock signal, keeps the first level while counting N (N: integer), and immediately changes to the second level after counting N. a first constant pulse width generating circuit configured, and a period of counting of the clock signal triggered by the trailing edge of the output pulse of the first constant pulse width generating circuit and counting M times (M: an integer). a second constant pulse width generating circuit composed of an M-ary counter that maintains a first level and immediately changes to a second level after counting M counts; and the first and second constant pulse width generating circuits. a first synthesis circuit that synthesizes output pulses of the circuits and provides speed error information of the motor;
an up-down counter that cumulatively digitally integrates the speed error information using the output of the first synthesis circuit and the clock signal, and provides cumulative speed error information of the motor according to the contents of the up-down counter. It is characterized by comprising a second synthesis circuit, a filter circuit that smoothes both outputs of the first and second synthesis circuits, and a motor drive circuit that drives the motor according to the output of the filter circuit. Motor speed control device. 2. The first synthesis circuit includes a logic circuit that performs the logical sum and AND of the output pulses of the first and second constant pulse width generation circuits, and the second synthesis circuit includes an up-down counter. A D/A that extracts the contents of in parallel and converts it from digital to analog.
A motor speed control device according to claim 1, characterized in that the motor speed control device includes a converter. 3. The first synthesis circuit includes a logic circuit that performs the logical sum and logical product of both output pulses of the first and second constant pulse width generation circuits, and the second synthesis circuit includes a A patent characterized in that it includes a transfer counter to which contents are transferred, and a logic circuit that counts up or down the counter and generates a pulse with a time width corresponding to the transferred contents. A motor speed control device according to claim 1.