JPS627702B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor memory characterized by having a static induction thyristor.

Semiconductor memory using conventional thyristors is
The thyristor contained therein has poor high frequency characteristics and cannot be used as a high-speed memory. In particular, the gate has a very large gate time constant due to large lateral resistance and large parasitic capacitance, and it is difficult to control the accumulated carriers. It has many drawbacks, such as:

On the other hand, a semiconductor memory using a static induction transistor as a memory component has been proposed, and its high speed, low power consumption, high integration, and low noise are attracting attention. When a semiconductor memory is used as a static memory, the number of its constituent elements increases, which becomes an obstacle to higher integration and lower energy consumption. Also,
In order to achieve high integration with a small number of constituent elements, it is necessary to adopt a dynamic memory configuration.

The present invention eliminates the drawbacks of the conventional thyristor-based semiconductor memory and electrostatic induction transistor-based semiconductor memory, and its purpose is to provide ultra-high speed, low energy, low noise and highly integrated state. The goal is to provide storage memory.

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a perspective view of an embodiment of the present invention, in which almost parallel lines of p-type high impurity density are buried in an n-type low impurity density (hereinafter referred to as ^n- ) substrate 1 in which a channel is formed. (hereinafter referred to as p ⁺ ), a p ⁺ gate region 3 formed in a substantially mesh-like manner exposed on the surface, and an n-type high impurity density (hereinafter referred to as n ^{+ )} formed in the mesh. ), and a wiring 5 connecting the cathode region 4 in a direction crossing the buried region 2. The portion surrounded by a broken line 6 in the figure is one cell, which is formed by one n-channel electrostatic induction thyristor.

FIG. 2 is a sectional view of one cell of the embodiment shown in FIG. 1. The channel region 7 has a surface p ⁺
It is an electrostatic induction thyristor which is almost pinched off by the depletion layer 8 formed by the region 3 (which becomes the gate), and uses the buried p ⁺ region 2 as an anode and the surface n ⁺ region 4 as a cathode. The static characteristics of an electrostatic induction thyristor are well known, and an example thereof is shown in FIG. For example, when the gate voltage is 0, the blocking voltage changes as shown in curve a, when a negative voltage is applied to the gate, the blocking voltage changes as shown in curve b, and when a positive voltage is applied, as shown in curve c, the blocking voltage changes. The curve when the gate voltage is 0 is not limited to a, but may vary in the b and c directions. For example, when looking at curve a and using a load that provides a load line like the broken line in the figure, the initial operating point is point A, which is in a blocking state and no current flows. Next, when applying a larger blocking voltage V,
The operating point moves to point B and becomes conductive. Memory is performed using these points A and B.

FIG. 4 is a circuit diagram of the embodiment shown in FIG. 1, and the electrostatic induction thyristor 9 in the figure _is connected to lines X ₁ ,
... is connected to the anode, and the cathode is connected to the lines Y ₁ , Y ₂ , ... in the Y direction, and the gates are all connected and connected to the cathode through a resistor, or
A certain gate voltage is applied.

If you want to write to a certain bit, for example 10, set V ₂ to X ₁ and V ₃ to Y ₂ (where V ₂ <
When a voltage (V ₁ , V ₃ <V ₁ , V ₂ +V ₃ >V ₁ ) is applied, only the thyristors included in 10 become conductive, and no change occurs in the other thyristors. In the case of reading, the voltage between X ₁ and Y ₂ is lower than the others, so of course it is sufficient to detect this. Further, the written information is retained simply by applying a voltage slightly higher than the minimum retention voltage between the anode and cathode of the thyristor. In the manner described above, a static memory capable of non-destructive reading is realized. Electrostatic induction thyristors are ultra-fast, low control energy,
The low noise feature allows for very high speed, low energy, low noise memory. It is of course also possible to perform writing and reading by applying a voltage to the gate and changing the blocking voltage, and writing and reading can be performed more reliably and at a lower voltage. Of course, destructive reading is also possible.

In the embodiment shown in FIG. 1, the electrostatic induction thyristor is of the p-gate type, but of course it can be made of the n-gate type by reversing the conductivity type of each part, and by changing the p ⁺ region 2 to n ⁺ The n ⁺ region 4 can also be made p ⁺ . In this case, it is only necessary to form a p ⁺ region on the surface of the element, which greatly facilitates manufacturing.

FIG. 5 shows another embodiment of the present invention, in which an n ^- region 11 in which a channel is formed is replaced by a p ⁺ anode region 12.
p ⁺ formed on the top and continuous in almost one direction
An n ⁺ cathode region 14 is surrounded by the gate region 13 and connected to the gate region 13 by a wiring 15 in a direction crossing the gate region 13 . A wiring diagram of this memory is shown in FIG. In this case, since the anode is common and the memory operation is performed between the gate and the cathode, operation at a very low voltage is possible. In the case of this embodiment as well, the conductivity type can be changed as in the first embodiment and has the same characteristics.

FIG. 7 shows still another embodiment of the present invention.
A second gate 22 is added to the embodiment shown in the figure, and either the first gate 21 or the second gate 22 is connected in one direction as in the previous embodiment, and the other is connected in a continuous manner. As a structure, it is possible to lower the voltage during writing.

FIG. 8 shows still another embodiment of the present invention.
At the bottom of the embodiment shown in the figure, a p-type low impurity density (hereinafter referred to as p ^- ) region 31 is formed as a channel, and an n ⁺ region 32 is formed in the channel to form a gate. is similar to the embodiment shown in FIG. In this embodiment, by applying a bias to the n ⁺ region 32, even higher speeds can be achieved.

In the above embodiments, electrostatic induction thyristors are used as constituent elements, but each gate thereof can also be of a beam-based type. Examples of the base shape are shown in FIGS. 9a to 9c. A is a region in which p ⁺ gate regions 41 are connected by a thin region 42 having a lower impurity density (hereinafter referred to as p). b is a thin p-region 43, and c is a structure in which they are connected by a p-region 44 having approximately the same thickness. These p-regions or thin regions, including structures in which the base portion is made up of a uniform p-region, are used with only punch-through or with punch-through, and are used in static induction transistors or static This is the bipolar transistor mode of the inductive thyristor. High impurity density regions or metal regions or MOS, especially in parts of the base
When structural parts are brought into contact and voltage is supplied from these parts, the characteristics of a static induction transistor or a static induction thyristor are utilized. Therefore, these high impurity densities or metal or MOS
The base portion is configured such that the length from the structural portion to the controlled base portion is approximately within the Debye length.

The embodiments described above can be easily manufactured by making full use of various well-known techniques such as selective diffusion, selective growth, ion implantation, microfabrication, selective etching, plasma etching, sputtering, oxidation, and CVD.

Next, an example of a method for manufacturing a semiconductor memory according to the present invention will be described using FIG. 1 as an example. FIG. 10 is a sectional view showing the process. ^Selective diffusion ⁽ surface impurity density 5 ×
10 ¹⁹ cm ^-3 ). (Fig. 10a) Then n ^- layer 1
03 (impurity density: 1 x 10 ¹⁴ cm ^-3 ) by epitaxial growth b, and p ⁺ region 104 formed by selective diffusion (surface impurity density: 1 x 10 ²⁰ cm ^-3 ) into a net shape. c.

Next, an n ⁺ region is formed in the mesh of the p ⁺ region by selective diffusion (surface impurity density: 1×10 ²⁰ cm ⁻³ ). d Finally, form the electrodes to complete the process. The electrode to the buried layer 102 is connected to the buried layer 1 by forming a diffusion layer from the surface.
02, or may be partially etched to expose the buried layer 102. Of course, the specific resistance, impurity density, surface impurity density, thickness, dimensions, shape, mutual positional relationship, etc. shown in the above examples are not limited to these. For example, the dimensions of the mesh may be formed so that the meshes are almost pinched off by the diffusion potential, and the impurity density may also be changed depending on the required resistance value. Furthermore, lattice distortion compensation technology is effective in the high impurity density region and its surroundings.

The conductivity type etc. is not limited to this example and can be changed, and the impurity density etc. is, for example, 10 ¹¹ to 10 ¹⁷ cm ^-3 in a low impurity density region and 10 ¹⁶ to 10 ²² in a high impurity density region. It can be varied over a wide range such as cm ^-3 . Also, although the explanation has focused on static memory with non-destructive readout, it is of course possible to perform destructive readout, and it is also possible to use dynamic memory that utilizes the difference in turn-on and turn-off times.
Of course, it can also be charged and discharged.

Furthermore, the shape and relative position of each region are not limited to those in the embodiments, and may be round or other shapes as long as they can realize a pinch-off state. Alternatively, part of the gate may be a floating gate. Further, a structure in which each gate region is separated may also be adopted. The gate can be floating, biased, connected via a resistor or directly to another electrode. Furthermore, in the embodiment, the structure is such that the current flows between the anode and the cathode almost perpendicularly to the substrate surface, but the present invention is not limited to this, and a horizontal structure may be used in which the current flows in another direction, for example, substantially parallel to the substrate surface. Furthermore, which electrodes are shared and which electrodes are made substantially parallel in one direction is not limited to the embodiment.

Furthermore, it is also possible to make the gate or channel, or the vicinity thereof, sensitive to light and to configure a photothyristor for use. In this case, it can be used as an image sensor or the like.

As explained above, by using electrostatic induction thyristors as components, the present invention can realize ultra-high-speed, low-energy, low-noise semiconductor memory with high integration, and in particular, static memory can be easily manufactured. It has a structure that can be realized with a single element, and has extremely high industrial value.

[Brief explanation of the drawing]

Fig. 1 is a perspective view of an embodiment of the present invention, Fig. 2 is a sectional view of one cell shown in Fig. 1, Fig. 3 is an example of characteristics of a static induction thyristor, and Fig. 4 is a circuit diagram of Fig. 1. ,
FIG. 5 is a perspective view of another embodiment of the present invention, FIG. 6 is a circuit diagram of FIG. 5, and FIGS. 7 and 8 are cross-sectional views of one cell of still another embodiment of the present invention. FIG. 9 is a sectional view of a gate portion of still another embodiment of the present invention, and FIG. 10 is a sectional view showing the process of FIG. 1.

Claims (1)

[Scope of Claims] 1. A channel region of a first conductivity type and a low impurity density; and a cathode region of a first conductivity type and a high impurity density, at least a part of which is exposed in an island shape on one surface of the channel region. , a gate region of a second conductivity type and having a high impurity density disposed to substantially surround the cathode region, and an anode region of a second conductivity type and having a high impurity density embedded in the channel region. A semiconductor characterized in that, in a static induction thyristor, a conduction state between the cathode region and the anode region is changed by applying a predetermined voltage to the gate region or the anode region to perform a memory operation. memory. 2. The semiconductor according to claim 1, characterized in that it has at least one arrangement in which a plurality of the anode regions of the electrostatic induction thyristor are connected in one direction, and all the gate regions are connected. memory. 3. The semiconductor memory according to claim 1, characterized in that it has at least one array in which a plurality of the gate regions of the electrostatic induction thyristors are connected in one direction, and all the anode regions are connected. . 4. Claims 1 to 3 above, characterized in that the electrostatic induction thyristor has a second gate region of a second conductivity type and high impurity density in the channel region under the gate region. The semiconductor memory according to any one of the following. 5 A second channel region of a second conductivity type and low impurity density is provided in the channel region of the electrostatic induction thyristor, and a first conductive channel region is provided in the second channel region under the gate region. 4. The semiconductor memory according to claim 1, wherein a second gate having a high impurity density is embedded in the semiconductor memory. 6. Claims 1 to 5, characterized in that the gate region of the electrostatic induction thyristor is also connected below the cathode region.
A semiconductor memory according to any one of paragraphs.