JPS627985B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of designing a logical device to make maintenance and diagnosis of the logical device easy and efficient, and in particular, the present invention relates to a method of designing a logical device to make maintenance and diagnosis of the logical device easy and efficient. This article relates to the address scan-out method.

When a logic circuit is converted into an LSI, it is extremely difficult to create the test data required to determine the acceptability of the LSI itself or the logic device that uses it, and to analyze failures due to the relationship between the number of input/output pins and the degree of integration. However, the scan-out method is known to be an effective means of knowing more about the state of internal logic. The logical device has failed and
This scan-out method is used as a means of determining the faulty part and cause when an error occurs in operation, and the faulty part and cause are determined by knowing the internal state of the logic device from the outside. It is.

The conventional scan-out method has a configuration as shown in FIG. It consists of a decoder 6 and a multiplexer 7, and in FIG.
One of the internal logic outputs 10 and 10' in the internal logic circuit 2 designated by the address signals 8 and 8' is designated and selected by the decoder 6 and the multiplexer 7, and is output externally by the scan-out signal line 9. It is something that is sent out.

Here, one address instruction from the outside corresponds to one output of the internal logic, such as reading out the logical value of one logic section of the internal logic, and therefore, one address instruction reads one bit. Only the information indicating the state of the internal logic is read out, and therefore there is a need to re-edit it later in units of words or bytes.

This processing time has caused an extremely large problem in the case of urgent failure analysis of logic devices and the like.

The object of the present invention is to provide a scan-out system that does not have the above-mentioned drawbacks.
That is, a shift register that can be reset is provided at the output of the conventional scan-out circuit, and
The internal logic information obtained each time a new scan-out address is given is stored in the serial input of this shift register in sequence, and the internal logic address designation takes into consideration re-editing of this shift register output. When specifying a fictitious address, the contents of the shift register are read out all at once by storing a logical value "0" in the shift register.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing a scan-out method according to an embodiment of the present invention. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals.

In addition to the conventional scan-out circuit, the logic device 1 includes a shift register 12 at the output of the multiplexer 7, and a fictitious address detection circuit 11 that has a function of detecting a fictitious address when specifying an address. and writes a logical value “0” to the shift register 12 by detecting the fictitious address.
An AND gate circuit 11', a shift clock input line 14 for writing internal logic scanout information into the shift register, and a reset input line 13 for resetting all the flip-flops of the shift register at once are added.

In the figure, internal logic circuit outputs 10 and 10' constituting an internal logic circuit 2 of a logic device 1 are multiplexed with logic outputs that are arbitrarily selected at the time of design to be useful when maintaining and diagnosing the logic device from the outside. 7
connected to the input of Each of these logic outputs is logically ANDed with each address designation line in the multiplexer 7, and each output is collected as a logical sum for all addresses and is output as a serial input of the shift register 12 to the shift clock input 1 in the order of address designation.
4, the bits are shifted from the lower bits to the upper bits and stored in sequence. Figure 3 is the second
3 shows an embodiment of the shift register shown in the figure.
In the figure, flip-flops 15 and 15' constitute a shift register 12, which has the function of resetting all bits at once by means of a reset input 13. In the address scan-out operation, the shift register 12 is first reset, and then the logic state of the internal logic addressed by the address inputs 8, 8' is changed to the flip-flop 15, 1 as described above.
5', and as a result, the parallel outputs of all bits of the shift register are read out to the address scan-out output signal lines 9, 9'. The read data that is sequentially accumulated and stored in the shift register 12 requires separation between data for various reasons such as the internal logic configuration and the system configuration of the logic device. In general, a fictitious address such as the "0" address is given to the address that is not used. In this case, the virtual address detection circuit 11 and the AND gate circuit 11' for inserting a logic value "0" into the shift register operate to insert a logic value "0" into the shift register 12.

By configuring the shift register in this way and operating the address scan circuit, the conventional method of specifying an address for each logic circuit output of the internal logic and reading out one bit can be changed to the shift register.
By providing a bit flip-flop,
It becomes possible to perform scan-out reading once every time address specification is repeated n times. Furthermore, if addresses can be specified consecutively, by adding a count function (not shown) that counts the number of consecutive addresses and the number of addresses, it is possible to specify n addresses from an external device in one. It is also possible to designate multiple addresses. Furthermore, although the above explanation refers to a logic device, when applied to devices such as LSIs that have a limited number of input/output terminals, the input to the address register is treated as a serial input, and a shift clock and counter are provided. It is also possible to save significantly on the number of input pins.

Furthermore, the portions separated by broken lines in FIG. 2, such as the address register 5, shift register 12, and virtual address detection circuits 11 and 11', are added to the conventional scan-out circuit according to the present invention. It is also possible to separate the logical device to be diagnosed and use the address register, shift register, etc. in common for a plurality of logical devices.

As described above, according to the present invention, it is possible to establish a means to easily know the state of internal logic during maintenance and diagnosis of a logic device, so that efficient pass/fail determination and failure analysis can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a scan-out circuit of a conventional logic device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an embodiment of the shift register of FIG. be. 1...Logic device, 2...Internal logic circuit, 3,
3'...Input signal line, 4, 4'...Output signal line, 5
...Address register, 6...Decoder, 7...
Multiplexer, 8, 8'...address input line,
9,9'...Scan out signal line, 10,1
0'... Internal logic output, 11... Fictitious address detection circuit, 11'... AND gate circuit, 12...
Shift register, 13...Reset input line, 14
...Shift clock input line, 15, 15'...Flip-flop.

Claims (1)

[Claims] 1. In a scan-out circuit that arbitrarily addresses the internal logic state of a logic circuit and reads it out to the outside, a shift register that can be reset is provided at the output section of the scan-out circuit,
A scan-out circuit that sequentially stores scan-out results in said shift register, and stores logic "0" in said shift register in response to a scan-out for a fictitious address instruction.