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JPS628055B2 - - Google Patents
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JPS628055B2 - - Google Patents

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Publication number
JPS628055B2
JPS628055B2 JP55181496A JP18149680A JPS628055B2 JP S628055 B2 JPS628055 B2 JP S628055B2 JP 55181496 A JP55181496 A JP 55181496A JP 18149680 A JP18149680 A JP 18149680A JP S628055 B2 JPS628055 B2 JP S628055B2
Authority
JP
Japan
Prior art keywords
signal
circuit
prediction
level
compression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55181496A
Other languages
Japanese (ja)
Other versions
JPS57104321A (en
Inventor
Toshio Ooshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18149680A priority Critical patent/JPS57104321A/en
Publication of JPS57104321A publication Critical patent/JPS57104321A/en
Publication of JPS628055B2 publication Critical patent/JPS628055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00Colour television systems
    • H04N11/04Colour television systems using pulse code modulation
    • H04N11/042Codec means
    • H04N11/046DPCM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Description

【発明の詳細な説明】 本発明は予測符号化装置に関し、特にカラーテ
レビジヨン信号のごとく複数の信号を多重化した
信号を直接符号化する予測符号化装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a predictive coding device, and more particularly to a predictive coding device that directly codes a signal obtained by multiplexing a plurality of signals, such as a color television signal.

カラーテレビジヨン信号は画像の輝度信号と色
度信号とを周波数多重化した信号でありこれを効
率よく符号化する予測符号化装置として、輝度信
号と色度信号とを分離してそれぞれの信号を予測
符号化する分離符号化方式を用いる装置と、多重
化された信号を分離せずに直接予測符号化する直
接符号化方式を用いる装置とがある。分離符号化
方式を用いる装置は信号分離回路、信号合成回路
および複数個の予測符号化回路を具備せねばなら
ぬため規模が大きくなるのに対して、直接符号化
方式を用いる装置は信号分離回路および信号合成
回路が不要であり1個の予測符号化回路を具備す
るだけなので装置規模を小さくすることができ
る。
A color television signal is a signal obtained by frequency multiplexing the luminance signal and chromaticity signal of an image.As a predictive encoding device that efficiently encodes this signal, the luminance signal and chromaticity signal are separated and each signal is processed. There are devices that use a separate coding method that performs predictive coding, and devices that use a direct coding method that directly predictively codes multiplexed signals without separating them. A device using a separate coding method must be equipped with a signal separation circuit, a signal synthesis circuit, and a plurality of predictive coding circuits, resulting in a large scale, whereas a device using a direct coding method requires a signal separation circuit. Also, since a signal synthesis circuit is not required and only one predictive coding circuit is provided, the scale of the apparatus can be reduced.

第1図は従来の直接符号化方式の予測符号化装
置を示すブロツク図である。同図においてカラー
テレビジヨン信号が入力端子1から入力される
と、入力信号は減算回路2を通り予測回路3から
の予測信号を減算された誤差信号となり量子化回
路4へ送られる。該誤差信号は量子化回路4にお
いて周期Tで標本化され量子化されて差分パルス
変調符号(以下DPCM符号と略称する)として出
力端子5より出力されるとともに予測回路3へ送
られる。第2図は第1図の量子化回路4の量子化
特性を例示する特性図である。同図に例示するよ
うに、量子化回路4の特性としては一般に非直線
の量子化特性30が用いられる。このような特性
を用いることにより、誤差信号は小さいが視覚的
に量子化雑音が見え易い平坦な画像信号の部分を
細かく量子化し、誤差信号は大きいが視覚的に量
子化雑音が見え難い画像信号エツジ部分を粗く量
子化して、視覚にあつた量子化を行なうことがで
きる。第1図の予測回路3へ送られた信号は加算
回路6を通り予測器7からの予測信号を加算され
て予測器7へ送られる。予測器7の伝達関数P
(Z)は次式で与えられる。
FIG. 1 is a block diagram showing a conventional predictive coding apparatus using a direct coding method. In the figure, when a color television signal is input from an input terminal 1, the input signal passes through a subtraction circuit 2, and a prediction signal from a prediction circuit 3 is subtracted therefrom to form an error signal, which is then sent to a quantization circuit 4. The error signal is sampled and quantized with a period T in the quantization circuit 4, and is outputted from the output terminal 5 as a differential pulse modulation code (hereinafter abbreviated as DPCM code) and sent to the prediction circuit 3. FIG. 2 is a characteristic diagram illustrating the quantization characteristics of the quantization circuit 4 of FIG. 1. As illustrated in the figure, a non-linear quantization characteristic 30 is generally used as the characteristic of the quantization circuit 4. By using these characteristics, parts of a flat image signal where the error signal is small but quantization noise is easily visible can be finely quantized, and image signals where the error signal is large but quantization noise is difficult to visually see can be finely quantized. It is possible to coarsely quantize the edge portions to achieve quantization that is suitable for visual perception. The signal sent to the prediction circuit 3 in FIG. Transfer function P of predictor 7
(Z) is given by the following formula.

P(Z)=0.5Z-1+bZ-2−0.5bZ-3 ただし上式においてb=1−(1/2),Z-1
-jT、またTは量子化回路4の標本化周期を
示す。予測器7の出力信号はデイジタル・アナロ
グ変換器8を通りアナログ信号に変換された予測
信号となり減算回路2へ送られて入力端子1から
の入力信号との差である前記誤差信号が得られ
る。
P(Z)=0.5Z -1 +bZ -2 -0.5bZ -3 However, in the above formula, b=1-(1/2) 4 , Z -1 =
e −jT , or T indicates the sampling period of the quantization circuit 4. The output signal of the predictor 7 passes through a digital-to-analog converter 8, becomes a predicted signal converted into an analog signal, and is sent to a subtraction circuit 2, where the error signal, which is the difference from the input signal from the input terminal 1, is obtained.

従来の直接符号化方式を用いた予測符号化装置
は、誤差信号のレベルの発生分布が相異なる輝度
信号と色度信号とを分離せずに予測符号化を行な
うので、輝度信号および色度信号のそれぞれに対
し最適な量子化ができず分離符号化方式を用いた
ものに比べて符号化効率が劣るために、同一伝送
速度の下では信号対雑音比が劣りまた同一画質の
下では符号伝送速度の低減率が小さくなるという
欠点を有する。また量子化回路の量子化特性は可
変ではないから、誤差信号のレベルの発生分布が
時間の経過に伴なつて大幅に変化すると信号対雑
音比の劣化を生ずるという欠点がある。
A predictive coding device using a conventional direct coding method performs predictive coding without separating a luminance signal and a chrominance signal, which have different error signal level generation distributions. Since optimal quantization cannot be performed for each of This has the disadvantage that the speed reduction rate is small. Furthermore, since the quantization characteristics of the quantization circuit are not variable, there is a drawback that the signal-to-noise ratio deteriorates if the generation distribution of the level of the error signal changes significantly over time.

本発明の目的は前記の欠点を除去して誤差信号
の輝度信号成分および色度信号成分のレベルの発
生分布が時間とともに変化するのに応じて適応的
に動作して信号対雑音比および符号化効率に良好
な直接符号化を行なうことができる予測符号化装
置を提供することにある。
It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a signal-to-noise ratio and a coding system that adaptively operates as the generation distribution of the levels of the luminance signal component and the chrominance signal component of the error signal changes over time. An object of the present invention is to provide a predictive encoding device that can perform direct encoding with good efficiency.

本発明の装置は、複数の信号成分を含む入力信
号と予測信号との差を表わす誤差信号を送出する
減算回路と、前記誤差信号に含まれる前記複数の
信号成分を分離して複数の分離信号を送出する分
離回路と、前記複数の分離信号のうち少なくとも
1つの分離信号のレベルの発生分布を検知して前
記少なくとも1つの分離信号にそのレベルの発生
分布に適応するレベル圧縮を行なう適応圧縮回路
と、前記適応圧縮回路が送出する複数の信号を加
算する加算回路と、前記加算回路が送出する信号
を量子化して出力する量子化回路と、前記予測信
号を前記量子化回路の出力信号より予測して送出
する予測回路とを含んでいる。
The apparatus of the present invention includes a subtraction circuit that sends out an error signal representing the difference between an input signal including a plurality of signal components and a predicted signal, and a subtraction circuit that separates the plurality of signal components included in the error signal to produce a plurality of separated signals. and an adaptive compression circuit that detects the level occurrence distribution of at least one of the plurality of separated signals and performs level compression on the at least one separated signal in accordance with the level occurrence distribution. an addition circuit that adds a plurality of signals sent out by the adaptive compression circuit; a quantization circuit that quantizes and outputs the signal sent out by the addition circuit; and a prediction signal predicted from the output signal of the quantization circuit. and a prediction circuit that sends out the prediction.

次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.

第3図は本発明の第一の実施例を示すブロツク
図である。同図においてカラーテレビジヨン信号
が入力端子1から入力され減算回路2を通つて予
測回路3からの予測信号との差である誤差信号と
なり分離回路9へ送られる。分離回路9は副搬送
波周波数で変調された色度信号成分のみを通過さ
せる帯域フイルタと、輝度信号成分を通過させか
つ色度信号成分を阻止する帯域阻止フイルタとか
ら成る分波器である。誤差信号は分離回路9を通
り色度信号成分ならびに輝度信号成分とに分離さ
れ2つの分離信号となりそれぞれ適応圧縮回路1
0ならびに11に送られて各信号成分のレベルの
発生分布に適応するレベル圧縮を受けて、加算回
路13においてふたたび色度信号成分と輝度信号
成分とが加算され合成される。加算回路13から
の信号は量子化回路4において周期Tで標本化さ
れ量子化されてDPCM符号となり出力端子5から
出力されるとともに、予測回路3へ送られる。予
測回路3ではDPCM符号と予測器7の出力とが加
算回路6において加算されて予測器7へ送られ、
予測器7は次の標本化時刻における予測信号を送
出する。予測信号はデイジタル・アナログ変換器
8を通りアナログ信号に変換された予測信号とし
て減算回路2へ送られる。同期入力端子12から
は、同期信号分離装置からフレーム同期パルスが
入力端子1からの入力信号と同期して入力され
る。このフレーム同期パルスは量子化回路4から
送られる標本化パルスとともに適応圧縮回路1
0,11に印加されて、以下に説明するごとく適
応圧縮回路10,11の動作を制御する。
FIG. 3 is a block diagram showing a first embodiment of the present invention. In the figure, a color television signal is inputted from an input terminal 1, passes through a subtraction circuit 2, becomes an error signal which is the difference from a prediction signal from a prediction circuit 3, and is sent to a separation circuit 9. The separation circuit 9 is a duplexer composed of a bandpass filter that passes only the chromaticity signal component modulated at the subcarrier frequency, and a bandstop filter that passes the luminance signal component and blocks the chromaticity signal component. The error signal passes through the separation circuit 9 and is separated into a chromaticity signal component and a luminance signal component, resulting in two separated signals, each of which is sent to the adaptive compression circuit 1.
0 and 11 and subjected to level compression adapted to the level generation distribution of each signal component, the chromaticity signal component and the luminance signal component are again added and synthesized in the adder circuit 13. The signal from the adder circuit 13 is sampled and quantized at a period T in the quantization circuit 4 to become a DPCM code, which is output from the output terminal 5 and sent to the prediction circuit 3. In the prediction circuit 3, the DPCM code and the output of the predictor 7 are added in the adder circuit 6 and sent to the predictor 7.
The predictor 7 sends out a predicted signal at the next sampling time. The predicted signal passes through the digital-to-analog converter 8 and is sent to the subtraction circuit 2 as a predicted signal converted into an analog signal. A frame synchronization pulse is input from the synchronization signal separation device to the synchronization input terminal 12 in synchronization with the input signal from the input terminal 1 . This frame synchronization pulse is sent to the adaptive compression circuit 1 along with the sampling pulse sent from the quantization circuit 4.
0,11 to control the operation of the adaptive compression circuits 10,11 as described below.

第4図は第3図に示す第一の実施例のブロツク
図のうち適応圧縮回路10,11の部分を示すブ
ロツク図であり、第6図aおよびbはそれぞれ第
4図の適応圧縮回路の動作を説明するための誤差
信号のレベル発生分布図およびレベル圧縮回路の
特性図である。第4図に示すように、適応圧縮回
路10,11はいずれも圧縮回路20と制御回路
21とから構成される。
4 is a block diagram showing the adaptive compression circuits 10 and 11 in the block diagram of the first embodiment shown in FIG. 3, and FIG. FIG. 2 is a level generation distribution diagram of an error signal and a characteristic diagram of a level compression circuit for explaining the operation. As shown in FIG. 4, each of the adaptive compression circuits 10 and 11 includes a compression circuit 20 and a control circuit 21.

本実施例に用いた制御回路21は、誤差信号の
レベルすなわち予測誤差の発生分布を毎フレーム
ごとに計測しその結果に対応して圧縮回路20の
レベル圧縮特性を切替えることにより、予測誤差
の発生分布がつねに0の近傍に集中するように制
御している。第3図のブロツク図の量子化回路4
は、第6図aの分布40に示すごとく予測誤差の
発生分布が0の近傍に集中する信号に対して最適
な信号対雑音比が得られるように、第2図に示す
ような量子化特性30を有する。予測誤差の発生
分布が第6図aの分布41あるいは42のごとく
0の近傍への集中度が低くなるときは、それぞれ
第6図bに示すレベル圧縮特性45あるいは46
をもつ圧縮回路によつて信号レベルの発生分布が
0近傍に集中するようにレベルを変換することが
できる。すなわち分離信号の予測誤差が各フレー
ムごとに第6図aに示す分布40,41,42の
うちいずれに属するかを制御回路21が計測し
て、分布40のときは分離信号は同図bのレベル
圧縮特性44を通りすなわち第4図において分離
信号は直接スイツチ回路14へ送られスイツチ回
路14が閉じて加算回路13へ送出され、分布4
1(あるいは42)のときは分離信号は第6図b
のレベル圧縮特性45(あるいは46)を通りす
なわち第4図において分離信号はレベル圧縮特性
45(あるいは46)をもつ圧縮回路15(ある
いは16)を通りスイツチ回路17(あるいは1
8)が閉じて加算回路13へ送出される。圧縮回
路15,16はいずれも抵抗とダイオードから成
る周知の回路であり、スイツチ回路14,17,
18はいずれも印加される制御信号がハイレベル
のとき閉じて導通状態となり、制御信号がローレ
ベルのとき開いて切断状態となるアナログゲート
である。なお以上のように各分離信号のレベルを
圧縮することにより量子化雑音は低減できるが復
調された信号には波形歪を生じて歪雑音が増加す
るので、レベル圧縮特性は量子化雑音と歪雑音と
のトレードオフを行ない信号対雑音比が最大とな
るよう決定する。そのようにレベル圧縮特性を決
定すれば、受信側では送信側の圧縮回路に対応す
る伸長回路を必要とせず、したがつて送信側でど
の圧縮回路を使つているかを知らせる情報を伝送
する必要はない。
The control circuit 21 used in this embodiment measures the level of the error signal, that is, the distribution of occurrence of prediction errors for each frame, and switches the level compression characteristics of the compression circuit 20 according to the result, thereby reducing the occurrence of prediction errors. The distribution is controlled so that it always concentrates around 0. Quantization circuit 4 in the block diagram of Figure 3
is the quantization characteristic shown in Fig. 2 so that the optimum signal-to-noise ratio can be obtained for a signal whose occurrence distribution of prediction errors is concentrated near 0 as shown in the distribution 40 of Fig. 6a. It has 30. When the occurrence distribution of prediction errors is less concentrated in the vicinity of 0, as shown in distribution 41 or 42 in FIG. 6a, the level compression characteristic 45 or 46 shown in FIG. 6b, respectively, is applied.
It is possible to convert the level so that the signal level generation distribution is concentrated around 0 using a compression circuit having the following. That is, the control circuit 21 measures for each frame to which of the distributions 40, 41, and 42 the prediction error of the separated signal belongs as shown in FIG. The separated signal passes through the level compression characteristic 44, that is, in FIG.
When it is 1 (or 42), the separated signal is as shown in Figure 6b.
In other words, in FIG.
8) is closed and sent to the adder circuit 13. Compression circuits 15 and 16 are both well-known circuits consisting of resistors and diodes, and switch circuits 14, 17,
Reference numeral 18 designates analog gates that are closed and conductive when the applied control signal is at a high level, and open and disconnected when the control signal is at a low level. Although quantization noise can be reduced by compressing the level of each separated signal as described above, waveform distortion occurs in the demodulated signal and distortion noise increases, so the level compression characteristics are based on quantization noise and distortion noise. The signal-to-noise ratio is determined by making a trade-off with the maximum signal-to-noise ratio. If the level compression characteristics are determined in this way, there is no need for the receiving side to have an expansion circuit that corresponds to the compression circuit on the transmitting side, and therefore there is no need to transmit information that indicates which compression circuit is being used on the transmitting side. do not have.

制御回路21は分離回路9からの分離信号のレ
ベルの発生分布が各フレームごとに第6図aに示
す分布40,41,42のうちいずれに属するか
判定して、第4図に示す圧縮回路20内のスイツ
チ回路14,17,18を開閉する制御信号R,
S,Uを発生する。まず分離信号は比較回路2
2,23へ送られる。比較回路22(あるいは2
3)は2個の電圧比較器と1個の論理和ゲートと
から成り、一方の電圧比較器は分離信号の電圧E
と第6図aに示すように定めた予測誤差の電圧B
(あるいはA)と比較してE<B(あるいかE<
A)のときだけハイレベルの信号H(以下Hと略
称する)を発生して論理和ゲートの一方の入力と
し、他方の電圧比較器は電圧Eと第6図aに示す
ように定めた予測誤差の電圧C(あるいはD)と
比較してE>C(あるいはE>D)のときだけH
を発生して論理和ゲートの他方の入力とする。論
理和ゲートはいずれか一方の入力がHであればH
を送出するから、比較回路22(あるいは23)
はE<BまたはE>C(あるいは、E<Aまたは
E>D)のときだけHを計数回路25(あるいは
26)へ送る。計数回路25(あるいは26)は
フレーム同期パルスごとにゼロにリセツトされ、
比較回路22(あるいは23)からHが送られて
いる間だけ符号化回路4から送られる標本化パル
スを計数して計数信号P(あるいはQ)を送出す
る。また計数回路24はフレーム同期パルスごと
にゼロにリセツトされ、符号化回路4からの標本
化パルスを計数して計数信号Nを送出する。な
お、1フレームにおける標本化パルスの個数が予
じめ定まつておれば、計数回路24は不要であ
る。読出し専用メモリ(以下ROMと略称する)
27は前記の計数信号N,P,Qの組合せをアド
レス信号(N,P,Q)として信号W,X,Yを
読み出して制御信号発生回路28へ送る。アドレ
ス信号(N,P,Q)と信号W,X,Yとの対応
関係は次のように決める。予測誤差の発生分布が
第6図aに示す分布40,41,42のうちいず
れに属するかをアドレス信号(N,P,Q)によ
つて判定するために比率α,βを予め決めてお
き、Q/N<αかつ(P−Q)/N<βなる条件
を満足すれば分布40に属し、Q/N<αかつ
(P−Q)/N≧βなる条件を満足すれば分布4
1に属しあるいはQ/N≧αなる条件を満足すれ
ば分布42を属していると判定する。標本化パル
スが制御回路21に入力するごとに送出される計
数信号N,P,Qは、前記の3つの判定条件のう
ちどれか1つだけを満足する。ROM27のアド
レス計号(N,P,Q)に対応する場所には、ア
ドレス信号(N,P,Q)が分布40に属する条
件を満足すれば信号W,X,Yとして1,0,0
を、分布41に属する条件を満足すれば信号W,
X,Yとして0,1,0をあるいは分布42に属
する条件を満足すれば信号W,X,Yとして0,
0,1をそれぞれ格納しておく。制御信号発生回
路28はROM27からの信号W,X,Yを標本
化パルスの周期Tだけ遅延させて送出する遅延器
と、フレーム同期パルスをセツト入力として該フ
レーム同期パルスの時刻において前記遅延器から
送られる信号を該フレーム同期パルスの時刻から
その次にくるフレーム同期パルスの時刻まで送出
し続けるフリツプフロツプとから構成される。す
なわち制御信号発生回路28は各フレームごとに
1つの前のフレームにおける予測誤差の発生分布
を計測して決定した制御信号を該各フレームの制
御信号R,S,Uとして送出する。前記スイツチ
回路14(あるいは17,18)はそのぞれ制御
信号R(あるいはS,U)が1すなわちハイレベ
ルであれば閉じ、制御信号R(あるいはS,U)
が0すなわちローレベルであれば開いて、分離信
号をそのレベルの発生分布に対応した圧縮回路に
通して加算回路13へ送る。なお本実施例におけ
る適応圧縮回路10,11はいずれも3種類のレ
ベル圧縮特性をそれぞれ具備するが、適応圧縮回
路10,11のいずれか一方が1種類のレベル圧
縮特性を具備し他方が複数の種類のレベル圧縮特
性を具備する構成や、両者がそれぞれ複数の種類
のレベル圧縮特性を具備する構成なども可能であ
ることは明らかである。
The control circuit 21 determines for each frame which of the distributions 40, 41, and 42 shown in FIG. 6a the generation distribution of the level of the separated signal from the separation circuit 9 belongs, and controls the compression circuit shown in FIG. control signal R for opening and closing switch circuits 14, 17, 18 in 20;
Generate S and U. First, the separated signal is sent to the comparator circuit 2.
Sent to 2,23. Comparison circuit 22 (or 2
3) consists of two voltage comparators and one OR gate, one of which is connected to the voltage E of the separated signal.
and the prediction error voltage B determined as shown in Figure 6a.
(or A) compared to E<B (or E<
A) A high level signal H (hereinafter abbreviated as H) is generated and input to one of the OR gates, and the other voltage comparator receives the voltage E and the prediction determined as shown in Figure 6a. H only when E>C (or E>D) compared to error voltage C (or D)
is generated and used as the other input of the OR gate. OR gate is H if either input is H.
Since the comparator circuit 22 (or 23)
sends H to the counting circuit 25 (or 26) only when E<B or E>C (or E<A or E>D). The counting circuit 25 (or 26) is reset to zero on every frame synchronization pulse,
Only while H is being sent from the comparator circuit 22 (or 23), the sampling pulses sent from the encoding circuit 4 are counted and a count signal P (or Q) is sent out. Further, the counting circuit 24 is reset to zero for each frame synchronization pulse, counts the sampling pulses from the encoding circuit 4, and sends out a counting signal N. Note that if the number of sampling pulses in one frame is determined in advance, the counting circuit 24 is not necessary. Read-only memory (hereinafter abbreviated as ROM)
27 uses the combination of the count signals N, P, and Q as address signals (N, P, Q) to read out signals W, X, and Y, and sends them to the control signal generation circuit 28. The correspondence between the address signals (N, P, Q) and the signals W, X, Y is determined as follows. The ratios α and β are determined in advance to determine which of the distributions 40, 41, and 42 the occurrence distribution of prediction errors belongs to, based on the address signals (N, P, Q) shown in FIG. , if the conditions Q/N<α and (P-Q)/N<β are satisfied, it belongs to distribution 40, and if the conditions Q/N<α and (P-Q)/N≧β are satisfied, it belongs to distribution 4.
1 or satisfies the condition Q/N≧α, it is determined that the distribution 42 belongs. The count signals N, P, and Q sent out each time a sampling pulse is input to the control circuit 21 satisfy only one of the three determination conditions described above. If the address signal (N, P, Q) satisfies the condition of belonging to the distribution 40, 1, 0, 0 is stored in the location corresponding to the address code (N, P, Q) of the ROM 27 as the signal W, X, Y.
If the condition belonging to the distribution 41 is satisfied, the signal W,
If X, Y are 0, 1, 0 or the conditions belonging to distribution 42 are satisfied, the signals W, X, Y are 0,
Store 0 and 1 respectively. The control signal generation circuit 28 includes a delay device that delays the signals W, X, and Y from the ROM 27 by the period T of the sampling pulse and sends them out, and a frame synchronization pulse as a set input, and outputs the signals from the delay device at the time of the frame synchronization pulse. It consists of a flip-flop that continues to send out a signal from the time of the frame synchronization pulse to the time of the next frame synchronization pulse. That is, the control signal generation circuit 28 measures the occurrence distribution of prediction errors in the previous frame for each frame and sends out the determined control signals as the control signals R, S, and U for each frame. The switch circuits 14 (or 17, 18) are closed when the control signal R (or S, U) is 1, that is, high level, and the switch circuit 14 (or 17, 18) is closed when the control signal R (or S, U)
is 0, that is, a low level, it is opened and the separated signal is sent to the adder circuit 13 through a compression circuit corresponding to the generation distribution of that level. Note that the adaptive compression circuits 10 and 11 in this embodiment each have three types of level compression characteristics, but one of the adaptive compression circuits 10 and 11 has one type of level compression characteristics, and the other has multiple types of level compression characteristics. It is obvious that a configuration in which the two types of level compression characteristics are provided, or a configuration in which both of them each have a plurality of types of level compression characteristics is also possible.

以上説明したごとくカラーテレビジヨン信号の
輝度信号成分と色度信号成分とを分離してそれぞ
れのレベル発生分布に適応する圧縮回路を通しさ
らに両者を加算して量子化を行なうことにより、
輝度信号ならびに色度信号のそれぞれについて予
測誤差の発生分布に適応した直接符号化を行なう
ことができ、従来の直接符号化方式の予測符号化
装置の規模を大幅に増やすことなく信号対雑音比
あるいは符号化効率を向上させることが可能とな
る。
As explained above, by separating the luminance signal component and chromaticity signal component of a color television signal, passing them through a compression circuit that adapts to the respective level generation distributions, and then adding the two to perform quantization,
It is possible to directly encode each of the luminance signal and chrominance signal in a way that adapts to the prediction error occurrence distribution, and it is possible to improve the signal-to-noise ratio or It becomes possible to improve encoding efficiency.

第5図は本発明の第二の実施例を示すブロツク
図である。同図において入力端子1からの入力信
号はアナログ、デイジタル変換回路31を通りデ
イジタル信号に変換され、さらに減算回路32へ
送られて予測回路30からの予測信号との差であ
る誤差信号となる。分離回路33は減算回路32
からの誤差信号のうち色度信号成分のみを通過さ
せる帯域通過形のデイジタルフイルタと、輝度信
号成分を通過させ色度信号成分を阻止する帯域阻
止形のデイジタルフイルタとから構成される。分
離回路33から送られる分離信号は適応圧縮回路
34,35において各分離信号の予測誤差の発生
分布に適応するレベル圧縮を受けて、加算回路3
6において加算されてふたたび色度信号と輝度信
号の両成分を合成した信号となる。適応圧縮回路
34,35は、第4図において電圧比較回路2
2,23をデイジタル形の比較回路に置きかえさ
らに圧縮回路15,16をデイジタル形の圧縮回
路に置きかえて構成される。デイジタル形の圧縮
回路はROMから成り、分離回路33からの分離
信号をアドレス信号として第6図bに示す圧縮特
性に対応する信号を読み出すことにより信号レベ
ルの圧縮を行なう。加算回路36から送られる信
号は量子化回路37において量子化されてDPCM
符号となり出力端子5から出力されるとともに、
予測回路30へ送られて加算器6において予測器
7から送られる予測信号を加算されて予測器7へ
送られる。予測器7から送出される予測信号は減
算回路32においてアナログ・デイジタル変換回
路31からの信号との差である誤差信号になる。
また同期入力端子12からはフレーム同期パルス
が入力して、第一の実施例と同様にして適応圧縮
回路34,35の動作を制御する。本実施例は第
一の実施例をデイジタル化した構成であり、LSI
化に好適で装置を小形にできるという利点があ
る。
FIG. 5 is a block diagram showing a second embodiment of the present invention. In the figure, an input signal from an input terminal 1 passes through an analog-to-digital conversion circuit 31, is converted into a digital signal, and is further sent to a subtraction circuit 32, where it becomes an error signal that is the difference from the prediction signal from a prediction circuit 30. Separation circuit 33 is subtraction circuit 32
It is composed of a band-pass type digital filter that passes only the chromaticity signal component of the error signal from the filter, and a band-elimination type digital filter that passes the luminance signal component and blocks the chromaticity signal component. The separated signals sent from the separating circuit 33 undergo level compression in adaptive compression circuits 34 and 35 that adapts to the occurrence distribution of prediction errors of each separated signal, and then are sent to the adding circuit 3.
6, the chromaticity signal and the luminance signal are added together to produce a signal that is a composite of both the chromaticity signal and the luminance signal. The adaptive compression circuits 34 and 35 are connected to the voltage comparator circuit 2 in FIG.
2 and 23 are replaced with digital comparison circuits, and compression circuits 15 and 16 are replaced with digital compression circuits. The digital compression circuit consists of a ROM, and compresses the signal level by using the separation signal from the separation circuit 33 as an address signal and reading out a signal corresponding to the compression characteristics shown in FIG. 6b. The signal sent from the adder circuit 36 is quantized in the quantizer circuit 37 and converted into DPCM.
It becomes a sign and is output from the output terminal 5, and
The signal is sent to the prediction circuit 30, where the adder 6 adds the prediction signal sent from the predictor 7, and the resultant signal is sent to the predictor 7. The prediction signal sent from the predictor 7 becomes an error signal, which is the difference between the prediction signal and the signal from the analog-to-digital conversion circuit 31, in the subtraction circuit 32.
Further, a frame synchronization pulse is input from the synchronization input terminal 12, and the operation of the adaptive compression circuits 34 and 35 is controlled in the same manner as in the first embodiment. This embodiment is a digitalized configuration of the first embodiment, and has an LSI
It has the advantage that it is suitable for industrial applications and the device can be made compact.

以上説明したように本発明には、複数の信号成
分を多重化した信号の各信号成分の予測誤差の発
生分布が時間とともに変化するときこれに適応し
ながら1個の予測符号化装置により直接符号化す
ることにより、従来の直接符号化方式の装置より
も信号対雑音比が高くかつ伝送速度が低い符号化
効率が良好な予測符号化装置を規模を大幅に増大
することなく構成できるという効果がある。
As explained above, the present invention enables direct coding by one predictive coding device while adapting to changes in the occurrence distribution of prediction errors of each signal component of a signal obtained by multiplexing a plurality of signal components over time. This has the effect of making it possible to construct a predictive coding device with a higher signal-to-noise ratio, lower transmission rate, and better coding efficiency than conventional direct coding devices without significantly increasing the scale. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の直接符号化方式の予測符号化装
置を示すブロツク図、第2図は第1図の中の量子
化回路4の部分の量子化特性を示す特性図、第3
図は本発明の第一の実施例を示すブロツク図、第
4図は第3図の中の適応圧縮回路10,11の部
分を示すブロツク図、第5図は本発明の第二の実
施例を示すブロツク図および第6図aならびにb
はそれぞれ第4図の回路の動作を説明するための
予測誤差の発生分布図ならびにレベル圧縮特性図
である。 図において、1……入力端子、2,32……減
算回路、3,30……予測回路、4,37……量
子化回路、5……出力端子、6……加算器、7…
…予測器、8……デイジタル・アナログ変換器、
9,33……分離回路、10,11,34,35
……適応圧縮回路、12……同期入力端子、1
3,36……加算回路、31……アナログ・デイ
ジタル変換回路。
FIG. 1 is a block diagram showing a conventional predictive coding device using a direct coding method, FIG. 2 is a characteristic diagram showing the quantization characteristics of the quantization circuit 4 in FIG. 1, and FIG.
FIG. 4 is a block diagram showing a first embodiment of the present invention, FIG. 4 is a block diagram showing the adaptive compression circuits 10 and 11 in FIG. 3, and FIG. 5 is a block diagram showing a second embodiment of the present invention. The block diagram and Figures 6a and b
4 are a prediction error occurrence distribution diagram and a level compression characteristic diagram, respectively, for explaining the operation of the circuit of FIG. 4. In the figure, 1... input terminal, 2, 32... subtraction circuit, 3, 30... prediction circuit, 4, 37... quantization circuit, 5... output terminal, 6... adder, 7...
...Predictor, 8...Digital-to-analog converter,
9, 33...separation circuit, 10, 11, 34, 35
...Adaptive compression circuit, 12...Synchronization input terminal, 1
3, 36...addition circuit, 31...analog-digital conversion circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の信号成分を含む入力信号と予測信号と
の差を表わす誤差信号を送出する減算回路と、前
記誤差信号に含まれる前記複数の信号成分と分離
して複数の分離信号を送出する分離回路と、1つ
の前記分離信号を受けて該分離信号のレベル発生
分布が予め設定した複数の分布のいずれに属する
かを判別し該判別結果に応答して所定の複数のレ
ベル圧縮特性のうちの1つを選択し該分離信号に
与える適応圧縮回路を少なくとも1つ有しており
複数の前記分離信号のうちの少なくとも1つにレ
ベル圧縮を施して送出するレベル圧縮部と、該レ
ベル圧縮回路が送出する複数の前記分離信号を加
算する加算回路と、前記加算回路が送出する信号
を量子化して出力する量子化回路と、前記予測信
号を前記量子化回路の出力信号より予測して送出
する予測回路とを含んで構成されることを特徴と
する予測符号化装置。
1. A subtraction circuit that sends out an error signal representing the difference between an input signal containing a plurality of signal components and a predicted signal, and a separation circuit that separates the plurality of signal components included in the error signal and sends out a plurality of separated signals. Then, upon receiving one of the separated signals, it is determined which of a plurality of predetermined distributions the level generation distribution of the separated signal belongs to, and in response to the determination result, one of the plurality of predetermined level compression characteristics is determined. a level compression section that has at least one adaptive compression circuit that selects one of the plurality of separated signals and applies it to the separated signal; a quantization circuit that quantizes and outputs the signal sent out by the addition circuit; and a prediction circuit that predicts the prediction signal from the output signal of the quantization circuit and sends it out. A predictive encoding device comprising:
JP18149680A 1980-12-22 1980-12-22 Forecasting encoder Granted JPS57104321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18149680A JPS57104321A (en) 1980-12-22 1980-12-22 Forecasting encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18149680A JPS57104321A (en) 1980-12-22 1980-12-22 Forecasting encoder

Publications (2)

Publication Number Publication Date
JPS57104321A JPS57104321A (en) 1982-06-29
JPS628055B2 true JPS628055B2 (en) 1987-02-20

Family

ID=16101768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18149680A Granted JPS57104321A (en) 1980-12-22 1980-12-22 Forecasting encoder

Country Status (1)

Country Link
JP (1) JPS57104321A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0650822B2 (en) * 1985-02-04 1994-06-29 日本電信電話株式会社 Encoder / decoder
JPH073955B2 (en) * 1986-11-17 1995-01-18 株式会社日立製作所 Encoder
JPS63151225A (en) * 1986-12-16 1988-06-23 Victor Co Of Japan Ltd Adaptive high efficiency coding system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5597780A (en) * 1979-01-29 1980-07-25 Canon Inc Signal processing system
JPS55135421A (en) * 1979-04-09 1980-10-22 Nippon Telegr & Teleph Corp <Ntt> Adaptive prediction coding system

Also Published As

Publication number Publication date
JPS57104321A (en) 1982-06-29

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