JPS628798B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument in which keys are functionally divided at arbitrary positions to facilitate performance.

When playing an electronic keyboard instrument, the right hand usually plays the melody and the left hand plays the accompaniment, or the melody in the right hand and the accompaniment in the left hand are often played with different rhythm patterns, and for beginners, it is difficult to play them. was difficult.

Therefore, consideration has been made for beginners, such as specifying a chord with one finger of the left hand, and the chord performance is output according to the rhythm pattern of the linked rhythm box, but this method does not have much variation. In addition, not only the inverted chords written on the score were not pronounced, but the bass notes were also fixed uniformly.

Additionally, it may be difficult for beginners to keep up with the constant tempo set by the rhythm box, so further improvements have been desired.

The present invention has been made in view of the above circumstances, and includes storing and setting either the accompaniment or the melody in advance, and during performance, using the keyboard at any position for manual performance and for reading out the stored information. To provide an electronic musical instrument that can be played easily and even difficult pieces can be played by dividing the functions into those for performance.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the electronic musical instrument main body in this embodiment, and 1 in the figure.
is a keyboard consisting of four octaves. The keyboard 1 is constructed so that its functions can be divided at arbitrary positions, as will become clear from the explanation that follows. 2a and 2b use keyboard 1 normally, but they also write the function division position, write the played information to either the first or second memory (described later), or read the written information. This is a switch that specifies whether or not to do so. Further, 3 is an external operation switch such as a power switch and a volume control, and 4 is a speaker.

Next, the circuit configuration of this embodiment will be explained with reference to FIG. The circuit configuration shown in Figure 2 is roughly divided into five blocks and a circuit that connects each of these blocks, each of which is composed of, for example, one LSI (large scale integrated circuit) or hybrid IC. has been done. That is, 1
0 is a key input section operated by each key of the keyboard 1; 20 is a musical tone generating section composed of a circuit for creating and outputting musical tones, a circuit for controlling key input, etc.;
30 are the first and second scale chords set in advance.
A memory section 40 consisting of memories 31, 32 and peripheral circuits includes a memory for storing division positions, and a control section 50 consisting of a circuit for controlling the memories 31, 32 is an amplifier.

Each of these blocks 10 to 50 and their connection circuits will be described in detail below.

As mentioned above, the musical tone generating section 20 is provided with a 4-bit note counter 21 and a 2-bit block counter 22 for scanning the keyboard 1 and detecting pressed keys, and the first stage of the note counter 21 has a scanning counter. A clock O/ _A is applied for this purpose. The note counter 21 sends the count contents to the note decoder 23, and the note decoder 23 receives the count value of the note counter 21 from 0 to
11'', the keys are output to 12 lines 23a to 23l corresponding to the 12 notes ``C to B'' at different timings, respectively, and keys having the same note name in each octave of the key input section 10 are scanned. Furthermore, an output is obtained on the line 23m of the note decoder 23 when the count value of the note counter 21 reaches "12", and this output is sent to the note counter 21 as a reset signal and to the block counter 22 as a counting clock. applied. The block counter 22 counts according to the counting clock, and its count output is sent to the block decoder 24.
will be sent to. The block decoder 24 outputs different timing signals to the lines 24a to 24d according to the count value "0 to 3" of the block counter 22, and the signals output to the lines 24a to 24d are processed by an AND gate as an octave detection signal. 25a to 25d, respectively. The outputs of the AND gates 25a to 25d are input via an OR gate 26 to a shift register 27 having a serial-to-parallel conversion function and having a capacity of 48 bits corresponding to the number of keys in the key input section 10. This shift register 27 has a unique bit position for each key in the key input unit 10 and stores information for the pressed key, and its parallel output is composed of 48 bits with the same capacity as the shift register 27. is applied to the buffer 28. Batsuhua 28
reads the output of the shift register 27 when all keys in the key input unit 10 have been scanned, and uses line 23m of the note decoder 23 and line 2 of the block decoder 24 as read signals.
The output of the AND gate 28a to which the signal outputted to 4d is applied is applied. The output of the buffer 28 is sent to a musical tone generating circuit 29 that generates musical tone signals, and the musical tone generating circuit 29 digitally generates various musical tones in accordance with the pitches of the manipulated keys. The musical tone signal digitally created by this musical tone creating circuit 29 is outputted via a digital-to-analog converter 29a provided in this musical sound creating circuit 29, and the converted analog signal is sent to an amplifier 50. The sound is amplified and produced by the speaker 4. The operational output of the externally operated switch 3 is applied to the musical tone generating circuit 29, and the musical tone generating circuit 29 generates a predetermined musical tone signal according to the output of the buffer 28 and the operational output of the externally operated switch 3. .

On the other hand, the key input section 10 has a structure in which a diode 12 and a switch 13 interlocked with each key of the keyboard 1 are provided at the intersection of the row line and the column line, as shown in detail by a circle 11. The 48 switches for 4 octaves are arranged in a matrix of 4 rows and 12 columns. That is, each column line of the key input section 10 corresponds to the lines 23a to 23 of the note decoder 23.
l, and on this column line are keys with the same note name but different octaves, and in the same row are keys ``C~
Keys corresponding to the 12 tones of "B." are connected, and key operation outputs can be obtained from the key input unit 10 to each line 10a to 10d at the timing of each note name.

Thus, the key operation signals outputted to lines 10a-10d are applied to AND gates 61a-61d, respectively, and the outputs of these AND gates 61a-61d are applied to AND gates 25a-25d, respectively. The opening and closing of the AND gates 61a to 61d are controlled by an output signal A output from a control section 40, which will be described later. That is, the AND gate 61a
~61d are lines 10a~10 of the key input section 10
This controls whether or not the key operation output outputted to d is inputted to the tone generation section 20.

Further, the key operation outputs outputted to the lines 10a to 10d are also inputted to the memory section 30, and the first
AND gate 3 in memory 31 and second memory 32
It is input via 1a to 31d and 32a to 32d. These AND gates 31a to 31d and 3
Opening control signals B and C are applied to 2a to 32d from a control circuit 40, which will be described later, and these control circuits 40
Outputs B and C from the memory 31 and 32 are further applied as read/write signals (R/W) to the memories 31 and 32, respectively. Note that the memory unit 30 includes memories 31 and 32.
The reason why two are provided is that the accompaniment or melody can be read out and written into one of the memories in advance depending on whether the accompaniment or melody is to be read out and played by key operation on the key input section 10. These memories 31 and 32 can be combined into one by simply adding some additional circuits.

Furthermore, signals G and F are input from the control circuit 40 to the first and second memories 31 and 32 for incrementing an address circuit provided in these memories and for instructing writing or reading. .

The memories 31 and 32 also have lines 23a to 23 from the note decoder 23 as pitch name identification signals.
The note code output to 1 and the block code output from AND gates 31a to 31d or 32a to 32d are written.

On the other hand, the control section 40 controls line 1 of the key input section 10.
The key operation outputs outputted to 0a to 10d, the clock O/ _A , and the outputs of switches 2a and 2b are input, and AND gates 31a to 31d, 32a to 32
control signal B, which performs opening/closing control for d and write/read instructions for the memories 31 and 32;
C, furthermore, increment signals G and F for the memories 31 and 32, opening/closing control signals E for the AND gates 31e to 31h, and the AND gates 32e to 32e.
32h, the details of which are shown in FIG. Note that the input/output terminals in the detailed diagram shown in FIG. 3 do not correspond in position to those shown in FIG. 1.

That is, in FIG. 3, 401 and 402 are the note counter 21 and block counter 2 shown in FIG.
Counter 40 is a counter that operates in synchronization with Counter 2.
A clock signal O/ _A similar to the clock signal input to the note counter 21 is applied to the first stage of the note counter 21. Then, when the counter 401 counts "12", the counter 401 counts "12".
The signal output to line 403 resets the counter 40.
It is applied as a counting clock of 2. The output of the counter 402 is input to a key-on detection circuit 404, which converts key operation signals output to lines 10a to 10d of the key input section 10 to AND gates 25a to 25a.
Similarly to 25d, the octave is selected and output, and the output is output via the OR gate 405. Therefore, the output of this OR gate 405 is input directly to AND gates 406 and 407, and to an AND gate 409 via an inverter 408. The AND gate 406 receives the output of the 48-bit capacity shift register 410 from the inverter 4.
The output of the shift register 410 is directly supplied to the AND gates 407 and 409 through 11. That is, these AND gates 406,4
07,409, when a new key operation is performed,
A "1" signal is output when the key operation is continued and when the key operation is stopped. The outputs of the AND gates 406 and 407 are connected to the shift register 410 via an OR gate 412.
given to. Further, the output of the AND gate 406 is applied to the AND gate 413 together with the output of the division instruction contact of the switch 2a, and the output of the AND gate 413 is used as a reading command to the memories 414 and 415 that store the contents of the counters 401 and 402. give as. That is, memories 414, 415
The note code and block code are calculated by reading the contents of the counters 401 and 402, which operate in synchronization with the note counter 21 and block counter 22, based on the position of the operated key when the switch 2a is in the division instruction position. The output is applied to the coincidence circuit 416 along with the outputs of the counters 401 and 402. Matching circuit 41
6 compares the information output from the counters 401 and 402 with the codes output from the memories 414 and 415, and applies the coincidence output to the set terminal S of the R-S flip-flop 417 when they match.
Reset terminal R of R-S flip-flop 417
When the count value of the counter 402 reaches "3", the output obtained on the line 418 and the output obtained on the line 403 are applied via an AND gate 419. The set side output Q of this R-S flip-flop 417 is applied to AND gates 420 and 421, and the outputs of the AND gates 406 and 409 are applied to these AND gates 420 and 421, respectively. The outputs of the AND gates 420 and 421 are connected to the set terminal S of the R-S flip-flop 422,
Applied to reset terminal R. In addition, the above R-S
The reset side output of flip-flop 417 is
It is applied to AND gates 423 and 424, and the outputs of the AND gates 406 and 409 are applied to these AND gates 423 and 424, respectively. The outputs of the AND gates 423 and 424 are applied to the set terminal S and reset terminal R of the R-S flip-flop 425.

Further, the set side output Q of the R-S flip-flop 417 is applied to an AND gate 426, and the reset side output is applied to an AND gate 427. The AND gate 426 is further supplied with the output of the contact of the switch 2a that instructs reading from the memories 31 and 32, and the output of the first contact of the switch 2b.
Contact output and switch 2b to instruct reading of
The output of the second contact is supplied. The outputs of the AND gates 426 and 427 are applied to an OR circuit 429 via an OR gate 428.

The or gate 429 further includes a switch 2a.
The output of the contact point specifying the normal performance of and the memory 3
The output of the contact specifying writing to 1 and 32 is supplied, and the output is sent to the AND gates 61a to 61d.
is given as opening/closing control signal A.

Furthermore, the outputs of the contacts that designate the writing of the switch 2a are given to AND gates 430 to 433, and the outputs of the contacts that designate the reading of the switch 2a are given to the AND gates 434, 435, 438, 43.
9. And the above AND gate 43
0,431 are the first and second switches of switch 2b, respectively.
A second contact is provided, and its output is a gate control signal of AND gates 31a to 31d and a read/write (R/W) control signal B of memory 31, a gate control signal of AND gates 32a to 32d, and a gate control signal of memory 32, respectively. It is supplied as a read/write (R/W) control signal C.

The AND gate 434 further includes the R-S
The set side output Q of the flip-flop 425 and
The output of the first contact of the switch 2b is given, and the output is given as the opening/closing control signal E of the AND gates 31e to 31h. Also, and gate 435
Further, the set side output Q of the flip-flop 422 and the output of the second contact of the switch 2b are applied, and the outputs are applied to the AND gates 32e to 32h.
is given as an opening/closing control signal D.

In addition, the AND gates 432 and 433 have
Further, the output of the AND gate 406 is applied in common, and the output of the first contact and the output of the second contact of the switch 2b are respectively applied. The output of this AND gate 432 is applied to an OR gate 436, and the output of the AND gate 433 is applied to an OR gate 437. And this or gate 43
6 further includes the output of the AND gate 406, the output of the read designation contact of the switch 2a, and the output of the switch 2a.
The output of the first contact of the terminal b and the output of an AND gate 438 to which the reset side output of the R-S flip-flop 417 is applied are supplied. The OR gate 437 further includes the output of the AND gate 406, the output of the readout designation contact of the switch 2a,
The output of the second contact of the switch 2b and the output of an AND gate 439 to which the set side output Q of the R-S flip-flop 417 is supplied are supplied. The output of this OR gate 436 is sent to an OR gate 437 as an increment signal G of the memory 31.
The outputs of are respectively supplied as the increment signal F of the memory 32.

Next, in the above configuration, for example, the lowest octave of the four octave keys, that is, C ₂ ~
A case will be described with reference to FIG. 4 in which the key _B2 is used for reading and playing, an accompaniment is stored in advance, and the accompaniment is read out by operating any of the keys _C2 to _B2 .

First, to indicate the separation position, the switch 2a is set to designate the division position, and the key "C ₃ " is operated in order to read out and use keys C ₂ to B ₂ for performance. Due to the operation of the _C3 key, an operation output is obtained on the line 10b of the key input section 10 at the timing "C", and is input to the key-on detection circuit 404 of the control section 40. The key-on detection circuit 404 outputs a "1" signal to a predetermined line of the OR circuit 405 based on the contents of the counter 402. As a result, the AND gate 406 outputs a "1" signal, and the output of the AND gate 413 becomes "1", so that the contents of the counters 401 and 402 are read into the memories 414 and 415. Therefore, the match circuit 416 always detects a match at the timing _C3 during key scanning, and the R-S flip-flop 4
17 into the set state.

Next, the accompaniment score is memorized in advance, and when playing,
Figure 4 shows a case in which reading accompaniment is performed by operating any of the keys C ₂ to _{B 2} , and a melody is played manually by operating the other keys, that is, keys C ₃ to _{B 5} . Refer to and explain.

That is, in order to memorize the sheet music, switch 2a
is designated as the write position, and the switch 2b is set to the first contact, so that the data is written to the first memory 31. Then, the accompaniment score shown in FIG. 4 is written by operating the keyboard 1. At this time, in the memory 31, the switch 2a is designated as the write position, and the switch 2b is set as the first contact, so a write signal is sent from the AND gate 430, and the AND gates 31a to 31d are opened. It has become a state of affairs. So, first, when you operate the key for the first note "G ₂ ", the operation output is output to line 10a at the note timing of "G",
The output of this line 10a is applied to the memory 31 via the AND gate 31a, and the output of the line 2
The note codes output to 3a to 23l are applied to the memory 31. At this time, the signal output to the line 10a is output from the OR gate 405 at a timing unique to "G ₂ ", and since there is no "1" in the bit position of "G ₂ " in the shift register 410, the signal is output from the AND gate 406 at a timing unique to "G 2 ". “1” output is obtained. Therefore, AND gate 432 satisfies its logical condition, and increment signal G is applied to memory 31 via OR gate 436 as a read command. As a result, the memory 31 reads and stores the note codes outputted to the lines 23a-23l and the block codes outputted from the AND gates 31a-31d. Note that the memory 31 (the same applies to 32) is connected to lines 23a to 32.
The note code output to 23l counts the number of times the "B" chord is output, and C ₂ ~
The chords entered while scanning all keys of B ₅ are stored as being to be sounded at the same time, but now only the chord of "G ₂ " is memorized. Then, when the keys "G ₃ , B ₃ " are operated next, "G ₃ , B ₃ " are stored as being to be sounded simultaneously by the same operation as described above. Following the accompaniment score shown in Figure 4, "G ₃ , B ₃ ", "D ₃ ", "G ₃ , B ₃ ", "G ₃ , B ₃ "...
..., the fourth memory is stored in the memory 31.
The accompaniment pattern shown in the figure is stored and set.

Next, a case will be described in which the accompaniment stored in this way is read out taking only its rhythm pattern into account, and the right hand plays the melody score shown in FIG. 4. In this case, the switch 2a is set to read designation as shown in FIG. Note that the switch 2b maintains the current state. With this setting and the key separation specification described above, at the key timing of C ₂ to B ₂ , R-S
The reset side output of the flip-flop 417 becomes "1", and the set side output Q becomes "1" at key timings _C3 to _B5 . Therefore, first, with your right hand,
When the first melody note "G ₄ " is played, the operation output is obtained on the line 10c of the key input section 10, and at this time, the set side output Q of the flip-flop 417 is "1" as described above. As a result, the logic condition of AND gate 426 is satisfied, and as a result, OR gate 429 sends open signal A of AND gates 61a to 61d. Therefore, the key operation output is applied to the AND gate 25c via the AND gate 61c. AND gate 25c has block decoder 2
Since the octave detection signal is applied from line 24c from line 24c, when this line 24c is selected, that is, when the count value of block counter 22 reaches ``2'', the operation signal of ``G ₄ '' is applied. is written into the shift register 27 via the AND gate 25c and the OR gate 26, and thereafter shifted sequentially. Thus, when an output is received from the AND gate 28a, that is, when all keys of the key input section 10 have been scanned, the signal input to the shift register 27 is read into the buffer 28, and the musical tone creation circuit 29 is transferred to the buffer 28. A musical tone with a pitch of "G ₄ " is created according to the data read in, and is sounded by the speaker 4.

Next, when the second melody note "B ₄ " is played, the tone creation circuit 29 generates "B ₄ " by the same operation as above.
A musical tone with a pitch corresponding to is created and sounded.

Then, to play the next melody note "D ₅ ", play the "D ₅ " key with your right hand and C ₂ ~ with your left hand.
Play any key on B ₂ . As a result, the pronunciation of "D ₅ " played with the right hand is the same as above, but when a predetermined key from C ₂ to _{B 2} is operated, at that timing, the R-S flip-flop 41
7 is in the reset state. Therefore, the logical condition of the AND gate 423 is satisfied, the R-S flip-flop 425 is set in the set state, and its output is passed through the AND gate 434 to the AND gate 31e.
The opening signal E is sent from ~31h.

At the same time, the logical condition of AND gate 432 is satisfied and an increment signal G is sent to memory 31. In response to this instruction, the first memory 31 compares the note code output to the lines 23a to 23l of the note decoder 23 with the note code stored and set in advance, and when a match is detected, the first memory 31 changes the note code to the previously written block code. Output to the following line. In this case, the first memorized pitch is "G ₂ ", so lines 23a~
When the note code "G" is output to 23l, an output is obtained from memory 31, and AND gate 2
5a. Therefore, the musical tone generating circuit 29 simultaneously generates two tones "G ₂ " and "D ₅ " and outputs them through the speaker 4. Then, when the left-hand key operation is stopped, a "1" signal is output from the AND gate 409 at that timing, and at the same time,
Since the reset side output of R-S flip-flop 417 is "1", a reset signal is sent to R-S flip-flop 425 via AND gate 424. Therefore, the set side output Q becomes "0", and the AND gate 31e
The opening/closing control signal E from 31h to 31h becomes "0", and the sounding of the musical tone "G ₂ " is stopped.

Hereinafter, by playing the melody shown in the melody notation in FIG. 4 with the right hand and any key from C ₂ to _{B 2} with the left hand in the rhythm pattern shown in the rhythm notation in FIG. Musical tones with pitches corresponding to the musical score shown in FIG. 4 are created and sounded through the speaker 4.

In the above embodiment, the switch 2b is set as the first contact to write and read the accompaniment score, but it is also possible to set the switch 2b as the second contact to write and read the melody. In this case, the accompaniment can be performed with the left hand by using the keys at the separately designated pitches from the functionally divided key group, that is, the pitch _C2 . The operation in this case is substantially the same as the circuit operation described above except that the functional circuit group is different, so a detailed explanation will be omitted.

Further, in the above embodiment, the division position is set to pitch _C3 , but it goes without saying that the division position can be specified at any pitch in the same manner as above.

As explained in detail above, the electronic musical instrument according to the present invention stores either accompaniment or melody in advance, and when reading the accompaniment or melody, selects one of the keys in the function-divided key group at any position on the keyboard to play the accompaniment. Or, by playing according to the rhythm pattern of the melody, you can play difficult songs with simple operations, which is effective for beginners.
Further, since the functional division of the keyboard can be designated at any position, there are various advantages such as the ability to change the range of pitches that can be performed manually in addition to reading performance.

[Brief explanation of the drawing]

The accompanying drawings show an embodiment of the present invention, in which FIG. 1 is an external perspective view of the main body of an electronic musical instrument, FIG. 2 is a circuit block diagram, and FIG. 3 is a detailed view of the control section of FIG. 2.
FIG. 4 is a diagram for explaining the operations of FIGS. 2 and 3. 1...Keyboard, 2a, 2b...Switch, 20...
. . . Musical sound generation section, 30 . . . Memory section, 40 . . . Control section, 414, 415 . . . Memory, 416 . . .

Claims (1)

[Claims] 1 A keyboard, a setting means for setting manual performance, memorized performance, set for memorized performance, and division position designation for memorized performance based on the operational output of the keyboard, and a setting means for specifying division positions for memorized performance by the setting means. a division position storage means for storing division positions by operating the keyboard when specified settings are made; and a melody or accompaniment input by operating the keyboard when the set for memorized performance is set by the setting means. a storage section for storing the pitch code; and one or more keys of either one of the keyboards divided by the division position storage means when the setting means sets the memorized performance, in the storage section. An electronic musical instrument comprising means for setting a function as a reading instruction key for a pitch code.