JPS628936B2 - - Google Patents
Info
- Publication number
- JPS628936B2 JPS628936B2 JP54059119A JP5911979A JPS628936B2 JP S628936 B2 JPS628936 B2 JP S628936B2 JP 54059119 A JP54059119 A JP 54059119A JP 5911979 A JP5911979 A JP 5911979A JP S628936 B2 JPS628936 B2 JP S628936B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- thick film
- electrode
- substrate
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、厚膜基板に搭載するチツプの接合法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for bonding chips mounted on a thick film substrate.
チツプの接合方法にはチツプの取り付ける構造
的見地から、(a)活性面(電極接合面)を上側にし
て基板に取り付けるバツク接合法(フエースアツ
プボンデイング)、(b)活性面を下(基板側)にし
て取り付けるフリツプチツプ接合法(フエースダ
ウンボンデイング)、(c)上記(a)、(b)を接合過程に
含んだデカル接合法がある。従来、ソルダーブル
な電極を両側にもつチツプを基板に取り付ける場
合、上側電極の接合に対して特殊なコンタクト
(リード電極)を使用し、チツプの両側電極を熱
圧着方式により同時にはんだ接合する特殊なデカ
ル接合法がとられている。この場合、コンタクト
を使用するためチツプ電極との位置合せに対し高
精度が要求され、チツプ、コンタクトの位置決め
用の治具が必要である。さらに厚膜基板上に他の
素子と共に取り付ける場合、厚膜プロセスが複雑
になる欠点を有する。 From the structural standpoint of attaching the chip, there are two ways to bond the chip: (a) back bonding (face-up bonding) where the chip is attached to the substrate with the active surface (electrode bonding surface) facing up; (b) back bonding (face-up bonding) where the chip is attached with the active surface facing down (substrate ), and (c) the decal bonding method, which includes the above (a) and (b) in the bonding process. Conventionally, when attaching a chip with solderable electrodes on both sides to a board, a special contact (lead electrode) was used to connect the upper electrode, and a special decal was used to simultaneously solder the electrodes on both sides of the chip using a thermocompression method. A bonding method is used. In this case, since contacts are used, high precision is required for alignment with the chip electrodes, and a jig for positioning the chip and contacts is required. Furthermore, when mounting together with other elements on a thick film substrate, the thick film process becomes complicated.
本発明の目的は、厚膜基板上の導体電極とチツ
プの上側電極をはんだでブリツジさせて接合する
ことにより、上記した従来技術の欠点をなくし、
従来使用していたチツプ、コンタクトの位置決め
用冶具および特殊なコンタクトを不要にし、かつ
はんだ接合のための特殊な厚膜プロセスも不要に
することにある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art by bonding the conductor electrode on the thick film substrate and the upper electrode of the chip with solder.
The purpose is to eliminate the need for chips, contact positioning jigs, and special contacts that have been used in the past, as well as the need for a special thick film process for solder bonding.
本発明は両側にソルダーブルな電極を有するチ
ツプを厚膜基板に取り付ける場合、従来使用して
きた特殊なコンタクトや冶具を不要にし、さらに
は、厚膜プロセスを簡単にするため、チツプの上
側電極と厚膜基板上の導体電極を、厚膜基板全体
のリフロー時に、はんだペーストのはんだでブリ
ツジさせて接合することを特徴とする。 When a chip with solderable electrodes on both sides is attached to a thick film substrate, the present invention eliminates the need for special contacts and jigs that have been used in the past, and further simplifies the thick film process. The conductor electrodes on the film substrate are bonded by bridging with solder paste during reflow of the entire thick film substrate.
以下、図において本発明の実施例を説明する。
第1図は、厚膜基板上に、トライアツクチツプ5
を搭載した場合で、アルミナ基板2上に、まず
Ag−Pd導体電極1を印刷形成し、その上にガラ
ス絶縁層3を印刷形成し、さらにその上にはんだ
ペースト4を印刷して、最後にトライアツクチツ
プ5の上側電極6−1,6−2をアルミナ基板2
と反対側に向けて搭載してある。 Hereinafter, embodiments of the present invention will be explained with reference to the figures.
FIG. 1 shows a triax chip 5 mounted on a thick film substrate.
is mounted on the alumina substrate 2, first
An Ag-Pd conductor electrode 1 is printed, a glass insulating layer 3 is printed on it, a solder paste 4 is printed on it, and finally the upper electrodes 6-1, 6- of the tri-chip 5 are formed. 2 to alumina substrate 2
It is mounted facing the opposite side.
第2図は、第1図におけるトライアツクチツプ
5を搭載した厚膜基板をリフローし、加熱するこ
とにより、はんだペースト4中のはんだが凝集
し、はんだブリツジを起こした状態を示す一実施
例を表わし、トライアツクチツプ5の上側電極6
−1,6−2とAg−Pd導体電極1がブリツジし
たはんだ8−1,8−2で、はんだ接合されてい
る。 FIG. 2 shows an example in which the thick film substrate on which the triax chip 5 shown in FIG. upper electrode 6 of the triax chip 5
-1, 6-2 and Ag--Pd conductor electrode 1 are soldered together with bridged solder 8-1, 8-2.
第3図a,bはアルミナ基板2上にAg−Pd導
体電極1を、第2図のトライアツクチツプ5の上
側電極6−1,6−2とAg−Pd導体電極1間に
はんだブリツジが起こるように印刷形成したパタ
ーン形状を示す。第4図a,bは、Ag−Pd導体
電極1が印刷形成された工程までのアルミナ基板
2上に、Ag−Pd導体電極1間で短絡しないよう
に、ガラス絶縁層3を印刷形成したパターン形状
を示す。第5図a,bは、ガラス絶縁層3が印刷
形成された工程までアルミナ基板2上に、トライ
アツクチツプ5の上側電極6−1,6−2とAg
−Pd導体電極1間ではんだブリツジを起こし、
かつそれに必要なはんだ量を確保できるように印
刷したパターン形状を示す。第6図a,b,cは
トライアツクチツプ5の上側電極6−1,6−2
と下側電極7の形状を示す。 Figures 3a and 3b show an Ag-Pd conductor electrode 1 on an alumina substrate 2, and a solder bridge between the upper electrodes 6-1, 6-2 of the triax chip 5 in Figure 2 and the Ag-Pd conductor electrode 1. The pattern shape printed as it occurs is shown. Figures 4a and 4b show a pattern in which a glass insulating layer 3 was printed on the alumina substrate 2 up to the step where the Ag-Pd conductor electrodes 1 were printed to prevent short circuits between the Ag-Pd conductor electrodes 1. Show shape. 5a and 5b show that the upper electrodes 6-1, 6-2 of the triax chip 5 and the Ag
- Solder bridging occurs between Pd conductor electrode 1,
It also shows the pattern shape printed to ensure the necessary amount of solder. 6a, b, and c are the upper electrodes 6-1, 6-2 of the triax chip 5.
and shows the shape of the lower electrode 7.
以上、述べたように、本発明によれば次の点に
大きな効果がある。 As described above, the present invention has the following significant effects.
() 特殊コンタクトが不要である。() No special contacts are required.
チツプの上側電極とのはんだ接合において、
従来は、特殊コンタクトを使用してきたが、本
発明により、これを不要とした。 In the solder joint with the upper electrode of the chip,
Conventionally, special contacts have been used, but the present invention has made these unnecessary.
() チツプ、特殊コンタクトの位置決め冶具が
不要である。従来、チツプの上側電極に特殊コ
ンタクトをはんだ接合する場合、高精度な位置
決め用冶具が使用されてきたが、本発明によ
り、これを不要とした。() No positioning jig for chips or special contacts is required. Conventionally, when a special contact is soldered to the upper electrode of a chip, a highly accurate positioning jig has been used, but the present invention has made this unnecessary.
() はんだ接合のための特殊な厚膜プロセスが
不要である。従来厚膜基板上に、他の素子と共
にチツプを取り付ける場合、はんだ接合時に特
殊なプロセスが必要となり、厚膜プロセスが複
雑になるという欠点を有したが、本発明によ
り、厚膜基板上の他の素子と同時にチツプを取
り付けることができ、チツプのはんだ接合のた
めの特殊な厚膜プロセスを不要とした。() No special thick film process is required for solder joints. Conventionally, when a chip is attached to a thick film substrate together with other elements, a special process is required for soldering and the thick film process becomes complicated. The chip can be attached at the same time as the device, eliminating the need for a special thick-film process for soldering the chip.
以上から、本発明により、チツプを厚膜基板に
取り付ける場合の作業効率が大幅に向上すると共
に実装プロセスの自動化が安易になりさらには、
厚膜基板としての大幅な原価低減につながる。 From the above, the present invention greatly improves work efficiency when attaching chips to thick film substrates, and facilitates automation of the mounting process.
This leads to a significant cost reduction as a thick film substrate.
第1図は、リフロー前のトライアツクチツプを
搭載した厚膜基板の断面図、第2図は、リフロー
後のトライアツクチツプを搭載した厚膜基板の断
面図、第3図aは、厚膜基板上のAg−Pd導体電
極パターン形状を示す平面図、第3図bは、第3
図aのA−A線断面図、第4図aは、厚膜基板上
のガラス絶縁層のパターン形状を示す平面図、第
4図bは、第4図aのB−B線断面図、第5図a
は、厚膜基板上のはんだペーストのパターン形状
を示す平面図、第5図bは、第5図aのC−C線
断面図、第6図a,cはトライアツクチツプの上
側、下側電極を示す平面図、第6図bは第6図a
のD−D線断面図である。
1……Ag−Pd導体電極、5……トライアツク
チツプ、6……上側電極、7……下側電極、8−
1,8−2……ブリツジしたはんだ。
FIG. 1 is a cross-sectional view of a thick film substrate on which a triax chip is mounted before reflow, FIG. 2 is a cross-sectional view of a thick film substrate on which a triax chip is mounted after reflow, and FIG. Figure 3b is a plan view showing the shape of the Ag-Pd conductor electrode pattern on the substrate.
4a is a plan view showing the pattern shape of the glass insulating layer on the thick film substrate; FIG. 4b is a sectional view taken along the line B-B in FIG. 4a; Figure 5a
is a plan view showing the pattern shape of the solder paste on the thick film substrate, FIG. 5b is a sectional view taken along the line C-C of FIG. 5a, and FIGS. A plan view showing the electrode, Fig. 6b is similar to Fig. 6a.
It is a sectional view taken along the line DD. DESCRIPTION OF SYMBOLS 1...Ag-Pd conductor electrode, 5...Triac chip, 6...Upper electrode, 7...Lower electrode, 8-
1,8-2... Brisked solder.
Claims (1)
に、ソルダーブルな電極を上下両面に有するチツ
プを取り付ける接合法であつて、上記チツプの下
側電極と基板の導体電極とを対向接合するととも
に、上記チツプの上側電極と基板の導体電極をは
んだでブリツジさせて接合することを特徴とする
チツプのはんだ接合法。1 A bonding method in which a chip having solderable electrodes on both upper and lower surfaces is attached to a plurality of conductor electrodes printed on a substrate, in which the lower electrode of the chip and the conductor electrode of the substrate are bonded facing each other, A method for soldering chips, characterized in that the upper electrode of the chip and the conductor electrode of the substrate are joined by bridging with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5911979A JPS55151345A (en) | 1979-05-16 | 1979-05-16 | Soldering method of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5911979A JPS55151345A (en) | 1979-05-16 | 1979-05-16 | Soldering method of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55151345A JPS55151345A (en) | 1980-11-25 |
| JPS628936B2 true JPS628936B2 (en) | 1987-02-25 |
Family
ID=13104097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5911979A Granted JPS55151345A (en) | 1979-05-16 | 1979-05-16 | Soldering method of chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55151345A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5276379U (en) * | 1975-12-05 | 1977-06-07 | ||
| JPS5324254U (en) * | 1976-08-09 | 1978-03-01 |
-
1979
- 1979-05-16 JP JP5911979A patent/JPS55151345A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55151345A (en) | 1980-11-25 |
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