JPS629212B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a so-called SOI (Silicon on Insulator) structure in which a semiconductor layer is formed on a dielectric substrate.

Grooves are formed on the surface of a dielectric (insulating) substrate such as silicon dioxide (SiO ₂ ) or quartz glass, a polycrystalline silicon or amorphous silicon layer is deposited on the surface of the substrate, and the layer is laser annealed to form the grooves. as the core
It is known that a single crystal with a quality equal to or better than the SOS (Silicon on Sapphire) structure can be grown. FIG. 1A shows an example of this, in which 1 is a dielectric substrate, 2 is a groove formed on its surface to a depth of about 1000 to 2000 Å, and 3 is a silicon layer about 5000 Å thick. The silicon layer 3 is made by growing polycrystalline silicon by, for example, chemical vapor deposition (CVD) and melting it by laser annealing, and when it solidifies, the groove 2 becomes a nucleus and becomes a single crystal. .
Therefore, the silicon layer 3 has, for example, similar to SOS.
Elements such as MOS transistors can be formed. 1st
In FIG. b, a MOS transistor is formed by performing source S and drain D diffusion in the flat part 3a of the silicon layer 3, where 4 is a gate oxide film and 5 is a gate electrode.

By the way, if the formation region of the element is, for example, the upper part of the groove 2 as shown in FIG. The elements differ in crystallinity, silicon film thickness, etc., and the element becomes as shown in the figure and does not have the same characteristics as the element shown in Figure b. For example, one of the advantages of the SOS structure is that the lower portions of the source and drain are insulators, so the junction capacitance is negligibly small, and this can be expected in the structure shown in Figure 1b. In the structure shown in c, the junction capacitance of the source region S cannot be ignored. Of course, the groove 2 is used as a nucleus during single crystallization, but it is not preferable that the presence of the groove 2 causes the characteristics of many elements within one chip to become uneven.

The present invention has been made in view of the above points, and involves forming grooves in advance on the surface of a dielectric substrate along scribe lines, then forming a non-single-crystal semiconductor layer on the surface of the substrate, and further layering the semiconductor layer with laser or light beams. Alternatively, the method is characterized in that it is annealed with an energy beam such as an electron beam to form a single crystal, and then a desired semiconductor element is formed in a portion of the single crystallized semiconductor layer excluding the upper layer portion of the groove, This will be explained in detail below with reference to the illustrated embodiments.

FIG. 2 is a plan view of a main part showing an embodiment of the present invention, in which 1 shows a large number of chips (element pieces including at least one active element and/or passive element) along a scribe line 6. This is a large diameter dielectric substrate that is divided into parts. In the present invention, grooves 2 are provided vertically and horizontally on the surface of the dielectric substrate 1 along the scribe line 6. The method for forming the device is the same as the conventional method shown in FIGS. (better) layer 3 by CVD method
Grow to about 5000 Å. FIG. 3 shows a cross section (cross section AA in FIG. 2) after the non-single crystal semiconductor layer 3 is formed. Next, laser annealing is performed to convert the non-single crystal semiconductor layer into a single crystal layer using the grooves 2 as nuclei. If the groove 2 in Fig. 2 is formed with a diamond blade, for example, its width will be about 10 to 100 μm,
Also, the distance between grooves 2 depends on the chip size, but
It becomes an order. The depth is 1000 to 2000 as in Figure 1.
Å, or approximately half the thickness of the substrate 1 in order to facilitate the cutting operation during scribing.

For laser irradiation of the non-single crystal silicon layer formed on the substrate 1, there are two methods: (1) covering the entire chip region 7 surrounded by the groove 2 with a laser spot with a large beam diameter, and (2) using a laser beam with a small diameter. There are methods such as scanning the area 7. In either case, as shown by the solid arrow in the figure, single crystallization progresses from the groove 2 toward the center, and for example, a single crystal of crystal plane 100 grows. Thereafter, MOS transistors and the like are formed in the same manner as in FIG. 1b, etc., but the area is limited to the chip region 7 (corresponding to the flat part 3a in FIG. 1), and at least the upper part of the groove 2 is not used. . After the device is formed, it is cut along the scribe line 6 to obtain a semiconductor device chip having seven chip regions. Note that the annealing of the non-single-crystal silicon layer is not limited to laser light, and may be performed using focused strong light such as arc light, electron beam, or the like.

According to the method for manufacturing a semiconductor device of the present invention described above, by aligning the grooves that serve as the core of the single crystal with the scribe lines, the chip area for forming elements becomes flat and uniform, so that many This has the advantage that the characteristics between the elements can be made uniform, making the SOI structure more practical.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device in which a groove is provided in a dielectric substrate, and FIGS. 2 and 3 are plan views showing an embodiment of the present invention. In the figure, 1 is a dielectric substrate, 2 is a groove, 3 is a silicon layer, 6 is a scribe line, and 7 is a chip region.

Claims (1)

[Claims] 1. Grooves are previously formed on the surface of a dielectric substrate along scribe lines, then a non-single crystal semiconductor layer is formed on the surface of the substrate, and the semiconductor layer is further annealed with an energy beam such as a laser, a light beam, or an electron beam to form a single crystal. A method for manufacturing a semiconductor device, comprising: crystallizing the single crystallized semiconductor layer, and then forming a desired semiconductor element in a portion of the single crystallized semiconductor layer excluding the upper layer portion of the groove.