JPS6298052U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram of a PLL circuit that is one embodiment of the present invention, Figure 2 is a PLL circuit that is another embodiment of the present invention, and Figures 3 and 4 are R-DAT.
An explanatory diagram of the device, FIG. 5 is a block diagram of a conventional PLL circuit. 11a... PLL circuit, 11b... demodulation section, P
DC...Phase comparator, CLG...Regenerated clock generator, LPF...Low pass filter, SW...Switch unit.

Claims (1)

[Claims for Utility Model Registration] In a PLL circuit in a digital audio tape device that reproduces a clock signal included in a reproduced signal read from a magnetic tape and reads the reproduced signal in synchronization with the reproduced clock signal, A low-pass filter is provided between a phase comparator that generates a voltage signal according to a phase difference with the recovered clock signal, and a recovered clock generator that generates the recovered clock signal based on the voltage value of the voltage signal. A switch section is provided to bypass the phase comparator, and during playback, the output of the phase comparator is input to the recovered clock generation section via a low-pass filter, and during search, the output of the phase comparator is inputted to the recovered clock generation section without passing through the low-pass filter. A PLL circuit characterized by: