JPS629940B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer emulator that is capable of independently executing individual instructions of a microprocessor, including non-disableable interrupts, and monitoring the status thereof.

Generally, when checking the completeness of the functions of the software of a microcomputer system, it is necessary to use special software prepared for this system to execute individual instructions of the microprocessor and monitor its status. It will be done. Microcomputer emulators are used for this type of processing, and various systems have been proposed in the past.

However, in microcomputer systems, many microprocessors include interrupts that cannot be inhibited, and it has been extremely difficult to emulate such microprocessors. For example, problems such as execution of an interrupt that cannot be inhibited may cause the program to be unable to return from its jump destination, or a HALT instruction may cause system operation to stop, are likely to occur. In particular, when the microprocessor includes interrupts and their execution processes that cannot be inhibited by hardware, it becomes extremely difficult to control them. For this reason, it has been difficult to cause the program to correctly follow requests for interrupts that cannot be inhibited.

The present invention has been made in consideration of these circumstances, and its purpose is to correctly follow and handle interrupt processing that cannot be inhibited by hardware or the like. An object of the present invention is to provide a highly practical microcomputer emulator that can grasp the status.

That is, instead of the conventional method of executing the target instructions individually, the present invention executes the target instruction and the no-operation instruction inserted thereafter as a pair. It is an object of the present invention to provide a microcomputer emulator using a hardware method that effectively achieves the above-mentioned object by generating a non-disableable interrupt only during the execution cycle of an instruction.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an emulator according to an embodiment, and FIG. 2 is a timing chart showing its operation timing. Microprocessor 1 is
It operates according to a program input from the control storage device 2 or the execution instruction storage device 3 via the data bus 4. These storage devices 2 and 3 each store a target instruction program or an interrupt processing program, and the programs read from these storage devices 2 and 3 according to a predetermined sequence are sent to the bus cutoff circuit 5. , 6, and then read into the microprocessor 1 via the bus 4. On the other hand, a machine cycle counter 7 counts machine cycles of the microprocessor 1, and a bus switching flip-flop 8 is driven by this output.
That is, the flip-flop 8 is set after a predetermined machine cycle has elapsed. Once the counter 7 sets the flip-flop 8, it will no longer count machine cycles. This flip-flop 8 selectively energizes the storage devices 2 and 3, that is, controls the switching so that they are selectively operated.The output of the flip-flop 8 is appropriately inverted, and the gate circuits 9a,
9b and the bus cutoff circuits 5 and 6, respectively. The gate circuits 9a and 9b perform mutually inverted operations to selectively open the gates, and guide control signals issued from the microprocessor 1 to the storage devices 2 and 3, respectively. In response to this control signal, instruction programs and interrupt programs are read from the storage devices 2 and 3, and input to the microprocessor 1 via the bus 4 for execution.

By the way, the processor status detection circuit 1 operates by inputting a clock indicating a machine cycle.
0 monitors the status mode of the microprocessor 1, determines the execution cycle of instructions, etc., and issues various control signals. An interrupt permission signal that is one of the control signals, that is, a signal indicating the interrupt permission period for the target instruction, is sent to the interrupt signal selection circuit 12 via the gate circuit 11 gate-controlled by the output of the flip-flop 8. giving. This gate circuit 11
The interruption of all interrupt request signals is controlled by the signal given through the signal, and for example, only during the period of logic "1", the microprocessor 1 can interrupt the target execution program, including interrupts that cannot be inhibited. It will be released. Under such control, the selection circuit 12 receives a non-prohibitable interrupt request signal issued by the status detection circuit 10 and an input from predetermined hardware etc. when executing an instruction in the storage device 3. The microprocessor 1 is selectively input with an interrupt request signal to be sent to the microprocessor 1. That is, the selection circuit 12 receives a predetermined interrupt request signal and issues an interrupt request signal to the microprocessor 1. Further, the processor status detection circuit 10 detects the status mode of the microprocessor 1 and outputs the gate circuit 1.
3 and 14, respectively. This control signal is issued during the machine cycle period when the next instruction code is read after executing the instruction stored in the storage device 3, and this signal triggers the gate circuit 13 which inputs the machine cycle clock. is applied to the flip-flop 8 via the flip-flop 8, thereby resetting the flip-flop 8.

The signal generated via the gate circuit 14 is input to the NOP instruction storage device 15, whereby a no-operation instruction is forcibly output from the storage device 15 to the bus 4. This no-operation instruction is inserted after the execution of the target instruction, and is processed as a pair with the same instruction. In addition, the storage device 3 surrounded by a broken line in the figure
and its peripheral circuits (bus cutoff circuit 6 and gate circuit 10), along with an external interrupt request signal,
It is provided for the target program to be emulated.

Now, in a system configured in this way, the storage device 3 stores instructions to be executed, and the storage device 2 stores all the sequences up to the execution of the target instructions and the control program. Contains instructions for instructing the processing sequence after returning. The microprocessor 1 performs its intended function by selectively executing instructions supplied from these storage devices 2 and 3.

That is, the microprocessor 1 performs the execution on the storage device 2 at its initial stage. On the other hand, when executing one instruction stored in the storage device 3, the processor 1 first sends a signal to the counter 7, and then, after a predetermined machine cycle has elapsed, causes the flip-flop 8 to output a signal. Set flip-flop 8. By setting the flip-flop 8, the storage device 3 instead of the storage device 2 becomes the target of execution.
This allows the microprocessor 1 to access the storage device 3.
The instruction program will be executed in one step. Thereafter, when the microprocessor 1 obtains the next instruction program from the storage device 3 and is about to execute it, the microprocessor 1
The status detection circuit 10 is activated by detecting the status mode, whereby an interrupt permission period control signal is issued via the gate circuit 11 and interrupts to the execution of the storage device 3 are prohibited. At the same time, the bus cutoff circuit 6 is activated, and whatever instruction code is read from the storage device 3, its output to the data bus 4 is blocked. Then, instead of this, a no-operation instruction is read out from the NOP instruction storage device 15 onto the data bus 4, and the microprocessor 1 executes this no-operation instruction. That is, the microprocessor 1 uses the 1 stored in the storage device 3.
Every time one instruction program is executed, the next no-operation instruction is executed unconditionally. Note that the no-operation instruction read from the storage device 15 may be one that equivalently performs a no-operation function for the processor 1. Therefore, within this range, any instruction that the microprocessor 1 has You may also use instructions like this.

However, at a slight delay from the start of execution of the no-operation instruction, the interrupt signal selection circuit 12 receives a signal from the status detection circuit 10.
A non-forbidden interrupt request is issued to the microprocessor 1 via the microprocessor 1. This non-prohibitable interrupt request causes execution of the instructions stored in the storage device 3 to return to the control program in the storage device 2. Then, due to the generation of this non-prohibitable interrupt request, the flip-flop 8
is reset, and from now on the storage device 2 becomes the instruction source that the processor 1 executes. Then, by a non-prohibitable interrupt occurring during the execution cycle of the no-operation instruction read from the storage device 15, the original control program is returned to. Thereafter, this process is repeated in sequence, and the target instructions stored in the storage device 3 are executed one step at a time.

Incidentally, an interrupt issued during an execution cycle of the storage device 3 is inputted to the processor 1 by the selection circuit 12, and the process proceeds to an interrupt response cycle. Therefore, the status detection circuit 10 does not determine that this is the next instruction execution cycle, and the gate control signal is not output until the next execution cycle after the interrupt response cycle. As a result, the no-operation instruction is unconditionally inserted into the first instruction of the interrupt processing routine. In this case, since the control programs of the storage device 2 are completely independent, there is no need to take any special measures.

Thus, by forcibly inserting a no-operation instruction each time a target instruction is executed, and generating a non-prohibitable interrupt during the execution cycle of this no-operation instruction to return to the control program, Regardless of the type of interrupt generated by the execution instruction storage device 3, emulation can be executed by a nearly perfect single step operation. Therefore, the problem of complicated and difficult control as in conventional systems does not occur.

Next, the above emulation operation will be summarized based on the timing shown in FIG. In FIG. 2, a is a clock signal for convenience indicating the execution unit of instructions of the microprocessor 1, and the basic unit is indicated by A. Here, an example of an instruction that requires two units B to execute is illustrated. In FIG. 2, b indicates an interrupt request signal that cannot be inhibited, and c indicates an interrupt cutoff signal that blocks all interrupts. This signal is opened to the target execution program by logic "1". Further, d connects the storage device 3 storing the target instruction program and the storage device 2 storing the control program to the microprocessor 1.
e is a signal for selectively controlling switching between the microprocessor 1 and the memory devices 2 and 3 of the microprocessor 1. Further, f is a signal for forcibly outputting a no-operation command onto the data bus 4 in response to the read signal shown in e above.

However, now, when the execution cycle B of one target instruction is completed and a read signal is issued from the microprocessor 1 to the storage devices 2 and 3,
The interrupt cutoff signal c is reset to logic "0". Note that the output timing of this interrupt cutoff (permission) signal c is performed according to the command of the control program at the same time as the output timing E of the storage device switching signal d, and is generally determined by the output timing of a counter that counts the execution unit of the instruction. stipulated. As a result, a signal f for forcibly inserting a no-operation instruction is output, and the no-operation instruction is placed on the data bus 4 of the microprocessor 1. Thereafter, after a certain period of time has elapsed from the timing C, the interrupt request signal b, which cannot be inhibited, is issued. This request signal b is of course issued to the microprocessor 1, but at the same time, the internal interrupt control flip-flop of the microprocessor 1 is set to an interrupt-disabled state. The microprocessor 1 executes a non-prohibitable interrupt process from the period indicated by the timing D due to the generation of the signal b. Note that this interrupt processing is
This is not for external interrupts, but for requests inside the emulator. However, at this point, internally in the emulator,
Other interrupts are prohibited, and even if an interrupt for the execution of the storage device 3 is issued during the period of signal c after one instruction execution cycle B is completed, the interrupt for the execution of the storage device 3 after the above timing D is disabled. No changes occur to the execution cycle.

By the way, if the interrupt request signal b is generated during the execution cycle B of one instruction, the read signal e is no longer generated at the timing C mentioned above. This is because interrupt b to the execution of the storage device 3 occurs in period F of period B, so that the processor 1
This is because the process moves to the interrupt response cycle. In the next execution cycle after this response cycle ends, the signal e will be issued at timing C. The read signal e is not issued until the execution of the processing program shown at the timing D is completed. Therefore, even if an interrupt that cannot be disabled occurs during the execution of the target set of instructions,
An interrupt will occur again before the first instruction of the processing routine is executed. It goes without saying that there is no need to deal with this in the control program as described above.

In this way, a no-operation instruction is inserted each time an instruction with a single purpose is executed, and these are executed as a pair, so that an interrupt that cannot be inhibited is generated during the execution cycle of the no-operation instruction. As a result, even if the microprocessor includes processing for interrupt requests that cannot be prohibited, it is possible to emulate it by executing it alone (single step). Also, as is already clear, even if the control program does not exist on the storage device that stores the target instruction group,
The execution control described above is possible. Therefore, it is possible to effectively and easily emulate microprograms of various microcomputer systems, and it has great effects such as being highly practical.

Note that the present invention is not limited to the above embodiments. For example, the form of the no-operation command may be appropriately adopted as long as the command substantially performs a no-operation function. Furthermore, one instruction execution cycle is not defined as two units of time.
In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a basic schematic configuration diagram of an emulator according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining its operation timing. 1... Microprocessor, 2... Control storage device,
3... Execution instruction storage device, 4... Data bus, 5, 6
...bus cutoff circuit, 7...machine cycle counter,
8...Switching flip-flop, 9a, 9b, 11,
13, 14...Gate circuit, 10...Processor status detection circuit, 12...Interrupt signal selection circuit, 1
5...No-operation instruction storage device.

Claims (1)

[Claims] 1. In a microcomputer emulator for a microprocessor having a non-prohibitable interrupt means, a means for inserting a no-operation instruction after execution of the intended instruction of the microprocessor, and a means for inserting the no-operation instruction. means for generating a non-prohibitable interrupt and prohibiting the generation of other interrupts during an execution cycle;
means for causing the execution process of the non-prohibitable interrupt to be executed in a storage device other than the storage device storing the target instruction, and the execution process of the target instruction is executed by the no-operation instruction. A microcomputer emulator is characterized in that an interrupt is generated only during the execution cycle of this no-operation instruction.