JPS629952B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a memory installation check device for a storage device that allows memory to be removed and replaced in order to replace the control data in a control device that performs automatic control using control data read from the storage device. In recent years, many examples of mechanical devices have become known that sequentially perform automatic control by using electronic memories made of integrated circuit elements and reading out control data stored in the electronic memories. Electronic memories of considerable capacity have come to be used, for example, in mechanical devices such as sewing machines and hand knitting machines, which are equivalent to household items, without having to worry much about the cost. In order to further expand the control capability of a control device using an electronic memory, the present invention provides a method for replacing each memory device storing different storage data by attaching and detaching it to a controlled device. The main purpose of this invention is to provide a means for checking, prior to use, whether or not the connection with the attached device is complete at the connecting end. To be more specific, for example, Japanese Patent Application Laid-Open No. 1983-1970, which was filed earlier than the present applicant,
No. 74156, etc. In technical means such as needle selection control of hand knitting machines or display of the number of knitting width stitches of knitting patterns, the control data can be replaced with another one by replacing the memory element, and a wide range of control can be achieved. In this case, even a general user who is relatively inexperienced in electronic circuit technology can know whether the memory element has been completely replaced, and can therefore handle the device accordingly. This paper attempts to disclose a technology that facilitates this process. Examples will be described below with reference to the drawings. First, a block 101 on the upper left side of FIG. 1 is a schematic representation of the needle selection control section of the knitting needles of a hand knitting machine, the details of which can be seen in the above-mentioned prior patent application, JP-A-53-74156. In that case, the memory 104 stores needle selection data corresponding to a certain knitting pattern. As a result, the readout address of the memory 104 is commanded using the detection signal of the knitting needle acting on the lowering cam of the knitting machine carriage (not shown) in the knitting machine needle bed 129, and the needle selection data read out according to the address is commanded. In the data processing calculation circuit 105 in the control block 101, the detection signal of the active knitting needle is used together with the calculation for controlling the selected knitting needle for each knitting needle. In the case of the present invention, a memory 104 in which connection check data is stored in advance at two addresses is used, and an address for reading the connection check data is given prior to the operation of the control block 101. , to determine whether the read data is correct or incorrect. Therefore, to describe the gist of the present invention in detail, the address switching circuit 102 receives the needle signal from the control block 101 or the needle signal of the present invention depending on which side of the input terminals D1 and D2 of the switching signal is inputted. Select the check address as input as one of the requirements for
When the D1 side is activated as a switching signal, a check address is output, and when D2 is activated, a needle signal is output as an address. As mentioned above, the memory 104 stores predetermined check data at two addresses in advance, and in this embodiment, all bits are stored as the first check address.

The check data when the bit becomes [0] is [01010101], and the check data read out in response to all bits [1] as the second check address is stored so that it becomes [10101010]. . For memory addresses other than these two check addresses, each control block 10
Various desired control data for one control purpose are stored, and when the switching signal D2 is applied, the control data are sequentially read out in accordance with the address of the hand signal. In this embodiment, the power supply and mode control terminals of the memory 104 are omitted. Each read data output terminal from the memory 104 is
It is connected in parallel to a group of exclusive OR elements 106 to 113 via a connector 103, and also connected in parallel to a read data processing arithmetic circuit 105 of control block 101. The arithmetic circuit 105
For example, in the case of JP-A-53-74156, the needle selection data read out from the memory is correlated with the needle signal indicating which needle among the knitting needles of the hand knitting machine. Its role is to selectively control needle selection for knitting needles. As is well known, the exclusive OR elements 106 to 113 have no output effect when the two inputs have the same sign, and act as an output when the inputs have different signs.
data is input to one terminal each, and address switching circuit 1 is used as one condition input for each terminal.
The T2 signal of the check address input of 02 and the T2 signal inverted by an inverter 114 are alternately and sequentially distributed and connected as shown in the figure. To explain the relationship between the T2 signal and each exclusive OR input here, the T2 signal terminal is connected in parallel to all bits of the check address input of the address switching circuit 102, and the signal content is

When it is [0], the memory output data is [01010101] as described above.
From the top on the diagram of the exclusive OR element, starting from the top signal, the element 106 is

[0] is
The element 107 has the following [1], and the element 108
to

[0] and [1] are alternately distributed and connected to the element 113. Therefore, when the content of the T2 signal is [1], all bits are [1]. Memory read data according to the check address [10101010]
In contrast to the above, element 106 is [1] and element 107 is [1].
for

[0] and the sequential element 113 is

[0] is input, and this relationship between the memory output data and the exclusive OR elements 106 to 113 is as follows as long as the connections at the connector 103 are all normal. Shibuor element 1
06-113. Each of the exclusive OR elements is for detecting an abnormality in the connection of the connector 103 as just described, and for this purpose, the elements 106 are
The configuration is such that the T2 signal is supplied to the element 107, the inverted signal of T2 is supplied to the element 107, and the conditions for exclusive OR detection are alternately supplied to the element 107. . Therefore, now the content of the T2 signal is

If [0] indicates that the connector 103 in the first digit is normal for both input and output of the memory 104, both inputs to the element 106 will be input.

[0] is given and the output has no effect.
Similarly, the two elements 107 are input [1] and the output is inactive, and the corresponding connectors 103
As long as the connections are normal, none of the elements 106 to 113 output any output. Therefore, if any connection is incomplete or if there is a short circuit between adjacent connector pins, an output will be generated at any of the elements 106 to 113, which will be output at the OR element 115. This is a configuration in which detection is output. The output of the OR element 115 is connected to one input terminal of an AND element 116, and the other input of the AND element 116 is connected to a T2 signal and a T4 signal, which will be described later as gate signals, via an OR element 123. When the T2 signal is output, the read data is checked according to the check address [11111111], and when the T4 signal is output, the read data is checked according to the check address [00000000]. AND element 116
An alarm display circuit 117 is connected to the output terminal of the alarm display circuit 117 , and the alarm detection output is inverted via an inverter 118 and is input to an AND gate 119 . The AND gate 119 opens and closes the clock pulse C from a pulse oscillator (not shown) to be input into the counter 120 at the next stage.
2, when there is no T7 output, the gate becomes open and the counter 120 starts counting. The reset end of the counter 120 is normally held in reset by a normally closed switch 121, and does not count unless the switch 121 is opened. As shown in FIG. 2, the switch 121 is connected to the connector 103 of the knitting machine main body 128.
When the printed circuit board 127 with the memory 104 attached thereto is inserted into the connector 103, the switch 121 is opened via the switch actuator 130.
When the memory 104 is connected to the counter 12
Counting of 0 starts. If the memory 104 is directly connected to and removed from the connector 103 without intervening the printed board 127 as in this embodiment, a manually operated switch 121 is used. Each bit output of the counter 120 is sent to the decoder 12.
2, and when the count value of the counter 120 is [2], [4], or [7], the decoder 122
outputs T2, T4, and T7 are produced at each output terminal. The T7 output of the decoder 122 is connected to a normal display circuit 126 and also connected to one gate input of an AND gate 119 via an inverter 125.
Furthermore, the T7 output is also connected to the switching signal end of the address switching circuit 102, and when the T7 signal is in the output state, it acts as a switching input on the D2 side, causing the needle signal from the control block 101 to act on the address in the memory 104. . When the number of stitches on the counter 120 is between [0 and 6], the T7 output is still not output and is inverted via the inverter 124 and inputted to D.
The address switching circuit 102 inputs and selects the check address side as described above. The signal T2 for the check address is the T2 output of the decoder 122. Furthermore, the T2 output is connected to one input terminal of the OR element 123, and the other output T4 of the decoder 122 is connected to the remaining inputs of the OR element 123. Alarm display circuit 117
A warning light 131 that is lit by the output of the knitting machine 126 and a pilot 132 that is lit by the output of the normal display circuit 126 are appropriately installed on the knitting machine body 128 so as to be easily seen as shown in FIG. To summarize the operation of the device of the present invention as explained above, first, before the printed circuit board 127 with the memory 104 attached is inserted into the connector 103, the switch 121 is closed and the counter 120 is not reset. Therefore, the count of counter 120

At [0], all three output terminals of the decoder 122 are non-output, so the OR element 123
The AND element 116 is kept in the closed gate state through the gate, the warning light 131 does not light up, and the decoder 122
Since there is no T7 output, the pilot 132 is also not lit. In this state, the address switching circuit 102 has the check address side selected as an input when the switching signal is input to the D1 side, and when the memory 104 is inserted into the connector 103 via the printed board 127, the memory 104 is fully loaded as described above. bit

In response to the first check address [0], if the connection at the connector 103 is normal, [01010101] is read from the memory 104. and exclusive or element 10
6 to 113, while signals of the same sign are given to the remaining inputs in exactly the same order, so the OR element 115 is non-output, and in this state the decoder Even if the T2 output or T4 output of 122 occurs and the OR element 123 outputs, the AND element 116 does not output, and the warning light 131
does not light up. At this time, the reset of the counter is canceled by opening the switch 121, and the AND element 116 is not output and the inverter 1 is turned off.
First, one of the AND gates 119 receives an open gate signal through the AND gate 18, and since the T7 output of the decoder 122 is still inactive, the remaining gate input is also in the open gate state. , so the counter 120 starts counting the clock C. When the count is [2], the T2 output of the decoder 122 is generated, and the input of the check address end of the address switching circuit 102 is affected by the second check address of all bits [1], and the memory 104 Then, check data [10101010] is read out. This inversion of the contents of the T2 signal is similarly transmitted to the condition input side of each exclusive OR element 106 to 113, so that the connection of connector 103 is normal and the check read from memory 104 is confirmed. If the data is correctly transmitted to each of the exclusive OR elements 106 to 113, no input will still be given to the OR element 115, and the warning light will not illuminate. As above, counter 1
When the count of 20 is [2], the output of the decoder 122
The read data corresponding to the check address with all bits [1] is checked by the T2 signal, and when the count of the counter 120 is [4], the decoder 12
All bits are output by the output T4 signal of 2.

The read data is checked according to the check address [0]. When the count of the counter 120 advances to [7], the output T7 of the decoder 122 acts, the pilot 132 lights up, and at the same time, the AND gate 119 is closed via the inverter 125. , counter 120
remains at count [7], and the T7 signal is maintained thereafter. By this T7 signal, the switching input terminal D2 of the address switching circuit 102 is switched to the active state, the input is switched from the check address side to the needle signal side of the control block 101, and the memory 102 is switched to the needle signal side of the control block 101.
Thereafter, the needle signal is used as a readout address and the stored content data of each commanded address is outputted.
The read data at this time is transmitted to the data processing arithmetic circuit 105 of the control block 101. During this time, the T2 and T4 outputs of the decoder 122 no longer occur, so the AND element 116 is in a closed gate state. When installing the memory 104, if any of the connection pins of the connector 103 have an incomplete or incorrect connection to the memory 104, or if there is an abnormality such as a short circuit between adjacent connection pins, please follow the instructions above. The T2 signal accompanying the counting operation of the counter 120 or
When the T4 signal occurs, a situation with an opposite sign occurs at the input of at least one of the exclusive OR elements 106 to 113, and therefore, at the time the T2 signal occurs or when the T4 signal The alarm display circuit 117 is activated in response to the output action of the AND element 116 via the two OR elements 115 and 123, and the warning light 131 is turned on.At the same time, the AND gate 119 is closed via the inverter 118, so that the counter 120 stops, and the decoder 122 remains in the state producing the T2 output or the T4 output. Therefore, the decoder 122 does not produce the T7 output, so the pilot 132 is not illuminated and the address switching is performed. The switching signal end of circuit 102 also remains active on the D1 side so that control block 101 cannot command the reading of control data from memory 104 until the memory attachment at connector 103 is properly corrected. FIG. 4 shows an example in which the technology of JP-A No. 53-81754 is applied. Compared to FIG. 1, the output data of the memory 104 is arranged by the pattern converter 59 and the data processing calculation circuit 105 detects the active knitting needle. The difference is that needle selection control is performed by performing computation for selective knitting needle control for each knitting needle together with the signal. Therefore, by replacing the memory 104 and arranging it using the pattern converter 59, it is possible to increase the types of patterns that can be knitted. Also in FIG. 4, the power supply and mode control terminals of the memory 104 are omitted. FIG. 5 shows the case when applied to Japanese Patent Application Laid-Open No. 53-111151. The memory 104 stores in advance the number of stitches such as sweater, stew, etc. according to the address input, and numerically displays the output of the memory 104 according to the address of the number of sets related to the number of knitting rows of the forming instruction circuit 201 + the number of knitting rows 202. A number is displayed on the number display device 204 via the circuit 203, and the knitting machine user sets the number of stitches to the number of stitches. In this case as well, the memory 104 stores check signals as in the case of FIGS. 1 and 4, and the memory 104 and its terminals can be checked in the same manner. By replacing the memory 104, it is possible to increase the types of molding such as sweaters and sweatshirts. In addition, although an example is omitted, as in Japanese Patent Application Laid-open No. 106858/1983, the forming information of a sweater, etc. once knitted by the user is stored in random access (RAM) according to the number of knitting stages, and then the user If you want to knit the same thing again, this time you can also display the stored RAM contents numerically according to the number of knitting stages.
RAM is non-volatile RAM (once the memory is stored, the power is turned off)
It is possible to apply the present invention by using the memory function (which remembers even if it is turned off). As described above, according to the present invention, desired storage data can be supplied to the control circuit of each target device without the necessity of connection abnormality when replacing and installing an electronic memory, and it is possible to supply desired storage data to the control circuit of each target device. It allows complete and easy use even in the case of a competent operator. Moreover, in an embodiment in which the control data is replaced by replacing the printed board with the memory attached to the printed board, the connection pins of the memory of the integrated circuit element, which are easily damaged, are also directly burdened with the mounting and removal. Since it is not exposed, there is no risk of damage and it is easier to handle.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram of the present invention, Fig. 2 is a partial front view schematically showing an embodiment of a main part of the present invention, and Fig. 3 is an embodiment in which the configuration shown in Fig. 2 is installed on a hand knitting machine. The partial perspective views of FIG. 4 and FIG. 5 are other embodiments corresponding to FIG. 1. 129... Address output device, 104... Electronic storage element, 105, 59, 105, 203... Control circuit, 103... Connector.

Claims (1)

[Scope of Claims] 1. An address output device that outputs an address signal, an electronic memory element that outputs control information stored in advance in response to the address signal, and a control circuit that automatically controls the output of the electronic memory element. In the control device, an electronic storage element that stores connection check information in addition to the control information is connected between the address output device and the control circuit, and the electronic storage element is removable and exposed from the main body of the control device. a connector that is connected to the electronic storage device; a switch device that operates when the electronic storage device is attached to the connector; and a device that outputs a check address signal to the electronic storage device via the connector by the operation of the switch device; Inspection means for inspecting the connection state between the electronic storage element and the connector according to connection check information output from the electronic memory element in response to a check address signal, and display means for displaying the inspection result output from the inspection means. A removable electronic storage connection device comprising: 2. The removable electronic storage device connecting device according to claim 1, wherein the switch means is disposed in the connector and is activated by attaching the electronic storage element to the connector.