JPS6310461B2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a buffer memory control method in a storage system in which main memory and buffer memory are managed by a store-in method. The present invention relates to a buffer memory control method for cases where

(Prior Art) Conventionally, in this type of buffer memory system, when the requested data requested to be accessed by the memory access device does not exist in the buffer memory, the block data including the requested data is transferred from the main memory to the internal buffer memory. The block is loaded into. At this time, if a fault is detected in data other than the requested data in the corresponding block stored in the main memory, the access request from the memory access device is processed as an access request to the faulty data. However, even though there is no problem with the requested data that was accessed, a block loading operation occurs, so the requested data is treated as faulty data, which reduces the reliability of the system. It was hot.

(Object of the Invention) An object of the present invention is to retrieve block data including the requested data from the main memory when the requested data requested to be accessed by the memory access device does not exist in the buffer memory in a store-in type buffer memory control method. When a block is loaded into the buffer memory, if there is a failure in data other than the requested data included in the block data, if the access request from the memory access device is a read request, the block data from the main memory is loaded into the buffer memory. After storing the request data in the buffer memory, the request data requested to be read is transferred to the memory access device, and if the access request is a write request, the data is transferred to the main memory. The block data from the buffer memory and the write data associated with the write request are merged and written into the buffer memory, and then the corresponding block data inside the buffer memory is written to the main memory, and the corresponding block data inside the buffer memory is invalidated. The above-mentioned drawback is solved by providing a means for accessing the memory, so that if there is no fault in the requested data in the block data, the access request from the memory access device will be processed normally even if a fault is detected in other data. An object of the present invention is to provide a buffer memory control method configured to improve the reliability of the system.

(Structure of the Invention) The present invention includes a main memory and a buffer memory,
This is an improved buffer memory control method in a storage system in which main memory and buffer memory are managed by a store-in method.

In the present invention, the buffer memory control method is implemented with means for determination.

The means for determining this is to block load block data including the requested data from the main memory to a block to be replaced in the buffer memory when the requested data requested to be accessed by the memory access device does not exist inside the buffer memory. If a failure is detected in data other than the requested data included in the block data, if the access request from the memory access device is a read request, the requested data included in the block data is transferred to the memory access device. It is also used to invalidate the block to be replaced inside the buffer memory.

The means for determining further includes, if the access request from the memory access device is a write request, the block data and the write data associated with the access request are merged and written to the replacement target block in the buffer memory, and then the replacement target block is written. This is for writing the block data contained in the block into the main memory and invalidating the block to be replaced.

(Example) Next, the present invention will be described by showing an example. FIG. 1 is a diagram showing an embodiment of the configuration of a device for realizing the buffer memory control method according to the present invention. In FIG. 1, the device includes a main memory 1, a buffer memory 2, a memory access device 3, and a control section 4. The buffer memory 2 consists of an address array section 10 for storing main memory addresses, control information, etc., and a data array section 20 for storing data. The control information of the address array section 10 includes information indicating whether block data corresponding to the main memory address stored in the address array section 10 is stored in the data array section 20 or not. This information is called V bit. When the value of the V bit is 1, it indicates that the block data corresponding to the main memory address is stored in the data array section 20, and when the value of the V bit is 0, it indicates that the corresponding data does not exist. show. The main memory address of the address array section 10 is a block address, and the data of the data array section 20 is block data. Further, the relationship between the main memory 1 and the buffer memory 2 is controlled by a store-in method.

The operation of the above configuration will be explained based on the above explanation. When the memory access device 3 makes an access request to the buffer memory 2, whether or not the requested data exists in the buffer memory 2 is determined based on the V bit of the address array section 10 and the main memory address. This determination means compares the main memory address of the address array section 10 with the memory address from the memory access device 3, and further determines whether the value of the V bit of the address array section 10 is 1 or not. . Here, if the memory addresses match and the value of the V bit is 1, it indicates that the requested data from the memory access device 3 is stored in the data array section 20, and if the memory addresses do not match or the V bit If the value is 0, it indicates that the requested data does not exist in the requested data array section 20.

Here, a case where the requested data in response to an access request from the memory access device 3 is stored in the data array section 20 is called a block hit, and a case where the requested data does not exist in the data array section 20 is called a block miss.

The present invention improves the block load in the case of a block mishit. Generally, in the case of a block mishit, the block load is as follows:
By omitting the number of signal lines of the interface signal line 101 between the main memory 1 and the buffer memory 2, one block is transferred multiple times. In this explanation, 1 block is 64 bytes, and 4
Block loading is performed by transferring the data once. That is, block loading is performed by transferring one block four times every 16 bytes. When the 16-byte requested data accessed by the memory access device 3 results in a block miss,
The control unit 4 includes request data for the main memory 1.
The 64-byte block data is stored in the replacement target block inside the buffer memory 2 through four transfers. Here, if there is an empty block in the buffer memory 2, that empty block is detected as a block to be replaced by the first detection means, and if there is no empty block in the buffer memory 2, the most recently referenced block is swapped out onto the main memory, The second detection means detects the swap-out target block as a replacement target block, and the block is so-called LRU (Least Recently Used).
controlled by the method. Furthermore, among the block data to be transferred to the buffer memory 2, request data is generally the first to be transferred from a performance standpoint. Therefore, the data transferred from the second time onwards is not the requested data requested for access.
Here, if the access request from the memory access device 3 is a read request, the first transferred
If there is no fault in the 16-byte data, it is written to the block to be replaced, and the requested data is transferred to the memory access device 3 via the interface signal line 102. After that, the data transferred from the second time onwards are sequentially written to the replacement target block, and 64
After writing all the bytes of block data, if it is not detected in the second or subsequent transfer data, the value of the V bit in the address array section 10 is set to 1, and if a failure is detected, the value of the V bit is set to 1. Set to 0.

When the access request from the memory access device 3 is a write request, if there is no problem with the first 16 bytes of data transferred, the write data associated with the access request is written to the block to be replaced, and the data is sent to the memory access device 3. The completion of writing is reported via the interface signal line 102. After that, the data transferred from the second time onwards will be sequentially transferred.
Write to the block to be replaced. When all 64 bytes of block data have been written, if no failure is detected in the second and subsequent transfer data, the value of the V bit in the address array section 10 is set to 1, and the value of the E bit is set to 0. Set to .
In this case, if a fault is detected, the value of the V bit is set to 1, the value of the E bit is set to 1, and then the block data of the block to be replaced is swapped out to the main memory 1. At this time, since the value of the E bit is 1, detection of block data failures associated with the swap-out operation is suppressed. Upon completion of this faulty block data swap-out operation, the value of the V bit is set to 0 and the value of the E bit is set to 0.
If the memory access device 3 makes an access request again, if the request is for block data whose E bit value is 1, it will have to wait until the E bit value becomes 0. , which may lead to a decrease in performance. Therefore, this swap-out operation of faulty block data is
It is necessary to do this immediately after the above block word operation is completed.

(Effects of the Invention) As described above, in the present invention, when there is a failure in the subsequent reply data in the block load operation when a block miss occurs in store-in type buffer memory control, the access request becomes a read request. If so, the value of the V bit in the address array section is set to 0, and if it is a write request, the value of the V bit is set to 1, and the value of the E bit is set to 1, and then written to the data array section. By configuring the block data to be read, swapped out to main memory, set the V bit value to 0, and further set the E bit value to 0, failures in data other than the accessed data can be ignored. This has the effect of improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a configuration for realizing a buffer memory control method according to the present invention. DESCRIPTION OF SYMBOLS 1...Main memory, 2...Buffer memory, 3...Memory access device, 4...Control unit, 10...Address array unit, 20...Data array unit, 101-103
…Signal line.

Claims (1)

[Claims] 1. In a storage system comprising a main memory and a buffer memory, in which the main memory and the buffer memory are managed by a store-in method, when there is no requested data accessed by a memory access device in the buffer memory, When block loading block data including the request data from the main memory to the replacement target block in the buffer memory, if a fault is detected in data other than the request data included in the block data, the memory access device means for transferring the request data included in the block data to the memory access device and invalidating the replacement target block inside the buffer memory if the access request from the buffer memory is a read request; In addition, if the access request from the memory access device is a write request, the block data and the write data associated with the access request are merged and written to the replacement target block of the buffer memory, and then the data included in the replacement target block is 1. A buffer memory control method, comprising means for writing said block data into said main memory and invalidating said block to be replaced.