JPS6310520B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention uses, for example, an insulated gate field effect transistor (hereinafter referred to as MOST) as a basic element of a memory cell, and when a defective memory cell exists, the defective memory cell is The present invention relates to a semiconductor memory device with a redundancy function that replaces memory cells with spare memory cells.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device with a redundant function. In the figure, 1 is a memory cell array in which memory cells are arranged in a matrix, 2 is a row decoder to which address input signals A ₀ to Am _-1 are input and obtains 2 ^m row selection signals, and 3 is a row decoder that receives 2 m row selection signals.
4 is a column decoder to which address input signals Am to An are input and obtains ^2N column selection signals (n-m=N), and 4 is an output terminal 4a that outputs a read output signal Q and a data input. An input terminal 4b to which a signal D is applied serves as an output buffer for a data signal read from a memory cell located at the intersection of a selected row and column, and an input for writing write data D into the selected memory cell. A buffer circuit serves as a buffer, 5 is a spare memory cell row provided with spare memory cells, and 6 is a spare row decoder corresponding to this spare memory cell row.

Note that although other signals necessary for the functions of this memory device with redundant function are not shown, it goes without saying that these are provided.

Next, the operation of the semiconductor memory device with redundancy function having the above configuration will be explained. First, due to a manufacturing defect in the memory cell array 1, for example, one
If a defective bit or one row exists and this defective bit is detected during a memory wafer test, the selected row is deactivated and a spare row decoder is activated by the selection signal and a spare row decoder connected to it is activated. I try to eliminate defects by replacing them with spare lines. As a method to inactivate this defective bit and to activate the spare decoder, there is a method of cutting the built-in fuse electrically or with laser light, or a method of reducing the resistance of a high resistance fuse with laser light. is known, but
Both methods are done inside the memory element, so
After being stored in a package, it is impossible to determine whether the memory device uses the redundant function. Therefore, recently, as a method to determine whether the memory is using the redundant function even after being stored in a package, the data input signal D of the memory is set to a high voltage, and the read output signal Q is input while inputting the address signal. It is suggested that you investigate. That is,
The memory cells corresponding to the address signals for which the read output signal Q is at a low level do not use the redundancy function, while the memory cells corresponding to the address signals for which the read output signal Q is at a high level use spare memory cells. It is determined that there is.

However, in conventional semiconductor memory devices, a memory cell array with a redundant function has a drawback that it is impossible to determine whether or not the memory cell array uses the redundant function after it is housed in a package without performing a complicated test. It was hot.

[Summary of the invention]

Therefore, an object of the present invention is to provide a semiconductor memory device that allows a simple test to determine whether a memory cell array uses a redundant function even after being housed in a package.

In order to achieve such an object, the present invention provides a gate circuit that takes the logical sum of each preliminary decoder output signal of the preliminary decoder, and connects the output terminal of this gate circuit to an external terminal to adjust the level of this external terminal. This method makes it possible to determine whether the redundant function is to be used or not, and will be described in detail below using examples.

[Embodiments of the invention]

FIG. 2 is a block diagram showing one embodiment of a semiconductor circuit built into a semiconductor memory device according to the present invention. In the same figure, reference numerals 6a to 6n are spare row decoders whose detailed circuits are shown in FIG. activated by. Reference numeral 7 denotes a NOR gate circuit that takes a NOR gate for the spare decoder output signals of the spare row decoders 6a to 6n, and 8 is an output terminal of this NOR gate circuit 7, which is connected to a pin of a package (not shown) and connected to the outside of the memory cell array. ing.

Note that the spare row decoders 6a to 6n shown in FIG.
, 9 is a power line of power supply voltage Vcc, and 10 precharges an output node 11 connected to a spare row line when a precharge signal ψ _p is input to the gate. Output side MOST, 12a ₁ , 12a ₂ ~ 12
m ₁ and 12m ₂ constitute this spare row decoder MOST, 13a ₁ , 13a ₂ to 13m ₁ and 13
_m2 is a spare fuse that can be cut with a laser beam, 14
is the ground wire with potential Vss.

Next, the operation of determining whether or not to use the redundant function of the semiconductor memory device with the above configuration will be described. First, if no defective bit is detected in the memory cell array and the redundancy function is not used, the spare fuses 13a ₁ to 13m ₂ are not disconnected. On the other hand, when a memory cell is activated, one of the address input signals _{A 0} , ₀ , _.
Always one of them becomes conductive. Therefore, the output node 11 is discharged and the spare row decoders 6a to 6
The spare decoder output signal from n is not sent out and is at a low level, and no spare row line is selected. Therefore, the output of the NOR gate circuit 7 becomes high level. Next, for example, address signal A ₀ =“H”,
...The regular row is selected when Am="L",
If a bad bit is detected in that row, the redundancy feature is used. That is, a normal line in which a defective bit has been detected is made inactive (not shown). next,
In order to activate this spare row decoder, the corresponding fuses 13a ₁ to 13m ₂ are cut with a laser beam.
Therefore, the address input signal A ₀ , ₀ , ...Am,
One of the Am pairs is always at a high potential, but since the corresponding fuse is cut, the precharged output node 11 is not discharged. Therefore, for example, a high-level spare decoder output signal is output from the spare row decoder 6a, and a spare row line is selected. Therefore, a low-level NOR gate signal is output from the output terminal 8 of the NOR gate circuit 7. Therefore, it can be seen that this semiconductor memory device uses a redundancy function. In this way, by measuring whether the output terminal 8 of the NOR gate circuit 7 is at a high level or a low level, it is possible to easily determine whether the semiconductor memory device uses the redundancy function. .

FIG. 4 is a block diagram showing another embodiment of the semiconductor circuit incorporated in the semiconductor memory device according to the present invention. In the figure, reference numerals 15a to 15n are non-inverting buffer circuits that amplify the preliminary decoded output signals in order to reduce the load on the outputs of the preliminary row decoders 6a and 6n.

It goes without saying that the operation for determining whether or not to use the redundant function is the same as that shown in FIG. 2.

FIG. 5 is a block diagram showing still another embodiment of the semiconductor circuit built into the semiconductor memory device according to the present invention. In the figure, 16a to 16n are inverting amplifiers that invert and amplify the preliminary decoder output signals of the preliminary row decoders 6a to 6n, and 17 is a NAND gate circuit.

Next, the operation of determining whether or not to use the redundant function of the semiconductor memory device with the above configuration will be described.
First, if no defective bit is detected in the memory cell array and the redundancy function is not used, the spare fuses 13a ₁ to 13m ₂ are not disconnected.
On the other hand, when a memory cell is activated, one of the address input signals A ₀ , ₀ , _.
Always one of m ₂ becomes conductive. Therefore, the output node 11 is discharged and the spare row decoder 6a
From ~6n onwards, the spare decoder output signal is not sent out and is at a low level, and no spare row line is selected. Therefore, the outputs of the inverting amplifiers 16a to 16n become high level. Therefore, the output of the NAND gate circuit 17 is at a low level. Next, for example, when a normal row is selected with the address signal A ₀ = "H" . . . Am = "L" and a defective bit is detected in that row, the redundancy function is used. That is, a normal line in which a defective bit has been detected is made inactive (not shown). Next, in order to activate this spare row decoder, the corresponding fuses 13a ₁ to 13m ₂ are cut with a laser beam. Therefore, one of the sets of address input signals A ₀ , ₀ , . Not discharged. Therefore, for example, a high-level spare decoder output signal is output from the spare row decoder 6a, and a spare row line is selected. As a result, the outputs of the inverting amplifiers 16a to 16n become low level. As a result, a high level NAND signal is output from the output terminal 8 of the NAND gate circuit 17. Therefore, it can be seen that this semiconductor memory device uses a redundancy function. In this way, by measuring whether the output terminal 8 of the NAND gate circuit 17 is at a high level or a low level, it is possible to easily determine whether the semiconductor memory device uses the redundancy function. .

Although the above embodiments have been described with reference to a spare row decoder, it goes without saying that the same can be done when using a spare column decoder. Further, although the N-channel MOST has been described, it goes without saying that the same can be done for the P-channel MOST by reversing the polarity of the voltage. Further, although the case where the spare fuse is cut by a laser beam has been described, it goes without saying that a high-resistance spare fuse may be made to have a low resistance by a laser beam. It goes without saying that an amplifier may be connected to the output terminal of the NOR gate circuit or the output terminal of the NAND gate circuit.

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device according to the present invention, even after a memory cell array with a redundant function is housed in a package, it is easy to determine whether the redundant function is being used or not with a simple configuration. There are effects that can be determined.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional semiconductor memory device with a redundant function, FIG. 2 is a circuit diagram showing an embodiment of a semiconductor circuit built into a semiconductor memory device according to the present invention, and FIG. FIGS. 4 and 5 are circuit diagrams showing other embodiments of the semiconductor circuit incorporated in the semiconductor memory device according to the present invention. 1...Memory cell array, 2...Row decoder,
3... Column decoder, 4... Buffer circuit, 5...
Spare memory cell rows, 6 and 6a to 6n... Spare row decoder, 7... NOR gate circuit, 8... Output terminal, 9... Power supply line, 10... Output side MOS transistor, 11... Output node, 12a ₁ ,2a ₂ ...
12n ₁ and 12n ₂ ...MOS transistor, 1
3a ₁ , 13a ₂ ... 13n ₁ and 13n ₂ ... Spare fuse, 14 ... Earth wire, 15a to 15n ...
Non-inverting buffer circuit, 16a-16n...inverting amplifier, 17... NAND gate circuit. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device with a redundant function that includes a built-in spare memory cell, a gate circuit is provided to take the logical sum of each spare decoder output signal of the spare decoder, and the output terminal of this gate circuit is connected to an external terminal. A semiconductor memory device characterized in that by measuring the level of this external terminal, it is possible to determine whether or not to use a redundant function. 2. The semiconductor according to claim 1, wherein the gate circuit is a NOR gate circuit that takes the logical sum of the respective preliminary decoder output signals or the logical sum of the output signals amplified by a non-inverting amplifier. memory device. 3. The semiconductor memory device according to claim 1, wherein the gate circuit is a NAND circuit that takes the logical sum of output signals obtained by amplifying the respective preliminary decoder output signals with an inverting amplifier.