JPS6310607B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase processing circuit suitable for use in FM detection circuits and the like, and is particularly designed to achieve low voltage operation.

As a recent FM detection circuit, a quadrature detection circuit using a double-balanced differential amplifier as shown in FIG. 1 is often used. However, this circuit is not very suitable for low voltage operation because it has a configuration in which many transistors are connected in series between the power supply line and the ground potential (three transistors in FIG. 1). In FIG. 1, D ₁ , D ₂ , D ₃ are transistors Q ₁ , Q ₂ , transistors Q ₃ , Q ₄ ,
It is a differential amplifier consisting of each pair of transistors Q ₅ and Q ₆ , 11, 12, and 13 are first, second, and third current mirror circuits, and 14 is a capacitor C ₁ ,
C ₂ and a phase shift circuit formed by coil L ₁ . The double-balanced differential amplifier is formed by first, second, and third differential amplifiers D ₁ , D ₂ , and D ₃ , and has an emitter formed between the power supply line 15 of this circuit and the ground potential. The collector current path uses a constant current source _IS as a common current source. V ₁ , V ₂ , and V ₃ are DC bias power supplies, and V _IN1 and V _IN2 are input FM signals. In addition, a capacitor is connected to the output terminal 16.
C ₃ and resistor R ₁ are connected.

In the above FM detection circuit, if the output signal of the output terminal 16 is I ₀ and each transistor has the same characteristics, when there is no signal, I ₀ (DC) = (I _C3 + I _C6 ) - (I _C4 + I _C5 ) = (1/4I _S +
1/4I _S ) - (1/4I _S + 1/4I _S )=0 However, I _C3 , I _C4 , I _C5 , and I _C6 are the respective collector currents of transistors Q ₃ , Q ₄ , Q ₅ , and Q ₆ , I _S is the current flowing through the constant current source I _S.

I ₀ =0 means that an equilibrium state is maintained.

Next, the operation when a signal is present will be explained.

Now, to simplify the explanation, a case of a rectangular wave complete switching operation will be explained.

Now, the base input signal of transistor _Q1 is
V _B1 , the base input signal of transistor Q ₂ to V _B2 ,
Expressed as follows, V _B1 = V ₁ + V _IN1 V _B2 = V ₁ + V _IN2 = V ₁ − V _IN1 . Input signals V _IN1 and V _IN2 are set to have opposite phases.

Next, the base input signal of transistor Q ₃ is expressed as V _B3 The base input signal of transistor Q ₄ is expressed as V _B4 The base input signal of transistor Q ₅ is expressed as V _B5 The base input signal of transistor Q ₆ is expressed as V _B6 , V _B3 = V _B5 = V ₂ + _IN3 V _B4 = V _B6 = V ₂ . V _IN3 is a signal between the bases of transistors Q ₃ and Q ₄ .

Here, I _C3 = I _S when V _B1 > V _B2 and V _B3 > V ₂ , and transistors Q ₁ and Q ₃ are turned on.

Next, for I _C4 = I _S , V _B1 > V _B2 and V _B3 < V ₂ , and transistors Q ₁ and Q ₄ are turned on.

Next, for I _C5 = I _S , V _B1 < V _B2 and V _B5 > V ₂ and transistors Q ₂ and Q ₅ are turned on.

Next, I _C6 = I _S only when V _B1 < V _B2 and V _B5 < V ₂ , and transistors Q ₂ and Q ₆ are turned on.

However, I _C3 , I _C4 , I _C5 , and I _C6 are collector currents of transistors Q ₃ , Q ₄ , Q ₅ , and Q ₆ , respectively.

The operating waveform obtained under each of the above conditions is the second
As shown in Figures a to e and Figures 3 a to e. Second
The figure shows the current system on the transistor _Q1 side, and FIG. 3 shows the current system on the transistor _{Q2 side} .

Figure 2a shows the voltage waveform of the base input signal (V _B1 = V ₁ + V _IN1 ) of the transistor Q ₁ .
The waveform changes in the positive and negative directions around the reference bias. Figure b shows the voltage waveform of the base input signal (V _B3 =V _B5 ) of the transistors Q ₃ and Q ₅ , and a phase shift of 90° with respect to the input signal is set. Figure c
is the collector current I _C3 of transistor Q ₃ , d in the same figure.
is the current waveform of the collector current I _C4 of the transistor Q ₄ , and e in the same figure is the current waveform of the collector current I _C4 of the transistor Q ⁴
This is the waveform of the combined collector current (I _C3 + I _C6 ).
Similarly, Figure 3a shows the voltage waveform of the base input signal of transistor _Q2 ( _VB2 = _V1 + _VIN2 = _V1 - _VIN1 ), and Figure 3b shows the voltage waveform of the base input signal of transistors _Q4 and _Q6 . Figure c shows the collector current of transistor _Q5 ,
d in the figure is the collector current of the transistor Q ₆ , and e in the figure is the combined collector current of the transistors Q ₄ and Q ₅ .

The waveform shown by the solid line in Figures 2 and 3 is when the input signal frequency is ₀ and the FM center frequency, and the output waveform at this time has a duty of 50% as shown in Figure 4a. , if this is smoothed, the DC level of the output signal becomes zero. Next, when the frequency becomes lower and = ₀ − Δ, Fig. 2,
A phase shift as shown by the dotted line in FIG. 3 is obtained,
The output has an output waveform shown in FIG. 4b. Therefore, the output DC level _DC1 at this time changes in the negative direction. When the frequency becomes higher and becomes = ₀ + Δ, a phase shift as shown by the dashed line in Figures 2 and 3 is obtained, and the output waveform is as shown in Figure 4 c. . Therefore, the DC level of the output at this time
DC ₂ is a change in the positive direction. In this way, the output level changes depending on the FM modulation degree of the input frequency, and the FM detection output is the continuous output of this change.

As mentioned above, the conventional circuit described above is not suitable for low voltage operation because it has a large number of transistors connected in series between the power supply line and the ground.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a phase processing circuit suitable for low voltage operation by reducing the number of transistors connected in series between a power supply line and ground.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 5, the common emitters of transistors Q ₁₁ , Q ₁₂ and Q ₁₃ are connected to a first current source _IS1 ,
The common emitter of transistors Q ₁₄ , Q ₁₅ , Q ₁₆ is
It is connected to a second current source _IS2 . If the currents flowing through the current sources I _S1 and I _S2 are I _S1 and I _S2 , I _S1 = I _S2 .

The bases of the first and sixth transistors Q ₁₁ and Q ₁₆ are connected to the DC bias V ₁ as well as the input FM signal.
V _IN1 and V _IN2 are input. Here, V _IN2 =-V _IN1 , and the phases are opposite to each other. DC bias V ₁ is
It is applied to the bases of the third and fifth transistors Q ₁₃ and Q ₁₅ as well as to the terminal 21a of the phase shift circuit 21 composed of capacitors C ₁ and C ₂ and coil L ₁ . The other terminal 2 of this phase shift circuit 21
1b, an input FM signal is applied, and the FM signal via this phase shift circuit 21 is sent to the output terminal 21.
c to the common base of the second and fourth transistors Q ₁₂ and Q ₁₄ . Here, the collectors of the first and sixth transistors Q ₁₁ and Q ₁₆ are connected to the power supply line 2.
Connected to 2.

The output of the common collector of the second and fifth transistors Q ₁₂ and Q ₁₅ is connected to an output terminal connected to the output side of the third current mirror circuit 25 via the first current mirror circuit 23 as an output circuit. 26. Also, the third and fourth transistors
The output of the common collector of Q ₁₃ and Q ₁₄ is applied to the input side of the third current mirror circuit 25 via the second current mirror circuit 24, and is led out to the output side, that is, the output terminal 26. At the output terminal 26, a capacitor C ₃ for carrier removal and a resistor R ₁ are connected.
DC bias V ₂ is connected through.

The FM detection circuit of the present invention is constructed as described above, and the first and sixth transistors Q ₁₁ and Q ₁₆ function as input circuits, and input FM signals having phases opposite to each other are applied to their respective bases. In addition, when the input FM signal is at the center frequency (unmodulated), the bases of the second and fourth transistors Q ₁₂ and Q ₁₄ are connected to the input FM signal.
An FM signal that is 90° ahead of the signal is input. As a result, an FM detection signal is obtained, and the output terminal 26
The output current I ₀ of is derived as the difference between the two input currents of the first and second current mirror circuits.

Figure 6 a-e, Figure 7 a-e, Figure 8 a-c
2 is an operation signal waveform diagram shown to explain the FM detection operation of the above circuit.

To make the explanation easier to understand, we will now explain the operation when a complete square wave switching operation is performed.

When there is no signal, I _S1 = I _S2 = I _S , and the transistors Q ₁₁ to Q ₁₆ and the current mirror circuits 23 and 2
Diodes Q ₁₇ , Q ₁₉ , Q ₂₁ , which constitute 4, 25,
Assuming that the transistors Q ₁₈ , Q ₂₀ , Q _{22 ,} etc. have the same characteristics, and ignoring the base current, the base voltage of each transistor Q ₁₁ to _{Q 16} is equal to V ₁ .
Therefore, I ₀ = I _C8 − I _C12 = (I _C2 + I _C5 ) − (I _C3 + I _C4 ) = (1/
3I _S1 +1/3I _S2 )-(1/3I _S1 +1/3I _S2 )=0. Note that I _C2 , I _C3 , I _C4 , I _C5 , I _C8 , and I _C12 are transistors Q ₁₂ , Q ₁₃ , Q ₁₄ , Q ₁₅ , Q ₁₈ ,
Q means collector current of ₂₂ .

Here, transistors Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ ,
The base input signals of Q ₁₅ and Q ₁₆ are connected to V _B1 , V _B2 , V _B3 ,
Assuming V _B4 , V _B5 , and V _B6 , V _B1 = V ₀ + V _IN1 V _B6 = V ₁ + V _IN2 = V ₁ − V _IN1 V _B2 = V _B4 = V ₁ + V _IN3 V _B3 = V _B5 = V _1. be. V _IN3 is the FM signal after the input FM signal passes through the phase shift circuit 21.

Therefore, I _C2 is I _C2 only when V _B1 < V ₁ and V _B2 > V ₁
= _IS .

I _C3 is I _C3 only when V _B1 < V ₁ and V _B2 < V ₁
= _IS .

I _C4 is I _C4 only when V _B6 < V ₁ and V _B4 > V ₁
= _IS .

I _C5 is I _C5 only when V _B6 < V ₁ and V _B4 < V ₁
= _IS .

The above operation waveforms are as shown in FIGS. 6 and 7. FIG. 6a shows the base input signal V _B1 of the transistor Q ₁₁ , and FIG. 6 b shows the base input signal V _B2 =V _B4 of the transistors Q ₁₂ and Q ₁₄ . The figure c shows the collector current I _C3 of the transistor _Q13 , and the figure d shows the collector current I C3 of the transistor Q13.
is the collector current I _C2 of transistor Q ₁₂ . Further, e in the same figure is the common collector current I _C2 +I _C5 of the transistors Q ₁₂ and Q ₁₅ . Similarly, FIG. 7a shows the base input signal V _B6 of the transistor Q ₁₆ , and FIG. 7 b shows the base input signal V _B2 =V _B4 of the transistors Q ₁₂ and Q ₁₄ . The figure c shows the collector current I _C5 of the transistor Q ₁₅ , and the figure d shows the collector current I _C4 of the transistor Q ₁₄ . In addition, e in the same figure shows the transistor Q ₁₃ ,
The common collector current of _Q14 is I _C3 + I _C4 .

In FIGS. 6 and 7, the waveforms indicated by solid lines are
When the frequency of the input signal is = ₀ , which is the FM center frequency, the output waveform at this time has a duty of 50% as shown in Figure 8a, and if this is smoothed, that is, if the carrier is removed, The DC level of the output signal becomes zero. Next, when the frequency becomes lower and = ₀ - Δ, a phase shift as shown by the dashed line in FIGS. 6 and 7 is obtained, and the output has the output waveform shown in FIG. 8b. Therefore, the output DC level DC ₁ at this time changes in the positive direction. Also, the frequency increases,
= ₀ + Δ, a phase shift as shown by the dotted line in FIGS. 6 and 7 is obtained, and the output waveform is as shown in FIG. 8c. Therefore, the output DC level DC ₂ at this time changes in the negative direction. Input frequency FM like this
The output level changes depending on the degree of modulation, and the FM detection output is the continuous output of this change. Capacitor C ₃ is a carrier (2 ₀ at the output end)
, and the resistor R ₁ serves to convert the current output into voltage.

What is particularly noteworthy about the circuit of the present invention described above is that between the power supply line and the ground potential end,
Excluding the current source, there are only two elements (transistors) connected in series. As a result, this circuit can operate with a very low voltage power supply, making it ideal for low power consumption and integration. Furthermore, the level of the output average DC current does not vary depending on the presence or absence of the FM signal (when not modulated). Therefore, this output can be used for automatic frequency control.
Also suitable for use in AFC circuits. Furthermore,
(I _C2 + I _C5 ) and (I _C3 +
Since it outputs the current difference between I _C4 ),
Detection efficiency is also high.

Furthermore, in this circuit, as shown in FIG.
If the emitter areas of the transistors Q ₁₁ and Q ₁₆ are made larger (eg, twice) than those of the transistors Q ₁₂ , Q ₁₃ , Q ₁₄ , and Q ₁₅ , the detection output distortion can be further improved. This can be understood from the fact that when considering the internal distortion of the transistor, the current dependence is increased on the transistor portion that has a balanced operation relationship.

In the above explanation, the FM detection circuit is explained, but the first input signal is connected between the bases of the transistors Q ₁₁ and Q ₁₆ , and the transistors Q ₁₂ and
It can also be applied as a circuit that adds a second input signal to the common base of _Q14 and obtains the phase detection output of both signals.

As mentioned above, this invention has no fluctuation in the output average level regardless of the presence (non-modulation) or absence of an FM input signal, has high detection efficiency, and can operate at a particularly low voltage compared to conventional methods. It can also be used in monolithic (bipolar) ICs to provide even more effective phase processing circuits.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional FM detection circuit, Figures 2 a to e, Figures 3 a to e, and Figures 4 a to c are operating signals shown to explain the operation of the circuit in Figure 1. A waveform diagram, FIG. 5 is a circuit diagram showing an embodiment of the present invention,
6 a to e, 7 a to e, and 8 a to c are operation signal waveform diagrams shown to explain the operation of the circuit in FIG. 5, and FIG. 9 is another embodiment of the present invention. It is a figure which shows a part of example. Q ₁₁ to _{Q 16} ... transistor, Q ₁₈ , Q ₂₂ ... transistor, 21 ... phase shift circuit, 23, 24, 2
5...Current mirror circuit, I _S1 , I _S2 ...Current source.

Claims (1)

[Claims] 1. The emitters of the first, second, and third transistors are connected to a first current source, and the emitters of the fourth, fifth, and sixth transistors are connected to a second current source. , the collectors of the first and sixth transistors are connected to a power supply line, and the first input signal superimposed on the first DC bias, the second and fourth input signals are applied between the bases of the first and sixth transistors. a second input signal superimposed on the first DC bias to a common base of the transistor; and a second input signal superimposed on the first DC bias to the common base of the third and fifth transistors; 1. A phase processing circuit characterized in that a difference between outputs of a common collector of a fifth transistor and a common collector of a third and fourth transistor is derived from an output circuit. 2. The first input signal is an input FM signal,
2. The phase processing circuit according to claim 1, wherein the second input signal is a signal obtained by passing this input FM signal through a phase shift circuit. 3. The output circuit includes a first current mirror circuit connected to a common collector of the second and fifth transistors, and a second current mirror circuit connected to a common collector of the third and fourth transistors. and a third current mirror circuit, in which the output of the first or second current mirror circuit is applied to the input terminal, and the output of the second or first current mirror circuit is applied to the output terminal.
2. The phase processing circuit according to claim 1, wherein the phase processing circuit is a current mirror circuit.