JPS6311690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing signal generation control circuit. An example of a system that performs control by creating a plurality of types of timing signals controlled by a clock is a storage device.

As a conventional technique, a storage device that performs an interleaving operation will be described as an example.

FIG. 1 is a block diagram of a storage device that performs an interleaving operation. In the figure, L is a logic section, and M0 to Mi
is a storage unit, and MGO0 to MGOi are activation signals.

The logic section L is a section that performs high-speed access control, and the storage sections M0 to Mi are composed of random access memories (RAMs), for example, and are sections that operate independently at relatively low speeds. The logic section L operates in synchronization with a high-speed clock whose clock cycle is 1τ, and as shown in the time chart shown in FIG.
The configuration is such that the activation signal (MGO0 to MGOi) can be freely output at 1τ intervals as long as the cycle time of the two storage units is maintained. In Figure 1, MGO0
Although it is shown that MGOi is output sequentially from 1 to 3, the activation signal output in a certain clock cycle can be output to any memory unit as long as it is not output to two or more memory units at the same time. It is.

On the other hand, in the storage units M0 to Mi that have received the activation signal, the activation signal is sent to operate the RAM.
It is necessary to create various timing signals, such as a row address strobe (RAS) signal or a column address strobe (CAS) signal, at predetermined time intervals based on MGO0 to MGOi. Conventionally, for this purpose, a plurality of timing signals have been created using a delay line or the like, but this has disadvantages such as an expensive circuit.

Next, as the configuration of the timing generation circuit, a timing generation circuit using a shift register is shown in FIG. 3, and a time chart is shown in FIG. 4. In FIG. 3, assuming that the memory sections M0 to Mi operate in synchronization with the clock cycle (lτ) of the logic section L, the activation signal MGO0 from the logic section L is composed of flip-flops (FF) 50 to 56. The output of each flip-flop is shifted by 1τ at the output of each flip-flop. As a result, FF50
The JK flip-flop (FF) 60 is set by the output of the FF 55 (shift signal A), and reset by the output of the FF 55 (shift signal D).

The output of this J-KFF60 is supplied as the RAS signal of RAM70, and the output of J-KFF61 is similarly supplied.
The memory is operated by supplying it as a CAS signal.

When creating a timing signal using a shift register as described above, a logic element that operates at high speed in synchronization with the clock cycle (1τ) of the logic section L is required, which has the disadvantage of being expensive. Ta.

Further, FIG. 5 shows a timing generation circuit in which the logic section and the storage section operate at different clock cycles, which should eliminate the drawbacks of the timing generation circuit shown in FIG. 3, and FIG. 6 shows a time chart. In FIG. 5, it is assumed that the logic section L operates with a clock with a clock cycle of 1τ, and the memory sections M0 to Mi operate with a clock of 3τ. ) 80~
Shift register consisting of 82 and J-
The KFF 83 creates and outputs a timing signal required by the RAM 70, such as a RAS signal. However, as shown in the time chart shown in FIG.
There is a delay of 3τ until the signal is output, which is a delay of 2τ compared to the circuit shown in FIG.
Furthermore, it is output on the first clock cycle.
For MGO2, there was a delay of 2τ until the RAS signal was output, and it was output in the second clock cycle.
There is a delay of 1τ for MGO1, and the delay until the output of the required signal changes depending on the clock cycle in which the activation signal is applied, and the output of the required signal is performed in units of 3τ, so there is a narrow timing. It was impossible to create.

Although the present invention is not limited to storage devices, it is an object of the present invention to receive an activation signal generated at an arbitrary timing and efficiently generate various timing signals at predetermined times, and for this purpose, the timing according to the present invention The signal generation control circuit generates N clocks each having a period N times the basic period τ and whose phase difference is sequentially shifted by 1τ, and receives an external activation signal at the time of occurrence of any of the N clocks. a starting signal identifying circuit that identifies whether the starting signal has been received first; a used clock determining circuit that determines which of the N clocks to use based on the output of the starting signal identifying circuit; A clock selection circuit that selects a desired clock from the N clocks based on the output, and a timing signal generation circuit that generates a plurality of timing signals based on the clock selected by the clock selection circuit. It is characterized by

The present invention will be explained below with reference to the drawings.

FIG. 7 is a circuit configuration diagram of an embodiment according to the present invention, in which 1 to 7 are D-type flip-flops (FF), 10 to 12 are JK flip-flops (FF), and 20 to 30 are gates. , 40 is a selection circuit which is a collection of gates, MGO0 is a start signal, CLK
0 to CLK2 are clocks, CEND is the output of flip-flop 7, and T1, T2, T3, . . . are required timing signals.

The structure of the storage device is the same as that shown in FIG. 1, and the embodiment shown in FIG. This is an example.

FIG. 8 is a diagram showing a time chart of the embodiment shown in FIG.

The operation of the embodiment is as follows.

In Figure 7, the clock (CLK0 to CLK2)
is the clock (CLKL) of logic section L (shown in Figure 1)
It has a period three times the clock period 1τ of logic part L, and as shown in FIG.
1 and CLK2 are out of phase with CLK0 by 1τ and 2τ, respectively. Note that the period of the clock used in this timing signal generation control circuit is determined by the operating speed of the logic elements in the memory sections M0 to Mi. Now, assume that the activation signal MGO0 is output from the logic section L to the storage section M0 at the timing shown in FIG. The activation signal MGO0 issued from the logic block L at the 0th clock of CLKL is turned FF by CLK0.
It is set to 1, and the output of FF1 is further set to FF10 by CLK2. The outputs of FF1 and FF10 are logically ORed at gate 23 and input to gate 26 of clock selection circuit 40. gate 2
3, the clock selection circuit 40 selects CLK0.
is selected and CLK0 is supplied to the shift register composed of FF4 to FF7. Also, the MGO0 signal set to FF1 is passed through OR gate 3,
Input to FF4. As a result, since FF4 is supplied with CLK0 by the clock selection circuit 40, signals T1 to T3 shown in FIG. 8 are output. Using these T1 to T3 signals, a timing signal required for the RAM is created, for example, similar to the circuit shown in FIG.

Next, for example, if the activation signal MGO0 is output at the first clock of CLKL with a delay of 1τ from the timing shown in FIG.
1 is selected and CLK1 is supplied as the shift register clock.

In this way, the phase of the clock at which the start signal MGO0 is first received is identified, and the clock selection circuit 40 supplies the shift register, which is a timing generation circuit, with a clock having the same phase as the first clock received. Start signal by
Even if MGO0 is sent at any timing (however, the phase shift is an integer multiple of 1τ), the activation signal MGO0
It is possible to generate a predetermined timing at a certain time from . Also, by changing the combination of inputs to the clock selection circuit 40 and creating a clock that is shifted by 1τ or 2τ with respect to the clock that receives the activation signal MGO0, timing signals with fine time intervals can be created as desired.

In addition, in FIG. 7, the gates 20 to 22 are
This is provided to prevent the corresponding flip-flop from being set by a clock other than the clock that first received the activation signal when the activation signal MGO0 has a width of 1τ or more. For example, looking at the time chart shown in Figure 6, after MGO0 turns on (“1”), FF1 is set at the trailing edge of -CLK0, and as a result, the Q output of FF1 becomes “0” and this Q The gate 21 outputs “0” due to the output “0”.
FF2 is not set at the trailing edge of CLK1.

Also, the cycle end signal which is the output of FF7
CEND is a signal that is output when all predetermined timings of the memory unit M0 are output and the operation of one memory cycle is completed. This signal resets the J-KFFs 10-12, and furthermore, the clock selection circuit 40 stops sending out the clock.
As a result, it becomes possible to receive the next activation signal MGOi.

As explained above, according to the present invention, a plurality of clocks having a longer period than the fundamental period are used, and
Since the clock that has received the activation signal is identified and the clock to be used is then determined and selected, it is possible to configure the circuit with logic elements that are relatively slower than conventional circuits, and also to It is possible to accurately deal with the activation signal sent out at the timing of , and the effect is extremely large.

[Brief explanation of the drawing]

Figure 1 is an example of the configuration of a storage device, Figure 2 is an example of a time chart of a conventional circuit, Figure 3 is an example of the configuration of a timing generation circuit using a shift register, and Figure 4 is an example of a timing generation circuit using a shift register. An example of a time chart, FIG. 5 is a configuration example of a timing generation circuit operating in different clock cycles, FIG. 6 is an example of a time chart in different clock cycles, and FIG. 7 is a circuit configuration diagram of an embodiment according to the present invention.
FIG. 8 is a diagram showing a time chart of the embodiment. In FIG. 7, 1 to 7 are D type flip-flops, 10 to 12 are JK flip-flops,
20 to 30 are gates, 40 is selection circuit, MGO0
is the start signal, CLK0 to CLK2 are the clocks, T1
~T3 is a timing signal.

Claims (1)

[Claims] 1 N clocks each having a period N times the fundamental period τ and having a phase difference of 1τ are generated, and at which of the N clocks an external activation signal is first received. a starting signal identifying circuit for identifying whether a clock has been used, a clock determining circuit for determining which of the N clocks to use based on the output of the starting signal identifying circuit, and a clock determining circuit for determining which of the N clocks to use based on the output of the clock determining circuit for A clock selection circuit that selects a desired clock from the N clocks using the clock selection circuit, and a timing signal generation circuit that generates a plurality of timing signals based on the clock selected by the clock selection circuit. Timing signal creation control circuit.