JPS6311701B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides for a predetermined gate circuit of a device under test.
This invention relates to an improvement in the scan-in control circuit of a test device that checks scan-in, clock increment, and scan-out operations.

(2) Prior art and problems Conventionally, a scan-in signal is applied from a test device to a gate circuit at a predetermined address, such as a flip-flop (FF), in a device under test such as a computer system, and after a predetermined clock increment, a scan-out signal is applied. The operation is checked by receiving a signal. This scan-in function allows FF with the function to set the opposite value of the reset value, that is, the value determined by scan-in or reset.
When attempting to set an arbitrary value to the FF, it is necessary to check the output value of the FF or the operation of the FF after resetting. Of course, it is possible to use a circuit configuration that allows the FF to perform both 0 and 1 scan-in operations, but changing the circuit of the device under test is undesirable both in terms of configuration and cost.

(3) Purpose of the Invention The purpose of the present invention is to provide a scan-in control circuit that can simplify the steps without changing the circuit of the device under test when performing a scan-in operation of a predetermined gate circuit of the device under test and setting an arbitrary value. It is to provide.

(4) Structure of the Invention In order to achieve the above object, the scan-in control circuit of the present invention is a scan-in control circuit of a test device that checks scan-in, clock increment, and scan-out operations for a predetermined gate circuit of a device under test. In addition to the scan-in control section and the scan-out control section, a scan-in arbitrary value setting circuit for simultaneously controlling both control sections is provided, and the output value of the gate circuit of the device under test selected by the scan-out control section is The present invention is characterized in that the scan-in control section performs the scan-in operation only when the scan-in arbitrary value is different from the set arbitrary scan-in value.

(5) Embodiments of the invention Since the scan-in function is generally used during maintenance, the present invention provides a test device with a scan-in control section and a scan-out control section, as well as an arbitrary value scan-in control circuit that controls both at the same time. It is something. This allows you to set the FF after resetting any value without changing the circuit of the device under test.
This allows you to set the output value without being conscious of it.

The figure is a configuration explanatory diagram of an embodiment of the present invention.

In the figure, an address (ADD) and scan-in (Sin) are input from the scan-in control unit 30 in the test device 20 to the representative FF ₁₁₁ in the device under test 10, and an output value (SCAN) is sent out. , are returned to the test apparatus 20 together with the output values of each FF 11 ₂ , 11 ₃ , and are selected by the scan-out control section 26 in the FF output address selection circuit 27 . In the present invention, an arbitrary value scan-in setting circuit 25 is provided which can set an arbitrary value of 1/0 in order to control both control sections simultaneously.

The arbitrary value scan-in signal stored in the register 21 is input to the AND circuit 29 through the EOR circuit 28 together with the FF output value selected by the FF output address selection circuit 27. Further, the instruction code stored in the register 22 is decoded by the decoder 24, and the scan-out (Sout) instruction is sent to the scan-out control section 26 together with the address from the register 23. Further, the arbitrary value scan-in (FSin) command is sent to the arbitrary value scan-in setting circuit 25, the set arbitrary value scan-in signal is sent to the scan-out control section 26, and scan-out control is performed in response to the scan-in signal. Also, the AND circuit 29 takes the AND of this scan-in signal and the output of the EOR circuit 28.
It is input to the scan-in control unit 30 together with the address of the register 23.

With the above configuration, when an arbitrary value scan-in (FSin) command arrives, the arbitrary value to be scanned in and the FF selected by the scan-out control section are
11 The output value of ₁ is input to the EOR circuit 28, and if the values are the same, the output will be "0", so AND29
Since there is no output, the FSin instruction ends. if,
If a different value is input to the EOR circuit 28, the output will be "1", so the AND circuit 29 passes an arbitrary value scan-in signal and inputs it together with the address to the scan-in control unit 30, and a scan-in operation is performed for the FF ₁₁₁ . The same operation can be performed for the reset (RS) signal of _FF111 .

(6) Effects of the Invention As explained above, according to the present invention, by providing a test device with an arbitrary value scan-in control circuit that simultaneously controls a scan-out control section and a scan-in control section, a predetermined gate circuit of a device under test can be controlled. can be set to any value. in this case,
The procedure is extremely simple, as the circuit of the device under test does not need to be changed in any way, and only a few configurations are added to the test device.

[Brief explanation of the drawing]

The figure is a configuration explanatory diagram of an embodiment of the present invention, in which 10 is a device under test, ₁₁₁ is a flip-flop (FF), 20 is a test device, 21, 22, 23 are registers, 24 is a decoder, and 25 is an arbitrary number. 2 is a value scan-in setting circuit; 26 is a scan-out control section;
7 is an FF output address selection circuit, 28 is an EOR circuit, 29 is an AND circuit, and 30 is a scan-in control section.

Claims (1)

[Claims] 1 In the scan-in control circuit of the test equipment that checks the scan-in, clock advance, and scan-out operations for a predetermined gate circuit of the equipment under test, in addition to the scan-in control section and the scan-out control section, it is possible to control both control sections simultaneously. A scan-in arbitrary value setting circuit is provided, and the scan-in operation is performed by the scan-in control section only when the output value of the gate circuit of the device under test selected by the scan-out control section differs from the set scan-in arbitrary value. A scan-in control circuit characterized in that: