JPS6311880B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a drive circuit for a pulse motor of a pointer type electronic timepiece.

As electronic watches have become more widespread, users have begun to desire watches with lower current consumption and longer battery life, and various measures have been taken to reduce current consumption. As a result, the current consumption of clock LSIs has recently come to be on the order of several hundred nanoamperes, but this is still not completely satisfactory, and we have been working on creating electronic clocks with even longer lifespans. It has become necessary to consider ways to reduce current consumption in even more detailed areas.

Among these, the magnitude of the through-current in the output buffer that constitutes the drive circuit that drives the pulse motor has become something that cannot be overlooked.

The output buffer of conventional drive circuits consists of a simple inverter configuration, and when the input signal rises and falls, the inverter's P-channel type
Because there is a period when the MOS transistor and the N-channel MOS transistor are in the ON state at the same time,
A through current flows, wasting power and significantly shortening the life of the battery. In addition, as a conventional means for reducing the through current of the inverter buffer, a P channel of the inverter buffer has been used.
MOS transistor gate input and N channel
Separately from the gate input of the MOS transistor, the phase of the pulse input to the gate of the N-channel MOS transistor is changed and shortened by an integrating circuit using a resistor and a capacitor for the pulse input to the gate of the P-channel MOS transistor. In this way, a P-channel MOS transistor and an N-channel MOS transistor can be operated at the same time.
We tried to prevent through current from flowing by not turning it on, but in LSI, the precision of building resistors and capacitors varies widely, and the time constant of the integrating circuit is not fixed, so the gate of the P-channel MOS transistor The difference between the pulses applied to the input and the gate input of the N-channel MOS transistor disappears, causing a through current to flow, or the difference between the pulses applied to the gate input of the P-channel MOS transistor and the gate input of the N-channel MOS transistor increases. If the circuit becomes too large, an open state may appear in the output of the buffer, and it contains extremely unstable elements, making it unsatisfactory as a drive circuit for preventing through current.

In order to eliminate the above-mentioned drawbacks, an object of the present invention is to provide a memory control circuit that receives an output signal from a waveform shaping circuit and determines the polarity of alternating pulses to be applied to the coil of a pulse motor, and each of the memory control circuits. A pair of feedback delay circuits that receive an output signal as input, and a P-channel MOS transistor and an N-channel MOS transistor that receive signals from the pair of feedback delay circuits, respectively, and are controlled independently from each other. The feedback delay circuit includes a P-channel MOS transistor and an N-channel MOS transistor constituting the buffer.
By configuring the MOS transistors to prohibit conduction at the same time, the pulse motor eliminates the through current of the output buffer of the pulse motor drive circuit, reduces wasteful current consumption, and achieves an electronic clock with a long battery life. The purpose of the present invention is to provide a drive circuit for the following.

Embodiments of the present invention will be described below based on the drawings.
FIG. 1 is a circuit block diagram of the electronic timepiece of the present invention, and FIG. 2 is a diagram of main voltage waveforms in FIG. 1.

1 is an oscillation circuit that outputs a 32kHz signal using a crystal resonator as a time reference source. 2 is a frequency dividing circuit, which receives the oscillation signal from the oscillation circuit 1 and divides the frequency into 1.
Outputs a frequency-divided signal of Hz. 3 is a waveform shaping circuit which inputs the 1 Hz frequency divided signal from the frequency dividing circuit 2 and outputs a waveform shaped signal _P1 .

Reference numeral 4 denotes a drive circuit, which includes a storage control circuit 5, feedback delay circuits 6 and 7, and output buffers 24 and 25 each consisting of a P-channel type MOS transistor and an N-channel type MOS transistor. Binary flip-flop 5a (hereinafter referred to as binary FF) of storage control circuit 5 of drive circuit 4
The input terminal φ of the binary FF 5a is connected to the output of the waveform shaping circuit 3, and the output terminal Q and the inverted output terminal of the binary FF 5a are each connected to one of the input terminals of the AND gates 5b and 5c, and ,
The other input terminals of the AND gates 5b and 5c are connected to be supplied with the signal _P1 of the waveform shaping circuit 3.

The output terminals of the AND gates 5b and 5c output 1/2 Hz memory control signals P ₂ and P ₃ , and the output terminal of the AND gate 5b is connected to the feedback delay circuit 6.
It is connected to one input terminal of the NOR gate 8 and the NAND gate 12.

The output terminal of the NOR gate 8 is connected to the inverter 9,
10 and 11, the P channel type MOS transistor 24a of the buffer 24 (hereinafter referred to as P-MOS
It is connected to the gate terminal of the transistor (abbreviated as Tr), and
It is connected to the other input terminal of the NAND gate 12.

The output terminal of the NAND gate 12 is connected to the NAND terminal of the buffer 24 via inverters 13, 14, 15.
Channel type MOS transistor 24b (hereinafter referred to as N-
It is connected to the gate terminal of a MOS Tr (abbreviated as MOS Tr), and is also connected to the other input terminal of the NOR gate 8.

In this embodiment, the feedback delay circuit 7
NOR gate 8 and three inverters 9, 10, 1
1 constitutes an OR gate means, and a NAND gate 12 and three inverters 13, 14, 15 constitute an OR gate means.
It constitutes an AND gate means.

The output terminal of the AND gate 5c of the storage control circuit 5 is connected to the NOR gate 1 of the feedback delay circuit 7.
6 and one input terminal of the NAND gate 20. The output terminal of the NOR gate 16 is connected to the gate terminal of the N-MOS Tr 25a of the buffer 25 via inverters 17, 18, and 19, and is also connected to the other input terminal of the NAND gate 20. The output terminal of the NAND gate 20 is connected to the inverters 21, 22,
23 to the N-MOS Tr of the buffer 25.
25b and the gate input terminal of the
It is connected to the other input terminal of NOR gate 16. Further, drive pulses from the output terminals of the buffers 24 and 25 are output to terminals A and B of the drive circuit 4, respectively. 26 is a pulse motor drive coil connected between terminals A and B.

Next, the operation in the above configuration will be explained. The waveform shaping circuit 3 receives the oscillation signal from the oscillation circuit 1 and outputs a 1Hz frequency divided signal.The waveform shaping circuit 3 outputs a waveform shaped signal _P1 as shown in FIG. The signal is output and input to the storage control circuit 5 of the drive circuit 4.

The waveform shaped signal _P1 is input to the binary FF5a of the storage control circuit 5, so that it is converted into a binary signal.
The FF 5a performs a frequency dividing operation, and 1/2 Hz signals having mutually opposite phases are outputted from the output terminal Q and the inverted output terminal. When the waveform shaping signal P ₁ is input in a state where "H" level signals are alternately output to the output terminal Q and the output terminal by the 1/2 Hz output of the binary FF 5a, the AND gate 56
And the AND gate 5c outputs storage control signals _{P 2} and _{P 3} alternately every second as shown in FIG.
The polarity of the drive pulse applied to the pulse motor coil is determined depending on whether the pulse motor coil is output.

When the storage control signal _P2 is output as an "H" level signal, it is input to the NOR gate 8 of the feedback delay circuit 6, and the output of the NOR gate 8 is driven to "L".
level signal. The NOR gate 8 is “L”
When the level is reached, the inverters 9, 10, 11
P-MOS Tr24 of the buffer 24 via
As shown in Figure 2D, the gate of a has a storage control signal.
_P2 changes from “L” level to “H” level at time t ₀ and becomes “H” at time t ₁ after a delay of t ₁ - t ₀ .
A signal _P4 having a level is applied to the P-MOS
Tr24a is turned off. At the same time, the output signal of the inverter 11 takes the "H" level.
Since P ₄ is input to the other input terminal of the NAND gate 12 which is waiting to receive the storage control signal P ₂ at the "H" level, the output terminal of the NAND gate 12 receives the "L" level signal. Output.
When the output of the NAND gate 12 becomes "L" level, the inverters 13, 14, 15
N-MOS Tr24 of the buffer 24 via
The gate input of b is a P-MOS Tr as shown in Fig. 2 (e).
From t ₁ when 24a becomes “H” level, t ₂ −t ₁
A signal _P5 which becomes "H" level from time _t2 after a delay of time is applied, and the N-MOS Tr24b
is in the ON state.

Therefore, the P-MOS Tr24 of the buffer 24
Time _t1 when a is turned off and N-MOS Tr2
The time t ₂ when 4b is turned on is NAND1
2. There is a delay time t ₂ −t ₁ for the signal P ₄ to pass through the inverters 13, 14, and 15, and P−
Since it is prohibited for MOS Tr24a and N-MOS Tr24b to be in the ON state at the same time, in this embodiment, the power is connected to the drain and source of N-MOS Tr24b via the source and drain of P-MOS Tr24a as in the conventional case. This prevents the phenomenon of through current flowing.

Also, from time _t2 when the N-MOS Tr24b turns ON, the output of the buffer 24 changes from "H" level to "L" level as shown in FIG. signal is output.

Moreover, at this time, the signal P ₃ from the memory control circuit 5
is at the "L" level, the output signals P ₆ and P ₇ of the feedback delay circuit 7 are both at the "L" level, and furthermore, these signals P ₆ and P ₇ cause the P-MOS Tr
25a is ON state, N-MOS Tr25b is OFF
state, and the terminal B of the buffer 25 outputs “H”.
A level output signal will be output.

Therefore, the pulse motor coil 26 is connected to terminal B.
A drive current flows from the terminal A toward the terminal A, driving the pulse motor.

Then, the storage control signal P ₂ is changed to t ₃ in FIG.
When the output of the NAND gate 12 becomes "L" level at the time of "H" level, the N-MOS
As shown in Fig. 2 E, the gate input of Tr24b is as follows.
Signal P ₂ changes from “H” level to “L” level t ₃
A signal _P5 which becomes "L" level at time _t4 after a delay of time t4 _{- t3} is applied to the N-MOS.
Tr24b is turned off. At the same time, the signal P ₅ which has become "L" level is input to the other input terminal of the NOR gate 8 whose one input terminal is set to "L" level by the storage control signal P ₂ . The output terminal of is set to "H" level. Moreover, when the output of the NOR gate 8 becomes "L" level, the inverters 9, 10, 1
1 of the buffer 24 through P-MOS Tr2 of the buffer 24.
The gate input of 4a is N- as shown in Figure 2D.
A signal _P4 that goes to the "L" level is applied from the time _t5 , which is delayed by the time _t5 - _t4 from the time _t4 when the MOS Tr24b is turned off, and the P-MOS
Tr24a is turned on. Therefore, the memory control signal
Even at time _t3 when _P2 changes from “H” level to “L” level, P-MOS Tr24a and N-MOS Tr24
b will operate without being in the ON state at the same time, that is, without any through current flowing.
The output terminal A of the buffer 24 outputs an "H" level signal to the terminal A from time _t4 . Moreover, since the signal P ₃ from the storage control circuit 5 is at the "L" level at this time, the output signals P ₆ and P ₇ of the feedback delay circuit 6 are both at the "L" level, and this signal P-MOS25a by P ₆ and P ₇
is in the ON state, and the N-MOS Tr 25b is in the OFF state, so that an "H" level output signal is output from the terminal B of the buffer 25. Therefore, since "H" level signals are applied to both terminals B and A of the pulse motor coil 26, no current flows and the pulse motor stops.

Similarly, in response to a storage control signal P ₃ as shown in FIG. 2C outputted from the storage control circuit 5, the feedback delay circuit 7 outputs a buffer input signal P ₆ having a different phase as shown in FIGS. , P ₇ are output, and the buffer 25 is connected to the second circuit without through current flowing
As shown in the figure, an "L" level drive pulse is output to the output terminal B. Moreover, since the signal P ₂ from the storage control circuit 5 is at the "L" level at this time, the output signals P ₄ and P ₅ of the feedback delay circuit 6 are both at the "L" level, and Signal P ₄ ,
Due to _P5 , P-MOS Tr24a is in ON state, N-
MOS Tr24b becomes OFF state, buffer 2
An "H" level output signal is output from terminal A of No. 4.

Therefore, the pulse motor coil 26 is connected to terminal A.
A drive current flows from the terminal toward terminal B to drive the pulse motor.

As described above, the present invention determines the polarity of the alternating pulses applied to the pulse motor coil by using the 1Hz signal from the waveform shaping circuit as input, based on the flow of the through current of the output buffer in the drive circuit for driving the conventional pulse motor. A pair of feedback delay circuits receives the output signal from the storage control circuit and inputs signals of different phases from the feedback delay circuits, respectively.
The MOS Tr and N-MOS Tr are controlled independently, and the P-MOS Tr and N-MOS Tr are prevented from operating at the same time by using a delayed input signal to prevent through current by using only logic elements. This eliminates wasted current consumption. Furthermore, when a large number of signals are applied per second such as chopper drive, current consumption can be particularly reduced, which is extremely effective in providing an electronic timepiece with a long battery life.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of the electronic timepiece of the present invention, and FIG. 2 is a diagram of main voltage waveforms in FIG. 1. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Frequency division circuit, 3... Waveform shaping circuit, 4... Drive circuit, 5... Memory control circuit, 6, 7... Feedback type delay circuit, 24, 25...
Batsuhua, 26... Coil for pulse motor.

Claims (1)

[Claims] 1 An oscillation circuit using a crystal oscillator as a time reference source,
A frequency dividing circuit which inputs the frequency divided signal from the oscillation circuit, a waveform shaping circuit which receives the frequency divided signal from the frequency dividing circuit and outputs a predetermined pulse signal, and an output signal from the waveform shaping circuit. In an electronic watch equipped with a drive circuit for driving a pulse motor as an input, the drive circuit has a memory control function that uses an output signal from a waveform shaping circuit as an input to determine the polarity of alternating pulses applied to the coil of the pulse motor. circuit, a feedback delay circuit that receives each output signal of the storage control circuit as input, a P channel type MOS transistor that receives the signal from the feedback delay circuit, and an N
Each gate of a channel type MOS transistor is provided with a buffer that is independently controlled, the feedback type delay circuit and the buffer have a pair each corresponding to the output terminal of the coil, and the feedback type delay circuit has one pair of OR gate means having an input terminal input with the output signal of the storage control circuit and an output terminal connected to the gate of the P-channel type MOS transistor; The N-channel type
It consists of AND gate means connected to the gate of the MOS transistor, and the output signal of the OR gate means is feedback connected to the other input terminal of the AND gate means, and the output signal of the AND gate means is connected to the other input terminal of the AND gate means. A pulse motor drive circuit for an electronic watch, characterized in that the circuit is feedback-connected to the other input terminal of the OR gate means.