JPS6312287B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input circuit for a CMOS type integrated circuit.

Conventionally, CMOS inverters have been used to transmit external signals sent from a bus to internal circuits made of integrated circuits.

In an external data bus circuit that interconnects integrated circuits and has a high impedance state, the input circuit
In the case of a CMOS inverter, it is necessary to take measures to prevent gate floating even in a high impedance state in order to prevent gate floating due to a high impedance state and malfunction due to through current.

FIG. 1 is a block diagram of an example of a conventional integrated circuit input circuit.

The integrated circuits 10, 10', 11 are interconnected by a bus 1, and a signal from the integrated circuit 10 or 10' is input from the output inverter 2 or 2' to the inverter 3 of the integrated circuit 11 via the bus 1. Bus 1 is designed to prevent the input of input inverter 3 from becoming gate floating even if both inverters 2 and 2' stop driving and the bus is in a high impedance state.
A pull-up resistor 4 was added to determine the signal level.

FIG. 2 is a block diagram of another example of a conventional integrated circuit input circuit.

In this example, a pull-up resistor is provided within the integrated circuit 11, and other aspects are the same as shown in FIG.

As shown in FIG. 1, when the pull-up resistor 4 is provided outside the integrated circuit, the number of parts increases, and the second
When a pull-up resistor is provided in an integrated circuit as shown in the figure, there is a drawback that current consumption increases because direct current may constantly flow through the pull-up resistor 4.

The present invention eliminates the above-mentioned drawbacks, does not use pull-up resistors, and does not allow steady DC current to flow.
The present invention provides an input circuit for a CMOS integrated circuit that can determine the bus level.

The input circuit of the CMOS type integrated circuit of the present invention is connected to a bus to which at least one integrated circuit having an output inverter is connected, and transmits an external signal output from the output inverter to the internal circuit. Both have one CMOS type inverter and a drive capacity smaller than the output inverter and the output inverter.
It is configured to include an additional CMOS type inverter that inputs a part of the output of the CMOS type inverter and inputs the output to the input terminal of the CMOS type inverter to apply positive feedback.

Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention.

Bus 1 is driven by output inverters 2, 2', and the signals of integrated circuits 10, 10' are transferred to integrated circuit 11.
is input to the input inverter 3. In this invention, a feedback inverter 5 is added, and a part of the output of the input inverter 3 is input to the feedback inverter 5,
An input circuit is configured by connecting the feedback inverter 5 so that its output is input to the input inverter 3.

Next, the operation of this embodiment will be explained. First, integrated circuit (hereinafter referred to as IC) 10 or 1
Consider the case where information of 0' is transmitted to the IC 11.

The output inverter 2 or 2' drives the bus 1, and the input inverter 3 receives the potential (information) and takes it into the IC 11. At this time, competitive driving occurs between the output inverter 2 or 2' and the feedback inverter 5, but if the driving capacity of the output inverter 2 or 2' is made several times larger than that of the feedback inverter 5, the above competition occurs. However, the driving ability of output inverter 2 or 2' is always superior, and IC1
0 or 10' information is correctly transmitted. This competitive drive ends in an instant due to the positive feedback loop, and since the output potential of the feedback inverter 5 and the output potential of the output inverter 2 or 2' are both the same, no steady DC current flows. Therefore, there is no increase in power consumption due to the addition of the feedback inverter 5.

Next, consider a case where both output inverters 2 and 2' stop driving, that is, a case where the output inverters 2 and 2' are about to become high impedance. At this time, the transmission information immediately before the high impedance is held in a positive feedback holding circuit composed of the output inverter 3 and the feedback inverter 5, and its contents are output to the bus 1 through the feedback inverter 5. Therefore, even if both output inverters 2 and 2' stop driving, the bus line 1 does not go into a high impedance state and its potential is determined. Therefore, the input of the input inverter 3 never becomes gate floating, and malfunction does not occur.

As explained in detail above, according to the present invention,
Bus level can be determined without using pull-up resistors and without constant DC current flowing.
The effect is great because an input circuit for a CMOS type integrated circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of an input circuit of a conventional integrated circuit, FIG. 2 is a block diagram of another example of an input circuit of a conventional integrated circuit, and FIG. 3 is a block diagram of an embodiment of the present invention. be. 1... Bus, 2, 2'... Output inverter, 3
...Input inverter, 4...Pull-up resistor, 5
...Feedback inverter, 10, 10', 11... integrated circuit.

Claims (1)

[Claims] 1. at least one CMOS inverter connected to a bus to which at least one integrated circuit having an output inverter is connected and transmits an external signal output from the output inverter to an internal circuit;
and an additional CMOS type inverter having a smaller driving capacity than the output inverter and inputting a part of the output of the CMOS type inverter and inputting the output to the input terminal of the CMOS type inverter to apply positive feedback. An input circuit of a CMOS type integrated circuit featuring: