JPS6312418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission line tracer that sequentially stores line information in the order of occurrence in a transmission system for troubleshooting when an error occurs, collecting statistical information, and the like.

More specifically, it relates to a method of storing traced information.

First, an example of a transmission system to which the present invention is applied will be explained using FIG. 1.

Figure 1 shows a typical loop transmission system, which consists of computers, terminals, and other information devices IDi (i=
0, 1,...n) are usually connected in a loop through one transmission line TL to form one distributed processing system. Each information device IDi is a corresponding transmission station
Join the loop transmission system via STi (i=0, 1, . . . n). One of the transmission stations is responsible for monitoring and controlling the entire loop, and is called a supervisory control station. ST ₀ is the supervisory control station in this case.

FIG. 2 shows an example of a transmission control method in the loop transmission system shown in FIG. Supervisory control station
ST ₀ sends out a polling signal POL to check if there is a station requesting transmission in the system. A transmission station with no transmission request ignores the detection of the signal and simply passes the received information to the transmitting side. For this reason, the polling signal
POL goes around the loop and returns to supervisory control station ST ₀ ,
This process is repeated until there is a station requesting transmission. At this time, if a transmission request is issued from the transmission station ST ₁ to the transmission station ST _o , the transmission station ST ₁ transmits the data frame DATA without passing the polling signal. Time fill signal indicating that there is no information after transmission is complete
Waits for a response from the other station while sending a TF. Transmission station that received the data frame DATA addressed to its own station
ST _o sends a response to this as a response frame RESP to transmission station ST ₁ . After receiving a normal response and completing transmission, the transmission station ST ₁ sends out a polling signal POL and relinquishes the right to transmit. Here the data frame DATA and response frame RESP are both
Frame formats that comply with HDLC (High Level Data Link Control) procedures are often adopted, and the polling signal POL consists of a unique bit pattern that does not appear in the frame information mentioned above.
Further, the time fill information TF is normally selected as a series of "0" bits or flag information "F". Third
The figure shows an example of the format of the frame information mentioned above. In the figure, F is a flag pattern indicating a frame division. Further, the FCS immediately before the flag F in the latter stage is frame check information and is used for error detection when an error occurs in the information surrounded by the flag F.
After the pre-stage flag F, the destination address DA, control information C regarding frame transmission and reception, and transmitting station address SA follow in this order. data frame DATA
Then, this is followed by data information I, which is a response frame.
In RESP, response information ANS is attached. Generally, the data information I has a variable length, but the response information ANS has a fixed length.

Nowadays, in response to requests for processing decentralization, higher functionality, and larger capacity, recent loop transmission systems tend to increase transmission speed, increase data frame length, and improve network reliability. Introducing optical fibers into transmission lines, microprocessors, and other various
The increased speed of LSI makes it possible to achieve the above items.

When an error occurs in the above-mentioned transmission system and the cause is to be investigated, conventionally the cause of the error is inferred based on various error accumulation information and processing status left at each transmission station, and then an online scope or logic scope is used to investigate the cause of the error. A method was used to confirm this. Since this method traces all line bit information, it requires equipment such as a high-speed, large-capacity online scope, and the ability to detect the line status is poor, making it difficult to save information where it is truly needed. The disadvantage is that it takes a very long time to investigate the cause.

In order to overcome this drawback, the following requirements must be met.

(1) Compress and trace only the necessary information rather than all line bit information.

(2) Detect the occurrence of any specified line state and save the current trace state.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for storing transmission line information that facilitates the detection of line failures.

The present invention is characterized by detecting preset transmission line information (hereinafter referred to as event factor) and the number of transmission line information received after detecting the event cause (hereinafter referred to as the number of event occurrences). This means that a save timing command is issued.

Examples of the present invention will be described in detail below. FIG. 4 shows a schematic configuration of a supervisory control station _ST0 in a loop transmission system to which the present invention is applied. Transmission line TL _R
The received signal is converted into a digital signal by the receiver 2 and sent to the line control circuit 3. The line control circuit 3 sends this to the line tracing circuit 1 via the reception bit signal line 31, and also sends the received information converted into serial/parallel data to the reception information storage circuit 5 according to a command from the transmission control circuit 6. Further, the information obtained by parallel-serial conversion of the transmission information from the transmission information storage circuit 7 can be used as either the reception bit information from the receiver 2 or the information from the built-in transmission signal generator (not shown). Send to transmitter 4. It also has the function of detecting various transmission control signals and notifying the transmission control circuit 6 of the detection. The transmitter 4 converts the digital signal from the line control circuit 3 into a signal suitable for transmission and sends it to the transmission line _TLS . The transmission control circuit 6 controls the entire transmission system and records error conditions based on the notification of transmission control signal detection from the line control circuit 3, and also has the function of transmitting and receiving data frames with other transmission stations. Furthermore, the line tracing circuit 1 added in the present invention is notified of the transmission control state as described later. The interface control circuit 8 has a function of controlling information exchange between the supervisory control station ST ₀ and the information equipment ID ₀ , and transfers information from the received information storage circuit 5 to the information equipment ID ₀ , and conversely from the information equipment ID ₀ . The information is sent to the transmission information storage circuit 7.
Further, transmission line trace information and trace status notification information from the line trace circuit 1 to the information equipment ID ₀ , and transfer of trace control information from the information equipment ID ₀ to the line trace circuit 1 are also performed through this circuit.

Next, line tracing circuit 1 directly related to the present invention
A more detailed configuration will be explained based on FIG. Line trace information is stored in the trace information storage circuit 15, and the stored information is roughly divided into the following five types. That is, the transmission control information from the transmission control circuit 6, the transmission control trace code from the trace control circuit 12, the information obtained by adding 1 to the count information of the trace information storage circuit 15 by the 1 addition circuit 14, and the information obtained by adding 1 to the count information of the trace information storage circuit 15, and furthermore, the transmission control trace code from the trace control circuit 12. These are line bit information and time fill signal duration information from the duration time counting circuit 17. One of these five pieces of information is selected and taken in by a multiplexer 16 under the control of the trace control circuit 12. Each case will be explained below. For example, the trace control circuit 12 is notified of data frame detection from the transmission control circuit 6 via the bus 60.
outputs a data frame detection code via bus 120, and at the same time multiplexer 16 outputs a control signal via control line 121 to select this code. Subsequently, the destination address DA given from the receiving circuit 5 via the bus 60,
The multiplexer 16 is controlled to take in frame header information such as control information C and source address SA, and this is sent to the trace information storage circuit 15.
to be memorized. Since the subsequent frame information is not related to transmission control, the word count information of the frame counted by the transmission control circuit 6 is taken in to complete tracing for the data frame. On the other hand, as shown in FIG. 2, in a transmission system, the same event is often detected consecutively. As an example, when tracing the polling signal POL when time fill signal tracing is not executed, the same code is stored continuously when there is no transmission request from any transmission station, and depending on the traffic status, the trace area may be filled with just this code. Sometimes it happens. This not only makes it difficult to see the trace information, but also makes it difficult to estimate the cause of the error. In this case, trace the polling signal as follows. When the same event detection circuit 13 detects a polling signal, if the immediately preceding information is not a polling signal, the trace control circuit 12 stores the polling signal code in the trace information storage circuit 15, and then subsequently stores all zero data. Store. This information is a count of the number of consecutive polling signal detections. For polling signals to be detected continuously thereafter, the count information of the number of consecutive polling signal detections stored in the trace information storage circuit 15 is incremented by 1 by the 1 addition circuit 14, and then stored in the original location again.

When tracing the time fill signal, follow the procedure below.

While the time fill signal detection circuit 18 is detecting the time fill signal, the duration time measuring circuit 17
Start. The duration time counting circuit 17 is configured to continue counting time while it continues to receive activation. The trace control circuit 12, which has been notified by the time fill signal detection circuit 18 that detection of the time fill signal has stopped, first sends a time fill signal code to the trace information storage circuit 15, and then sends a time fill signal code to the duration time clock circuit 17. The multiplexer 16 is controlled to send the duration information of the time fill signal stored in the time fill signal.

Information that has lost its significance due to an error is traced as follows. When the line bit error detection circuit 20 detects the occurrence of an error, the error notification line 211 is sent to the trace control circuit 12.
We will notify you of this via. Upon receiving this, the trace control circuit 12 sends the line error code to the trace information storage circuit 15 and then controls the multiplexer 16 to take in the line bit information stored in the line bit information storage circuit 19. A more detailed configuration of the line bit error detection circuit 20 will be described later.

The contents of the trace information storage circuit 15 are configured so that they can be imported into the information device ID ₀ via the interface control circuit 8, and the information device side requests the trace storage control circuit 11 to determine the factors that cause the transition to the trace storage state. It is possible to set the information as follows.
Upon receiving this, the trace storage control circuit 11 compares the correspondence with the transmission control information sent from the transmission control circuit 6, and if a coincidence is established, the trace storage control circuit 11 saves the information immediately or after a certain number of trace events have occurred. 12 to save the current trace information stored in the trace information storage circuit 15. The detailed configuration of the trace storage control circuit 11 will be described later.

An example of the format of the trace information described so far is summarized in FIG.

A is an example of a trace code when a polling signal is detected, and is composed of two words: a polling signal code POL CODE and a continuous detection number count CCNT.

b is for data frame detection and includes data frame code DATA CODE and destination address information DA,
A total of four words are formed: control information C, information related to transmission control such as source address SA, and frame word count WC not related to transmission control.

c shows a trace when a response frame is detected, but since the response frame has a fixed frame length, frame word counting is not necessary. Yotsutte response frame code RESP
CODE, destination address DA, control information C,
It consists of a total of 3 words of byte information for the source address SA and response information ANS.

d is for time fill, and is composed of a time fill signal code TF CODE and a duration count TCNT.

e is the trace information format of the information that caused the error, and is made up of a line error code ERR CODE and line bit information LBIT of a specified number of words.

Next, the configuration of the trace storage control circuit 11 will be explained with reference to FIG. This circuit is for notifying the aforementioned trace control circuit 12 of the occurrence of an event to be saved in order to prevent loss of necessary trace information, and its function is to detect the occurrence of an event after detection. It is roughly divided into two parts: a storage notification section that counts the number of traces, and issues a trace storage notification when a certain number is counted. The information set from the information equipment side to the trace storage control circuit 11 via the interface control circuit 8 includes the event to be detected and the number of events that occur from the time of detection until the storage notification is issued.The former is a latch circuit. The latter are set in the subtraction counter 1161 with preset at 1111, 1112, and 1113, respectively. The conditions for detecting an event that issues a storage command are not only the detection of a single event, but also the logical sum or logical product of multiple events, or a combination of both, and that the order of occurrence of the multiple events matches the specified one.
In this figure, the number of events is set to 2 to simplify the explanation, but it can be expanded to any number.

When detecting either of two events, each of the two factors is connected to a latch circuit 1111, 111, respectively.
Put it in 2. Then, the transmission control information sent from the transmission control circuit 6 and the pattern matching detection circuits 1121 and 1122 check whether it is a designated event or not. Note that at this time, the input from the latch circuit 1113 of the pattern match detection circuit 1122 is ignored. If the specified event is detected by either, OR gate 1151,
1152 and stored in flip-flop 1133.

When it is desired to detect that both events have been established, each of the two factors is connected to a latch circuit 111.
Enter 2,1113. This condition is, for example, when one event is the reception of a data frame and the other is the specified destination address at that time. This allows detection of data frames with a certain destination address. Pattern match detection circuit 11
If the establishment of the condition is detected in 22, the OR gate 115
1,1152 to flip-flop 1133
is memorized. At this time, the latch circuit 1111 receives a pattern such that no match occurs in the pattern match detection circuit 1121.

It is clear from the configuration of this figure that the above two conditions can be combined.

Next, a case will be described in which a match in the order of occurrence of multiple events is detected. In this case, the multiplexer 1171 makes two selections: continuous or discontinuous.

The factor that occurs first is stored in the latch circuit 1111, and the factor that occurs later is stored in the latch circuit 1112. When the pattern matching circuit 1121 detects a match, this state is stored in the flip-flop 1131. At this time, it is also stored in the flip-flop 1132, but on this side, the detection signal of the transmission control information from the transmission control circuit is input as the reset timing of the flip-flop, and unless a set input is input again, that is, pattern matching is detected. The structure is such that the circuit 1121 is reset unless a match is detected again. At this time, if the pattern match detection circuit 1122 also has a condition match output, the AND gates 1141 and 1142 perform a logical product of the two. In the case of consecutive matches in the order of occurrence, the output of the AND gate 1142 is the OR gate 1152.
If the order of occurrence matching, which does not need to be consecutive, is selected, the output of the AND gate 1141 is input to the OR gate 1152.

When the flip-flop 1133 is set as a result of the above-described various condition matching detection, the counter 116
Start 1. A certain number of events is preset in the counter 1161 by the information equipment, and is subtracted by a signal from the transmission control circuit 6 given via the event occurrence notification line 61, and when it reaches zero, the flip-flop 1134 is set. The output of the flip-flop 1134 is sent to the trace control circuit 12 via a signal line 1135 to the trace information storage circuit 15.
Instructs to save the current trace information stored in the .

Next, the line bit error detection circuit 20 used for tracing line error information will be explained with reference to FIG.

“1” in the received bit information input via the received bit signal line 31 activates the clock circuit 201,
Start timing for a certain set time. If a signal from the event occurrence notification line 61 from the transmission control circuit 6 is not received within this time, the clock circuit 201 instructs the trace control circuit 12 to acquire line error information via the error notification line 211. emits a signal.
If a signal is detected, the clock circuit 201 is reset via the OR gate 202, so no instruction to take in line error information is issued. In addition to the basic functions described above, it is necessary to control the clock circuit 201 so that it does not operate during frame reception and after the acquisition of the line error information described above is completed, and this function will be explained below. A frame receiving signal supplied from the transmission control circuit 6 via the frame receiving notification line 62 resets the clock circuit 201 via the OR gate 202. Intake notification line 63 from trace control circuit 12
The line error information acquisition completion signal supplied via the circuit sets the flip-flop 203 and at the same time activates the clock circuit 205 to start counting a certain period of time. The output of flip-flop 203 passes through OR gate 202 to keep timer circuit 201 in a reset state. In this state, a signal from the event occurrence notification line 61 resets the flip-flop 203 via the OR gate 204, or a signal output when the aforementioned clock circuit 205 completes a certain period of time measurement resets the flip-flop 203 via the OR gate 204. Continues until reset.

In this way, the present invention issues a storage timing command based on the event factor and the number of events occurring after the factor occurs, so that truly necessary information is saved.
Line failure points can be easily detected.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of a loop transmission system to which the present invention is applied, Fig. 2 is a time sequence example showing a transmission control method in the loop transmission system, and Fig. 3
The figure shows the frame format used in transmission.
FIG. 4 is a schematic configuration diagram of a supervisory control station, FIG. 5 is an example of a circuit configuration of a supervisory control station line tracing section, FIG. 6 is an example of transmission line trace information, and FIG. 7 is a supervisory control station according to the present invention. An embodiment of the trace information storage control circuit configuration of the line tracing unit. FIG. 8 shows an embodiment of the line bit error detection circuit configuration of the supervisory control station line tracing unit. 1...Line trace circuit, 11...Trace storage control circuit, 12...Trace control circuit.

Claims (1)

[Claims] 1. In a method of storing transmission line information in the order of reception, when preset transmission line information is detected, received transmission line information is stored until the number of received transmission line information reaches a preset number. Continue to store line information in the order in which it was received, and when the number of received transmission line information reaches the preset number above, save the previously stored transmission line information without storing the transmission line information that will be received thereafter. A method for storing transmission line information, characterized by: