JPS6313379B2 - - Google Patents
Info
- Publication number
- JPS6313379B2 JPS6313379B2 JP9280778A JP9280778A JPS6313379B2 JP S6313379 B2 JPS6313379 B2 JP S6313379B2 JP 9280778 A JP9280778 A JP 9280778A JP 9280778 A JP9280778 A JP 9280778A JP S6313379 B2 JPS6313379 B2 JP S6313379B2
- Authority
- JP
- Japan
- Prior art keywords
- codes
- systems
- output
- complement
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 9
- 230000001934 delay Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000013213 extrapolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Error Detection And Correction (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Description
【発明の詳細な説明】
この発明は特にPCM、△−Ｍ、DPCMなどの
伝送、記録再生に適した高品質伝送装置にかか
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high quality transmission device particularly suitable for transmission, recording and reproduction of PCM, Δ-M, DPCM, etc.
PCM、△−Ｍ音声等の特に記録再生に際し媒
体のドロツプアウトやきず、ごみ等により、また
通常伝送の際の雑音、混信等著しい障害を生じる
ことが知られている。 It is known that during recording and reproduction of PCM, Δ-M audio, etc., dropouts, scratches, dust, etc. on the medium cause significant disturbances such as noise and interference during normal transmission.
本発明は先ず、符号化信号を１ビツト乃至数ビ
ツト、または、PCMサンプル毎に、補数化して
伝送乃至記録再生する系を複数組備え而も同じ時
点の符号が互い補数関係にあるようにして伝送
し、受信乃至再生に際し完全に互いに補数関係に
あることをチエツクしながら受信し、何らかの原
因で一方の系が障害があればこれを除外し、もし
両方とも障害があることが判れば内挿・外挿・予
測情報で補うことを主旨とする。 First, the present invention includes a plurality of systems for converting encoded signals into complements for each bit to several bits or PCM samples, and then transmitting or recording/reproducing the signals so that the codes at the same point in time are complementary to each other. When transmitting, receiving or reproducing, it is checked that they are completely complementary to each other, and if there is a problem in one system for some reason, it is excluded, and if it is found that there is a problem in both systems, interpolation is performed.・The main purpose is to supplement with extrapolation/prediction information.
符号とその補数とを交互伝送することは送信電
力を一定化し、また雑音や記録媒体のドロツプア
ウトなど障害の低下に有効であることは発明者出
願昭53特願第71124号等記載の通りであるが、本
発明によるエラーチエツクは更に品質改善を行う
ことができる。 As described in patent application No. 71124 of 1983, etc., alternately transmitting the code and its complement is effective in keeping the transmission power constant and reducing disturbances such as noise and dropout of the recording medium. However, the error check according to the invention can further improve the quality.
第１図ａ，ｂは本発明を適用する伝送符号例を
示す。ａ図でX1，X2，X3，X4……の如き符号列
３０はX1，2，X3，4……のように１つおき
に補化されこれに対し併用伝送路の符号は３１の
ように1，X2，3，X4……の如く補化され、
同一時点に対するものが互に補数関係で並ぶ、こ
れは伝送においては別の線路或いは別の波長を用
い、記録再生系では２重トラツク等によつて行わ
れる。 FIGS. 1a and 1b show examples of transmission codes to which the present invention is applied. In figure a , the code strings 30 such as X 1 , X 2 , X 3 , X 4 . The code is complemented as 1 , X 2 , 3 , X 4 ... like 31,
Data for the same point in time are arranged in a complementary relationship. This is done by using different lines or different wavelengths in transmission, and by using a double track or the like in a recording/reproducing system.
ｂ図は同様な交互補数化を数ビツト単位で行つ
た場合を示す。例えばこれはPCMの１サンプル
でもよい。これらの補数化は通常２進では中央レ
ベルに対し相補対称性があるので１サンプルの全
ビツト、交番２進ではMSBのみで行えば対称性
があるのでMSBのみ補数を取ればよい。 Figure b shows a case where similar alternating complementation is performed in units of several bits. For example, this may be one sample of PCM. These complements usually have symmetry with respect to the center level in binary, so if all bits of one sample are converted, and in alternating binary, only the MSB has symmetry, so only the MSB needs to be complemented.
第２図は本発明に用いる符号送信部の内、一系
統の例を示す。１は信号源、２は符号器で、３は
パルス発振器、４は処理器で補数器５を所定のビ
ツトおきに補数化するようなゲートパルスを生じ
る。６は送信出力である。 FIG. 2 shows an example of one system of the code transmitter used in the present invention. 1 is a signal source, 2 is an encoder, 3 is a pulse oscillator, and 4 is a processor, which generates gate pulses to complement the complementer 5 every predetermined bit. 6 is the transmission output.
第３図は本発明による受信回路例を示す。二つ
の入力、７，８はそれぞれ遅延、１組の符号とそ
の補数符号とが同時に入るよう遅延９，１０を加
えて補数復元器１３，１４へ入る。１３，１４は
同期分離器１５、処理器１６で所定の時間位置で
補数を復元し、１３，１４の出力はスイツチ２２
が閉じれば合成され別のスイツチ２３を経て復号
器へ入る。回路１７は例えば加算器で、２チヤン
ネルのパルスを加えたものが補数であるから正常
は零になるような出力を持つ、もし１方のチヤネ
ルにミスがあれば１７は出力を生じスイツチ２２
の一方を切はなすがこの動作は１１と１２とで該
時点の時間的に前後両側の符号ないし符号群の値
を間挿したものと１３，１４の出力を比較器１
８，１９で比べ、より差の少い方を選ぶようスイ
ツチ２２を制御する。１８，１９は単なる引算器
でもよい、必要の応じ１８，１９の出力を更に比
べて２２を制御する。更に１８，１９の何れも出
力を有する時、すなわちこの時点の２チヤネル共
にエラーがある時はアンドゲート２０は出力を生
じ出力を全て内挿値を用いるようスイツチ２３を
制御する。 FIG. 3 shows an example of a receiving circuit according to the invention. The two inputs, 7 and 8, enter complement restorers 13 and 14 with delays 9 and 10 added, respectively, so that one set of codes and its complement code enter at the same time. 13 and 14 restore the complement at a predetermined time position by a synchronization separator 15 and a processor 16, and the outputs of 13 and 14 are sent to a switch 22.
When closed, the signals are combined and enter the decoder via another switch 23. The circuit 17 is, for example, an adder, and since the sum of the pulses of two channels is a complement, it has an output that is normally zero. If there is a mistake in one channel, the circuit 17 produces an output and switches the switch 22.
This operation is performed by interpolating the values of codes or code groups on both sides of the time at the time point 11 and 12, and the outputs of 13 and 14 are interpolated by the comparator 1.
8 and 19, and controls the switch 22 to select the one with the smaller difference. 18 and 19 may be simple subtracters, and if necessary, the outputs of 18 and 19 are further compared to control 22. Further, when both channels 18 and 19 have an output, that is, when there is an error in both channels at this point, the AND gate 20 generates an output and controls the switch 23 so that all the outputs use interpolated values.
こうして２５の出力は常にエラーのほとんどな
い出力となる。尚処理回路２１は２０の出力で動
作する単なる合成器でもよいが、１１，１２の出
力を撰択する機能を持たせてもよい。これには更
に同様な遅延や比較回路を要する。 In this way, the output of 25 is always an output with almost no errors. Note that the processing circuit 21 may be a simple synthesizer that operates with the output of 20, but may also have a function of selecting the outputs of 11 and 12. This also requires similar delay and comparison circuits.
本発明は一般に周期的に符号を補数として伝送
する系を複数備え、同時的に系の対応符号が補数
となるようにして、これを利用してエラーチエツ
クや制御を行うことを主旨とする。従つて必ずし
も第３図の回路の制御系をやめて、制御信号例え
ば第２図１７，１８，１９，２０等の出力でアラ
ーム類を制御してもよい。 The main purpose of the present invention is to generally include a plurality of systems that periodically transmit codes as complements, so that the corresponding codes of the systems simultaneously become complements, and to use this to perform error checking and control. Therefore, the control system of the circuit shown in FIG. 3 may be omitted, and the alarms may be controlled by the output of control signals such as those shown in FIG. 2, such as 17, 18, 19, and 20.
また系を２組に限らず３組以上とし遂次対応部
が補数となるように並べてもよい。 Furthermore, the number of systems is not limited to two, but three or more sets may be arranged so that the successive corresponding parts become complements.
第４図は３系統の例で、１は補数を取つた符号
を２種例示しｘ，ｙ，ｚは１組の例えばPCM符
号を示す。識別回路は第３図に準ずる。 FIG. 4 shows an example of three systems, where 1 indicates two types of codes with complements taken, and x, y, z indicate a set of, for example, PCM codes. The identification circuit is similar to that shown in FIG.
エラー識別回路も上記に限らず周知の種々の手
段によつて、制御信号を生じ或いは制御回路を構
成できる。 The error identification circuit can also generate a control signal or configure a control circuit by using various well-known means, not limited to those described above.
本発明は上記実施例に限らず種々の変形や実施
例部分の組合せができる。 The present invention is not limited to the embodiments described above, and various modifications and combinations of embodiment parts are possible.
第１図ａ，ｂは本発明による伝送符号の例３
０，３１，３２，３３を示す。
第２図は本発明に関する送信回路例を示す。１
……信号源、２……符号器、３……クロツクパル
ス源、４……処理器、５……補数器、６……出
力。
第３図は本発明による受信或いは再生回路例を
示す。７，８……入来信号、９，１０……遅延、
１１，１２……内挿器、１３，１４……補数器、
１５……同期分離器、１６……処理器、１７……
加算器等、１８……引算器等、２０……アンドゲ
ート、２１……処理器、２２，２３……スイツ
チ、２４……復号器、２５……信号出力。
第４図ａ，ｂは本発明に用いる符号の他の例を
示す。
Figure 1 a and b are example 3 of transmission codes according to the present invention.
0, 31, 32, 33 are shown. FIG. 2 shows an example of a transmitting circuit according to the present invention. 1
... signal source, 2 ... encoder, 3 ... clock pulse source, 4 ... processor, 5 ... complementer, 6 ... output. FIG. 3 shows an example of a receiving or reproducing circuit according to the present invention. 7, 8...Incoming signal, 9,10...Delay,
11, 12... interpolator, 13, 14... complementer,
15... Synchronization separator, 16... Processor, 17...
Adder etc., 18...Subtractor etc., 20...And gate, 21...Processor, 22, 23...Switch, 24...Decoder, 25...Signal output. FIGS. 4a and 4b show other examples of codes used in the present invention.
Claims (1)
送する系を複数組備える手段と、前記複数組にお
いてほぼ同一時点の符号が互いに補数関係とする
手段と、受信に当たり上記補数関係であるべき符
号が完全に補数関係ならば前記系統を合成復調
し、補数関係がない時は入力信号の前記時点の前
後の値の平均に近い方の符号のみを用いて復調す
るようにしたことを特徴とする高品質符号伝送装
置。1 means comprising a plurality of systems for transmitting digital codes as complements for each predetermined unit; means for ensuring that codes at approximately the same point in time in the plurality of sets are in a complementary relationship with each other; A high-quality code characterized in that if there is a complement relationship, the systems are combined and demodulated, and if there is no complement relationship, demodulation is performed using only the code that is closer to the average of the values before and after the input signal at the time point. Transmission device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280778A JPS5520048A (en) | 1978-07-28 | 1978-07-28 | High-quality code transmission device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280778A JPS5520048A (en) | 1978-07-28 | 1978-07-28 | High-quality code transmission device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5520048A JPS5520048A (en) | 1980-02-13 |
| JPS6313379B2 true JPS6313379B2 (en) | 1988-03-25 |
Family
ID=14064676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9280778A Granted JPS5520048A (en) | 1978-07-28 | 1978-07-28 | High-quality code transmission device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5520048A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261926A (en) * | 1987-04-20 | 1988-10-28 | Fujitsu Kiden Ltd | Parity circuit check system |
-
1978
- 1978-07-28 JP JP9280778A patent/JPS5520048A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5520048A (en) | 1980-02-13 |
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