JPS6313568B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias circuit for a power amplifier suitable for use in an output circuit of an audio device, and in particular is capable of increasing power conversion efficiency and satisfactorily improving switching distortion. It is.

Class A amplifier circuits, class B amplifier circuits, etc. have been conventionally used in the output circuits of audio equipment, but although the class A amplifier circuits do not cause switching distortion, they have the disadvantage of very poor power conversion efficiency. Although the class B amplifier circuit has higher power conversion efficiency than the class A amplifier circuit, it has the drawback of unavoidable switching distortion due to switching of the output transistor. Therefore, in order to reduce the occurrence of switching distortion in this class B amplifier circuit, a non-switching type power amplifier as shown in FIG. 1 has been proposed by devising the bias circuit of this class B amplifier circuit. That is, in FIG. 1, 1 indicates an audio signal input terminal, and the audio signal supplied to this audio signal input terminal 1 is supplied to the base of an npn transistor 2. Also, the emitter of this transistor 2 is connected to the negative power supply terminal - V _B to which a negative DC voltage is supplied, and the collector of this transistor 2 is connected by a three-stage Darlington connection.
It is connected to the base of the pnp transistor 3a constituting the SEPP circuit. In this example in Figure 1, this
The SEPP circuit consists of three pnp transistors 3a, 3
b and 3a and three npn transistors 4a, 4
b and 4c. That is, the collectors of each of the transistors 3a, 3b and 3c are connected to the negative power supply terminal -V CC to which a negative DC voltage is supplied, and the collectors of each of the transistors 4a, 4b and 4c are connected to the negative power supply terminal -V _CC to which a positive DC voltage is supplied. It is connected to the power supply terminal +V _CC , and the emitter of transistor 3a is connected to the base of transistor 3b, and the emitter of transistor 3a is connected to the emitter of transistor 4a and transistor 4 through resistor 5.
connected to the connection point of the base of transistor 3
The emitter of transistor 3b is connected to the base of transistor 3c, and the emitter of transistor 3b is connected to the emitter of transistor 4b and transistor 4c.
The emitter of the transistor 4c is connected to the emitter of the transistor 3c through a series circuit of resistors 7 and 8, and the connection point of the resistors 7 and 8 is connected to the connection point of the base of the transistor 4c through a load 9 such as a speaker. and ground. Further, the collector of the transistor 2 is connected to the emitter of an npn transistor 10 constituting an active bias circuit, and the collector of the transistor 10 is connected to the emitter of the transistor 1 through a resistor 10a.
0 and this transistor 1
0 is connected to the collector of a pnp transistor 12 constituting an active bias circuit through a temperature compensation diode 11, and the collector of this transistor 12 is connected to the base of the transistor 12 through a resistor 12a. transistor 1
The emitter of transistor 12 is connected to the base of transistor 4a constituting the SEPP circuit, and the emitter of transistor 12 is connected to positive power supply terminal +V _B to which a positive DC voltage is supplied via constant current circuit 13.

Further, the connection points of the resistors 7 and 8 are connected to the respective bases of a pnp transistor 14 and an npn transistor 15 constituting the current detection circuit, and the emitter of the transistor 14 is connected to a diode 16 and a resistor 17 connected in the forward direction. pnp through series circuit of
A diode-connected PNP transistor 1 constitutes a current mirror circuit together with a transistor 19.
8, and connect the emitter of this transistor 18 to the connection point of the base and collector of transistor 4a.
The connection point between the base and collector of this transistor 18 is connected to the base of a transistor 19, the emitter of this transistor 19 is connected to the base of the transistor 4a, and the collector of this transistor 19 is connected to the base of the transistor 12. Also, the collector of transistor 14 is connected to the base of transistor 3a. In this case, a current having the same value as the current flowing through transistor 18 flows through transistor 19 . Further, the emitter of the transistor 15 is connected to the connection point between the base and collector of a diode-connected NPN transistor 22 which forms a current mirror circuit together with an NQN transistor 23 through a series circuit of a forward-connected diode 20 and a resistor 21. The emitter of this transistor 22 is connected to the base of the transistor 3a, the connection point between the base and collector of this transistor 22 is connected to the base of the transistor 23, the emitter of this transistor 23 is connected to the base of the transistor 3a, and the emitter of this transistor 22 is connected to the base of the transistor 3a. The collector of transistor 23 is connected to the base of transistor 10, and the collector of transistor 15 is connected to the base of transistor 4a. A current having the same value as the current flowing through transistor 22 in this case flows through transistor 23.

In FIG. 1, when a positive input is received, the current on the npn transistor side of transistors 4a, 4b, and 4c increases, and the current on the npn transistor side of transistor 4a increases.
The voltage _{V a} between the base of and the output, ie the connection point of resistors 7 and 8, increases. At this time, the current detection circuit is composed of a transistor 18, a resistor 17, a diode 16, and a transistor 14 connected in series, and the detected voltage change does not appear as it is across each of the resistors 12a and 17. If the voltage change between the base and emitter of transistors 14 and 18 and the voltage change between the anode and cathode of diode 16 are respectively ΔV _BE , then the base of transistor 4a and resistors 7 and 8
From the voltage change ΔV _a between the connection point and this 3ΔV _BE
A voltage change ΔV B1 obtained by subtracting ΔV _B1 appears between each of the resistors 12a and 17, that is, between the collector and emitter of the transistor 12, and as a result, the voltage change between the base of the transistor 3a and the output terminal, that is, the resistor 7. The bias voltage between the connection point 8 and 8 is reduced by 3ΔV _BE . Also, when there is a negative input, the transistors 3a, 3b,
The current on the PNP transistor side of 3c increases, and the voltage V _b between the base of transistor 3a and the output terminal, that is, the connection point of resistors 7 and 8 increases, and the current detection circuit at this time operates in the same manner as described above. , resistor 10
a, that is, between the collector and emitter of transistor 10 and the base of transistor 3a and resistors 7 and 8.
A voltage change is generated by subtracting 3ΔV _BE from the voltage change ΔV _b between the connection point _of As a result, the emitter currents I _a and I _b of transistors 4c and 3c become as shown in FIG. 2, respectively, and the connection between the upper and lower waveforms becomes smoother, and switching distortion and crossover distortion occur. It is possible to obtain a low-distortion composite output waveform with suppressed distortion. In Figure 2, I _c and I' _c are transistors 4
c and 3c idling current.

However, in FIG. 1, nonlinear elements such as transistors 10 and 12 are inserted into the signal path, so nonlinear distortion becomes a problem, and the output transistor is a voltage-driven element such as a MOS field effect transistor. When I used it, there was an inconvenience that it could not be applied.

In view of these points, the present invention eliminates the above-mentioned non-direct distortion and also enables the use of voltage-driven transistors such as MOS field effect transistors in the output circuit.

Hereinafter, one embodiment of the bias circuit of the power amplifier of the present invention will be explained with reference to FIG. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 3, the audio signal input terminal 1 is connected via a series circuit of a resistor 24 for bias voltage determination and a diode 11a for temperature compensation to an N-channel MOS field effect transistor 3 constituting an SEPP circuit. Connected to the gate of the MOS field effect transistor 4, this diode 11
A and the gate of the MOS field effect transistor 4 are connected to the collector, which is the control output terminal, of a PNP transistor 25a constituting the variable current source 25, and the emitter of the transistor 25a is connected to a positive direct current through a resistor 25b. This transistor 25a is connected to the positive power supply terminal +V _B to which voltage is supplied.
The base of the transistor 25a is connected to the positive power supply terminal +V _B through a series circuit of a diode 25c and a resistor 25d, and the base of the transistor 25a is grounded through a constant current circuit 28 for bias determination. In this case, the constant current circuit 28 is constructed so that its current can be adjusted. The transistor 25a and the diode 25c constitute a current mirror circuit. Also, the audio signal input terminal 1 is connected to a resistor 26 for determining a bias voltage and a diode 11b for temperature compensation.
The diode 11b and the gate of the MOS field effect transistor 3 are connected to the collector of the npn transistor 27a constituting the variable current 27. The emitter of this transistor 27a is connected to a negative power supply terminal _-VB to which a negative DC voltage is supplied via a resistor 27b. The base of the transistor 27a is connected to the negative power supply terminal _-VB through a series circuit of a diode 27c and a resistor 27d, so that the diode 27c and the transistor 27a constitute a current mirror circuit. Also diode 25c
and the connection point of the constant current circuit 28 is connected to the base of the pnp transistor 29a, and this transistor 2
The emitter of transistor 9a is connected to the positive power supply terminal +V _B via a resistor 29b, and the collector, which is the control output terminal of this transistor 29a, is connected to the connection point between the base of the transistor 27a, which is the control input terminal of the current mirror circuit, and the diode 27c. Connecting. In this case, the diode 25c and the transistor 29a constitute a current mirror circuit. Therefore, in this case, the diode 25c and the transistor 25
The diode 25c and the transistor 29a constitute a current mirror circuit, and the diode 2 is supplied with the output current from the transistor 29a.
7c and the transistor 27a constitute a current mirror circuit, so the transistors 25a and 29
The currents flowing through a and 27a are equal.
Furthermore, the drain of the MOS field effect transistor 4 is connected to the positive power supply terminal +V _CC to which a positive DC voltage is supplied, and the drain of the MOS field effect transistor 3 is connected to the negative power supply terminal -V _CC to which a negative DC voltage is supplied. A series circuit of resistors 7 and 8 is connected between the sources of the MOS field effect transistors 4 and 3, and a connection point between the resistors 7 and 8 is grounded via a load 9 such as a speaker.

Also, the connection point between the resistor 24 and the diode 11a is an npn which constitutes a voltage detection and voltage-current conversion circuit.
The emitter of this transistor 30 is connected to the connection point of the resistors 7 and 8 through the resistor 31, and the collector of this transistor 30 is connected to the connection point of the diode 25c and the constant current circuit 28. Connecting. In this case, a current corresponding to the voltage at the connection point between the resistor 24 and the diode 11a is obtained at the collector of the transistor 30. Further, the connection point between the resistor 26 and the diode 11b constitutes a voltage detection and voltage-current conversion circuit.
The emitter of this transistor 32 is connected to the connection point of resistors 7 and 8 through a resistor 33, and the collector of this transistor 32 is connected to a series circuit of a diode 34a and a resistor 34b. Negative power supply terminal through V _B
At the same time, the collector of this transistor 32 is connected to the base of an npn type transistor 34c which together with a diode 34a constitutes a current mirror circuit 34, and the emitter of this transistor 34c is connected to a negative power supply terminal _-VB through a resistor 34d. The collector of this transistor 34c is connected to the connection point of the diode 25c and the constant current circuit 29. In this case, a current corresponding to the voltage at the connection point between the resistor 26 and the diode 11b is obtained at the collector of the transistor 32, and the current mirror circuit 34 constitutes a phase inversion circuit for this current. Therefore, in this case, the constant current circuit 28 includes resistors 24 and 2.
A current corresponding to the voltage across the diode 25 is supplied, thereby forming a current mirror circuit.
Since the current flowing through c is controlled, the current flowing through transistors 25a, 29a and 27a can thereby be controlled. That is, the resistance values of the resistors 7 and 8 are R _S , the current flowing through the resistor 7 is I _L , the current flowing through the resistor 8 is _-IL , and the transistors 25a constituting the variable current sources 25 and 27
In the transistor stars 30 and 32 constituting the voltage detection circuit, when the current of each of the resistors 24 and 27a is I, and the resistance value of each of the resistors 24 and 26 is R,
I _L and R _S are detected, and the current I of each of the transistors 25a and 27a is controlled by this detection output. Also, at this time, the bias voltage of the MOS field effect transistors 4 and 3 is determined by I.R, and when there is no signal, the current is adjusted so that 2I.R=V _GS+ +V _GS- = 2.I _{L.R S.} Here V _GS+ is MOS
Gate-source voltage of field effect transistor 4
V _GS- is the gate of MOS field effect transistor 4.
Indicates source voltage.

Further, when a positive half-cycle input signal is supplied to the audio signal input terminal 1, the current flowing through the MOS field effect transistor 4 changes from I _L to I _L +ΔI _L , and the transistors 25a and 2 forming the variable current sources 25 and 27 change from I L to I L +ΔI L.
Assuming that the current of 7a changes from I by I+ΔI, the sum of the gate-source voltages of MOS field effect transistors 4 and 3 is expressed by the following equation.

V _GS+ +V _GS- =2I・R+2∆I・R -∆I _L・R _S ...(1) In this case, due to the increase in ∆I _L , V _GS+ also becomes ∆V _GS
=ΔI _L /gm, but since the gm of this MOS field effect transistor 4 is sufficiently large, this ΔV _GS is ignored.

Therefore, in order to prevent the MOS field effect transistor 3 from being cut off when the MOS field effect transistor 4 is turned on, it is sufficient to satisfy ΔI=ΔI _L ·R _S /2R (2) from equation (1). Here, V _GS+ and V _GS- are assumed to be approximately constant. Similarly, when a negative half-cycle input signal is supplied, equation (2) should similarly hold in order to prevent the MOS field effect transistor 4 from being cut off when the MOS field effect transistor 3 is on. In the present invention, the detection output signals of the voltage detection transistors 30 and 32 and the variable current source 25,
The structure is such that the relationship between the currents of the transistors 25a and 27a constituting the transistor 27 is as shown in equation (2).

Since the present invention is as described above, the voltage V ₄ between the gate of the MOS field effect transistor 4 and the connection point of the resistors 7 and 8, that is, the output terminal, and the voltage V 4 between the gate of the MOS field effect transistor 3 and the output terminal. Voltage
V ₃ changes as shown in Figure 4, and therefore this
The currents Ia and Ib flowing through the MOS field effect transistors 4 and 3 change as shown in FIG.
The field effect transistors 4 and 3 are never cut off and are always connected to the transistors 25a and 2 which constitute the variable current sources 25 and 27 by the output signals of the transistors 30 and 32 which constitute the voltage detection circuit.
Since the bias voltage of MOS field effect transistors 4 and 3 is controlled by controlling 7a, the load 9
The connection between the upper and lower waveforms of the current flowing through the circuit becomes smooth, and it is possible to obtain a low-distortion composite output waveform that suppresses switching distortion and crossover distortion. Further, in the present invention, the audio signal supplied to the audio signal input terminal 1 is transmitted to the MOS field effect transistors 4 and 3 which constitute the output transistor.
Resistor 2 is a linear element to supply the gate of
4 and 26, and does not pass through a transistor, which is a non-linear element, there is an advantage that non-linear distortion does not occur as much, and according to the present invention, voltage drive is possible, so voltage drive, which is a high-speed switching element. MOS field effect transistor 4,
3 can be used.

In the above embodiment, two resistors 24 and 26 are provided and the input signal is supplied to the midpoint of their connection, but it is also possible to use one resistor and supply the input signal to each end of the resistor. Of course, the same effects as described above can be obtained even in this case. Further, in the above embodiment, an example was described in which a MOS field effect transistor was used as the output transistor, but it goes without saying that other transistors such as a bipolar transistor can be used in place of this, if necessary. Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various other configurations without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an example of a bias circuit of a conventional power amplifier, FIGS. 2 and 4 are diagrams for explaining the present invention, and FIG. 3 is an implementation of a bias circuit of a power amplifier of the present invention. It is a block diagram which shows an example. 1 is an audio signal input terminal, 3 and 4 are each MOS
Field effect transistors, 7, 8, 24 and 26 are resistors, 9 is a load, 25 and 27 are variable current sources each consisting of a current mirror circuit, 29a and 34c are transistors forming a current mirror circuit, 30 and 32 are voltage detection transistors.

Claims (1)

[Claims] 1. A first current mirror circuit having a control input terminal and first and second control output terminals; a first control output terminal of the first current mirror circuit is connected to one end; a first resistor, the other end of which is connected to the control output terminal, and a second resistor of the first current mirror circuit;
The second control output terminal is connected to the control input terminal.
a current mirror circuit, the voltages and input signals at one end and the other end of the first resistor are respectively supplied to the input electrodes, and the output electrodes are commonly connected through the second and third resistors, respectively. between the first and second output transistors, an output terminal derived from the connection point of the second and third resistors, and the respective input electrodes of the first and second output transistors and the output terminal; and first and second voltage detection transistors whose respective input electrodes are connected to the first and second voltage detection transistors, and the signals obtained at the respective output electrodes of the first and second voltage detection transistors are connected to the first current. A bias circuit for a power amplifier, characterized in that the power is supplied to a control input terminal of a mirror circuit.