JPS6314540B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion circuit that converts a pulse signal of NRZ (Non Return to Zero) code to a pulse signal of RZ (Return to Zero) code.

In data transmission, it is often necessary to convert NRZ code pulse signals to RZ code pulse signals, but during this conversion, care must be taken to avoid generating noise, so-called whiskers, etc. that can cause errors in the operation of logic circuits. It is important to process.

Conventionally, as a code conversion circuit from an NRZ code to an RZ code, there has been a code conversion circuit that samples an NRZ code pulse signal using a constant clock signal and converts it into an NRZ code pulse signal. However, such a code conversion circuit has a drawback that if the input pulse signal has jitter, drift, etc., the above-mentioned noise will occur in the output pulse signal.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above.
The code pulse signal is sampled by a clock signal and supplied to a storage circuit, such as a flip-flop, and the output of the flip-flop is further supplied to a gate circuit, such as a NAND gate, for sampling by the clock signal. The present invention aims to provide a code conversion circuit that can obtain an RZ code pulse signal free from noise.

An embodiment of the present invention will be described below with reference to the drawings. In the circuit diagram of the present invention shown in FIG. 1, the data input terminal D of flip-flop 1 has an NRZ
A pulse signal a of the same sign is input to the clock input terminal T, and a clock signal b is input to the inverter 2.
Input via . Here, the clock signal output from the inverter 2 is indicated by c. flip
The pulse signal d of the Q output of the flop 1 and the clock signal b are input to the NAND gate 3, and the AND output of the two is outputted via the inverter 4 as the RZ code pulse signal e.

FIG. 2 is a timing diagram illustrating the operation of FIG. 1. In FIG. 2, the pulse signal a is 1010
The clock signal b synchronized with this data is input to the flip-flop 1 in the form of being sampled by the clock signal c obtained by inverting the clock signal b by the inverter 2. As a result, the flip-flop 1 outputs the pulse signal d to the Q output terminal. As shown, there is a delay t ₁ between clock signals b and c, and a delay t ₂ between clock signal c and pulse signal a. That is, the purpose is to eliminate the cause of noise by effectively utilizing the operation delay times t ₁ and t ₂ that inevitably occur when logic elements such as the inverter 2 and the flip-flop 1 are used. The pulse signal d is also sampled with the clock signal b according to the function of the NAND gate 3, and is outputted from the output terminal of the inverter 4 as a pulse signal e. The NRZ code pulse signal a is eventually converted into the RZ code pulse signal e by the clock signal b with a delay equivalent to a half cycle.

Note that if an AND gate is used instead of the NAND gate 3, the inverter 4 becomes unnecessary.

As described above, according to the present invention, by using a simple logic element, high-quality code conversion can be performed, and the present invention can be applied to a PCM repeater and the like to improve its reliability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the code conversion circuit of the present invention, and FIG. 2 is a timing diagram showing the operation of the code conversion circuit shown in FIG. 1...flip flop, 2, 4...inverter, 3...NAND gate.

Claims (1)

[Claims] 1. A D flip-flop circuit having a D input terminal for an NRZ code pulse signal and an input terminal for a clock pulse signal input via an inverter, one input terminal connected to the output side of the D flip-flop circuit, and the inverter. and a gate circuit having the other input terminal connected to the input side of the code conversion circuit.