JPS6314597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a load balance calculation circuit for balancing the amount of load shared by both drive control devices in a system in which the same load is controlled by two drive control devices including electric motors, etc. It is.

Conventionally, when the same load using an electric motor or the like is controlled by two drive control devices, in order to balance the load sharing of these control devices, for example, a load balance calculator is connected as shown in Figure 1. A load balancing control circuit is used.

That is, the circuit shown in FIG. 1 is a circuit in which a load L is driven and controlled by a pair of electric motors M ₁ and M ₂ .
Speed regulators SR ₁ and SR ₂ that input the speed setting signal and speed detection signal and output the armature current setting value signal.
Then, the output signals of the speed regulators SR ₁ and SR ₂ are inputted, and _{the signals obtained by detecting the respective dynamic currents Id 1 and Id 2 of the electric} motors M 1 and M ₂ are inputted.
Current regulators CR _{1 and CR 2 that output control signals to control thyristors SCR 1 and SCR 2} installed in the power supply of M ₂
and the detected currents of the electric motors M ₁ and M ₂ are provided.
In order to input Id ₁ and Id ₂ , respectively, and balance the load sharing of each electric motor M ₁ and M ₂ , each of the speed regulators SR ₁ and
A load balance calculator LBO that outputs balance correction signals S ₁ and S ₂ to be supplied to SR ₂ is connected and arranged.

However, in this type of control circuit, performing load balancing control more than necessary using the load balancing calculator LBO and repeatedly adjusting the load sharing of each electric motor M ₁ and M ₂ is difficult, for example, due to string vibration loads or Loads operated with elastic materials such as ropes have disadvantages that can be detrimental.

Therefore, in order to eliminate the above-mentioned drawbacks, the load sharing ratio is set to a predetermined value, and the load is set to have a dead band for load unbalance so that the load balance calculation circuit does not operate until a predetermined unbalance value is reached. Attempts have been made to construct a circuit for the balance arithmetic unit LBO (see FIGS. 2 to 4). That is, as shown in Fig. 2, dead zone setting resistors Rd _z1 and Rd _z2 are connected to the load balance calculator LBO, and the differential current (Id ₁ − Id ₂ ) of the input current signals Id ₁ and Id ₂ is controlled. is within the range of O±α (dead band value), the arithmetic unit LBO does not operate and therefore does not generate the balance correction signal S.

However, even when using a load balance calculator LBO with this kind of dead zone α, if a relatively large unbalance value occurs, a balance correction signal is issued and balance control is started, but if the dead zone α is entered, Since the control is stopped at this point, there is a drawback that a load deviation equivalent to a dead zone always remains. Further, when the dead band value is constant, if the load amount is small, the unbalance value becomes a relatively large value, and there is a problem that balance control corresponding to the load cannot be achieved.

That is, according to the prior art, since the dead band is fixed, it has been pointed out that there is a problem that a so-called offset occurs in which a control deviation remains.

Therefore, as a result of various studies and trial production, the present inventors incorporated a hysteresis circuit into the load balance calculator that issues the load balance control signal, and made the dead band value of the load unbalance a function of the load amount. It has been found that the above-mentioned problems can be solved at once by improving unbalance control and preventing the occurrence of offset when the load is small. In other words, in a load balance calculation circuit that detects the load current of each motor that drives and controls the load, compares and calculates these, and obtains the required balance correction signal, the unbalance value of the load is determined by a dead band that is set as a function of the load amount. When the unbalance value exceeds the dead band value, a predetermined balance correction signal is output, and when the unbalance value returns to within the predetermined value range, the signal is also output under the action of the hysteresis element. It has been realized that the balance correction signal can be sent until complete balance of the load is achieved.

Therefore, the general object of the present invention is to provide a system in which the same load is driven by two drive control devices.
It is an object of the present invention to provide a load balance calculation circuit that can always quickly and stably balance the load share of each drive control device.

In order to achieve the above object, the present invention provides a speed regulator that inputs a speed setting signal and a speed detection signal and outputs an armature current setting value signal, and detects the output signal of the speed regulator and the motor. A current regulator is provided that inputs current and outputs a control signal to control the motor, and the same load is set to be controlled by two motors each equipped with the same control system, and the detected current of each motor is adjusted. In a load balance calculation circuit configured to input and detect load unbalance, and to provide a dead band for load unbalance to control load sharing in a balanced manner, a balance correction signal is input to each speed regulator. A current detector is provided to detect each load current, and an unbalance value is calculated from the deviation from the load current detected by these current detectors.On the other hand, the dead band value is calculated by inputting the average value of each of the load currents. When the unbalance value is within a predetermined dead band, the balance correction signal is not output, and when the unbalance value is outside the predetermined dead band, the balance correction signal is output and the unbalance correction signal is output. The present invention is characterized by providing a hysteresis circuit configured to output a balance correction signal until complete balance is achieved even if the balance value returns to within the dead band.

Other objects and advantages of the present invention will become more apparent from the detailed description below.

Next, preferred embodiments of the load balance calculation circuit according to the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 5, reference numeral 10 indicates a load;
This load 10 is balanced and controlled by a pair of electric motors 12 and 14. Thyristors 16 and 18 are connected to the power supply sides of these electric motors 12 and 14, and the thyristors 16 and 18 are controlled to start by current regulators 20 and 22, respectively. Current regulator 2
The output terminals of speed regulators 24 and 26 which input a speed setting signal and a speed detection signal and output an armature current setting value signal are connected to one input terminal of the speed regulators 0 and 22, and the speed regulator 24 , 26 are connected to the output terminals of the load balance calculator 28. Further, current detectors 30, 32 are connected to the power supply sides of the electric motors 12, 14, and these current detectors 30,
32, the detected currents Id ₁ and Id ₂ of the motors 12 and 14 are input to the load balance calculator 28, and the detected currents Id ₁ and Id ₂ are inputted to the current regulator 2.
The circuit is configured so that the input signal is input to the other input terminal of 0 and 22. In particular, in the present invention, a hysteresis circuit 34 is incorporated into the load balance calculator 28, as can be easily understood from FIG. In addition, in the figure, reference numerals 36 and 38 are speed generators,
The rotation speed is determined by the speed controller 2 as a speed detection signal.
It will be introduced on April 26th.

The present invention is constructed as described above, and its operation and effects will be described below, particularly in relation to the hysteresis circuit, which is the gist of the present invention.

The load currents Id ₁ and Id ₂ detected by the current detectors 30 and 32 are input to the load balance calculator 28 to generate an unbalanced value |Id ₂ −Id ₁ | and the hysteresis circuit 3
4 will be introduced. On the other hand, the hysteresis circuit 34
In addition, the average value of the load currents Id ₁ and Id ₂ (Id ₁ +Id ₂ /2) is also introduced, which causes the dead zone value α to vary proportionally. That is, an unbalance value is calculated from the difference between the load currents Id ₁ and Id ₂ and is set as an absolute value, and a relative dead band value α is set by this absolute value, the reference value, and the average value of the load currents. It turns out. Therefore,
As can be easily understood from Figures 6 and 7,
When the unbalance value is within the dead band consisting of the dead band value α, no correction signal is output, and when the unbalance value is outside the dead band, the load balance calculator 28 outputs a correction signal to the speed regulator 24, Appropriate correction signals S ₁ , S ₂ are given to 26, thereby making it possible to perform balance control stably and quickly. On the other hand, even if the unbalanced value of the load current returns to within the dead band value α as a result of sending the correction signals S ₁ and S ₂ , the correction signals S ₁ and S ₂ are It continues to be delivered under the influence of the element and is stopped when the load current is fully balanced.

According to the present invention, as described above, even when the load current returns to the dead band during load balancing control, the balancing control is not stopped, so no residual deviation of the load occurs and the occurrence of offset is prevented.
In addition, since the load unbalance value also changes relatively, suitable balance control could be achieved even when the load amount was small.

The preferred embodiments of the present invention have been described above, and the circuit of the present invention can achieve quick and stable load balance control with a simple configuration. Therefore,
It can be very suitably applied to supporting the bucket of an unloader such as a crane and controlling a control device for driving an opening/closing rope. It goes without saying that various other design changes can be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

Figure 1 is a system diagram of a control circuit using a conventional load balance calculation unit, Figure 2 is a block diagram showing a conventional load balance calculation circuit, and Figure 3 is a block diagram of the load balance calculation circuit shown in Figure 2. , FIG. 4 is an operating characteristic diagram of the load balance calculator of FIG. 1, FIG. 5 is a system diagram of a control circuit using the load balance calculator of the present invention, and FIG. 6 is a diagram of the load balance calculator of the present invention. The circuit block diagram shown in FIG. 7 is an operational characteristic diagram of the hysteresis circuit incorporated in the load balance calculation circuit of the present invention. 10... Load, 12, 14... Electric motor, 16,
18... Thyristor, 20, 22... Current regulator, 24, 26... Speed regulator, 28... Load balance calculator, 30, 32... Current detector, 34...
Hysteresis circuit, 36, 38...speed generator.

Claims (1)

[Claims] 1. A speed regulator that inputs a speed setting signal and a speed detection signal and outputs an armature current setting value signal, and a motor that receives the output signal of this speed regulator and the detection current of the motor and outputs an armature current setting value signal. A current regulator is installed to output a control signal to control the load, and the same load is set to be controlled by two motors each equipped with the same control system. The load current of each motor is detected in a load balance calculation circuit configured to detect balance and input a balance correction signal to each speed regulator to control load sharing in a balanced manner by providing a dead band for load unbalance. Each current detector is provided, and the unbalance value is calculated from the deviation from the load current detected by these current detectors, while the average value of each of the load currents is input and the dead band value is varied in proportion to this. and when the unbalance value is within a predetermined dead band, the balance correction signal is not output, and when the unbalance value is outside the predetermined dead band, the balance correction signal is output and the unbalance value is within the dead band. A load balance calculation circuit comprising a hysteresis circuit configured to output a balance correction signal until complete balance is achieved even after recovery.