JPS631553B2 - - Google Patents

Abstract

An electronic watch comprises a stepping motor 6 for driving a mechanism for displaying the time information, a quartz crystal controlled oscillator 1, a frequency divider 2 with an adjustable division ratio, a circuit 7 for adjusting the division ratio eg by suppressing a number of pulses from the oscillator to the divider, a memory 8 containing data corresponding to the number of the pulses to be suppressed in each adjusting, cycle and a logic circuit 10 which, in response to an interrogation signal, (switch 9) produces a measuring signal at the output of gate 19 which is supplied to the coil of the stepping motor and which comprises a series of pulse trains whose distribution is representative of the division factor and the frequency of the oscillator and whose duration is sufficiently short so as not to cause the motor to rotate and sufficiently long to cause a magnetic stray field from the motor which can be detected by an external apparatus for measuring therefrom the rate of the watch. The interrogation signal upon closure of switch 9 causes the divider to divide with its unadjusted value. A gate 11 is enabled by 1 Hz pulses at 11a to pass trains of 256 Hz pulses in alternate half quartz-second intervals. The pulses pass through the gate 19 until their number, counted by counter 17, equals the adjustment number eg 5 held in memory 8. The interrogation signal also acts on switch circuit 4 to disconnect the motor control inputs at 4a 4b of circuit 5 from the divider 2, and apply the measuring signal pulses at input 4e from the gate 19 instead. In the embodiment described, a "quartz-second" is shorter than a normal second, the watch crystal frequency being higher than a nominal frequency, alternatively the measuring signal may be transmitted acoustically. The external measuring apparatus is described in App No. 79/36415. <IMAGE>

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an electronic timepiece, which includes an oscillator used as a time base, a frequency divider coupled to the oscillator and having an adjustable frequency division rate, and a circuit for adjusting the frequency division rate. a memory associated with this adjustment circuit and whose state represents the magnitude of said adjustment; and a transformer responsive to signals generated in the clock by wave radiation detected by an external device for measuring the rate of the clock. Concerning things that are equipped with eucalyptus.

To measure the rate of this type of clock, a device is used that detects the stray magnetic fields of the stepper motor and precisely measures the time between two drive pulses.

This device allows sufficient measurement results to be obtained quickly if the drive pulses are separated by a short time, eg, 1 second. On the other hand, if the watch does not have a second hand and the drive pulse interval is 10 to 20 seconds or 1 minute, the progress measurement time will be longer.

U.S. Pat. No. 3,998,044 discloses a device for reducing the time it takes to measure the progress of such a clock,
In this case, the pulse generated in the middle stage of the frequency divider is
It supplies the motor with pulses that are short enough not to rotate the motor, but high enough in frequency to shorten the measurement time. However, this device cannot be used in watches with frequency dividers with adjustable frequency division ratios. Such watches, for example Swiss patent no.
In watches such as those described in US Pat. Nos. 53493 and 558559, pulses are subtracted and added at predetermined points in the divider circuit for each adjustment cycle (which may last as long as 64 seconds). Therefore, in one adjustment cycle, the time between two consecutive drive pulses is not constant.

Therefore, in order to accurately measure the clock advance, from the measurement of the time elapsed between each pulse occurring at a time equal to at least one adjustment cycle, 2
It is necessary to calculate the average time elapsed between two drive pulses. However, the problem with this measurement is that there is no indication of the beginning and end of the conditioning cycle.

Therefore, it is an object of the present invention to provide a means for applying a signal to a motor that can promptly and accurately measure the progress of a clock that does not cause the motor to rotate, taking into account the true frequency of the oscillator and the division ratio of the frequency divider. The object of the present invention is to eliminate the drawbacks of the prior art by providing a timepiece.

Hereinafter, the present invention will be described with reference to a first embodiment. This embodiment is equipped with a quartz oscillator 1, which divides a pulse with a frequency of, for example, 32,768 Hz (this is a value generally adopted during manufacturing) with a positive or negative tolerance of about 1 in 100,000. This is what is supplied to the vessel 2. Frequency divider 2 has a variable frequency division ratio, and adjusts the pulse frequency supplied by the oscillator to, for example, 1Hz.
It can be precisely reduced to A circuit 3 for shaping the drive pulse is connected to this frequency divider,
The two outputs are the input 4 of the changeover switch circuit 4.
a and 4b, respectively. Outputs 4h and 4j of the circuit 4 are connected to a control circuit 5 which applies drive pulses to the coils of a step motor 6 which drives a display mechanism (not shown).

The circuit 7 adjusts the frequency division ratio and is connected to the frequency divider 2. This circuit is known in particular from Swiss Patent No. 534913. That is, this patent discloses an adjustment circuit for suppressing a predetermined number of pulses from an oscillator output pulse for an arbitrary period of time.

Also, according to Swiss Patent No. 558559, another method is proposed, namely, the adjustment circuit adds a pulse to the output pulse of the oscillator, or, equivalently, synchronously decreases the division ratio of any time divider. A method for doing so is disclosed. Therefore, it is possible to use quartz whose frequency is lower than the nominal frequency.

Irrespective of this method, the adjustment circuit 7 is connected to a memory 8 containing data regarding the magnitude of the adjustment. This memory can take various forms, but in particular consists of electronic components.

The clock is equipped with a stem (not shown) for setting time and is configured to take three axes of position. That is, in the inwardly displaced position, or the first position, the stem is inactive, in the intermediate, or second position, the hands can be moved to set the time on the clock, and in the fully retracted position, or the third position. In its position it is adapted to act on interrogation means 9, shown as a switch in FIG. This switch connects the positive terminal of the battery that supplies power to the motor and the input of the switch circuit 4 via a matching circuit (not shown).
4k and the input 7L of the adjustment circuit 7.

Furthermore, there is a logic circuit 10, which is a frequency divider 2.
Inputs 10a, 10b connected to outputs 2c, 2d of
and a plurality of inputs 1 connected to the output 8m of the memory 8
0c and an output 10d connected to the information input 4e of the switch circuit 4.

The logic circuit further includes elements 11, 16 to 19, which will be described later.
It is equipped with

The inputs 10a and 10b are connected to inputs 11a and 11b of an AND gate 11, respectively.

Input 10c is connected to input 16a of comparator 16, whose input 16b is connected to output 17a of the divider stage of counter 17. Output 16
c is the clock input 18a of the flip-flop 18
It is connected to the. The non-inverting output Q and the inverting output of the flip-flop 18 are connected to the reset input 17RAZ of the counter and the input 19a of the AND gate 19.
are connected to each. Reset input 18
RAZ is connected to input 11b of gate 11. Further, the output 11c of the gate 11 is connected to the clock input 17CL of the counter and the input 19b of the gate 19. Output 19c is connected to output 10d of logic circuit 10.

The operation of the frequency divider 2 having an adjustable frequency division ratio, the adjustment circuit 7 for adjusting the frequency division ratio of the frequency divider, and the operation of the memory are as described in the aforementioned Swiss Patent Nos. 534913 and 558559. , the adjustment circuit 7 is adapted to receive data from the frequency divider 2 at its input 7f regarding the duration of the adjustment cycle and data regarding the magnitude of the adjustment to the frequency division ratio at its input 7g. In this embodiment, this data is stored in the memory 8 in the form of a number of units corresponding to a correction of at least 1/10 of a second per day in the speed of the clock.

The shaping circuit 3 inputs the signal from the frequency divider 2 and outputs pulses every second alternately to its two output terminals.
Under normal conditions, pulses are generated at the output of the circuit 4 and input to the control circuit, which alternately supplies drive pulses to the motor 6. This causes the motor to rotate forward at one step per second. Since this shaping circuit 3 is well known, detailed explanation thereof will be omitted.

FIG. 3 is a circuit diagram of the switch means 4 of FIG.
The means are connected between the shaping circuit 3 and the control circuit 5.

The first output 3a of the shaping circuit 3 is connected to the switching means 4.
is connected to the first input 4a of the
a is connected to the input 21b of the AND gate 21. The other input 21a of AND gate 21 is connected to the output of inverter 22. The data input 4e is connected to one input 24b of the AND gate 24, the other input 24b being connected to the control input 4k of the switch means 4. This input 4k is connected to the input of the inverter 22. The outputs of the gates 21 and 24 are input 25 of the OR gate 25.
a, 25b, respectively, and the output 25c of the OR gate 25 is the output 4h, that is, the control circuit 5
is connected to one input (G3) of the. The output 23c of the gate 23 is connected to the output 4j, ie the other input of the circuit 5.

When the stem of the watch is in the first or second position, the switch 9 is opened and the input of the switch means 4 is activated.
4K is logic level “0” (hereinafter simply referred to as “0”)
It is in. The same logic level therefore appears at input 24b of gate 24, and the signal at input 4e appears at gate 24.
5 is not added to the input 25b. Since the input of the inverter 22 is also "0", its output is a logic level "1" (hereinafter simply referred to as "1"), and the gate 2
1 and 23 are added to inputs 21a and 23a. The signal at input 4a thus reaches output 4h via OR gate 25, and the signal at input 4b is sent to output 4j.

When measuring the progress of a clock, place the stem in the third position. Therefore, switch 9 is closed and becomes "1".
is the input 4k of the switch means 4 and therefore the gate 2
4 and to the input of the inverter 22. The signal applied to data input 4e therefore reaches output 4h via OR gate 25. At this time, the output of the inverter 22 is "0", so the gates 21 and 23 are closed, and the inputs 4a and 4
The signal b cannot reach the outputs 4h, 4j of the switch means 4. Therefore, the output 4j is "0".

In this case, the control circuit 5 connected to the outputs 4h and 4j receives only the signal at the input 4e. Information on this signal will be described later.

When the signal 4h is "0", only the transistor T1 is conductive. Therefore, no current flows through the coil of the motor 6. With each pulse of signal 4h, control gates G1 and G3 of transistors T1 and T3 are set to "1"
The gates G2 and G4 of transistors T2 and T4 remain at "0".
It remains as it is. Transistors T1, T4 are therefore conducting, T2, T3 are non-conducting, and current pulses are applied to the coils of motor 6. In this example, the pulses last approximately 2 ms, which is short enough so that the motor is not rotated, yet long enough to be pulsed in a device based on the principle of detecting stray magnetic fields of the motor.

The operation of the logic circuit 10 of FIG. 1, that is, the operation of applying a signal to quickly measure the progress of the clock when the stem is in the third position, will be explained with reference to FIG. FIG. 2 is a waveform diagram of signals appearing in each part of this circuit.

When the stem is in the third position for this measurement, the switch 9 of the switching means is closed and an interrogation signal "1" is applied to the input 7L of the adjustment circuit 7. This adjustment circuit 7 is configured not to operate when its input 7L is "1", and the frequency divider 2 operates without adjusting the frequency division ratio.

Input 1 from the outputs of two different stages of frequency divider 2
For example, signals of 1 Hz and 256 Hz are applied to 0a and 10b, respectively.

The output 11c of the AND gate 11 periodically outputs a pulse train of half a quarter second, each pulse width being approximately 2 ms.

These pulses are applied to the input 19b of the gate 19 while being counted by a counter. These pulses are transmitted through the output terminal 19c of the gate 19 as long as the output of the flip-flop 18 is "1".
It is supplied to the data output terminal 10d.

The state of the output 17a of the frequency division stage of the counter 17 is
The comparator 16 compares the state of the output 18m of the memory 8 with the state of the output 18m of the memory 8, and if these states match, that is, if the number of pulses counted by the counter 17 matches the number stored in the memory 8, the output is 16c
changes from “0” to “1” and flip-flop 1
The state of the output Q of 8 changes, and becomes “0” and “0”, respectively.
It becomes “1”. This change resets the counter to zero, closes gate 19, and the signal from output 11c no longer reaches output 10d.

At the end of a new half-quarter second, flip-flop 18 is reset by the signal at input 10b and the signal resetting counter 17 disappears. Therefore, the counter 17 can count new pulse trains. Also, at the same time,
Input 19a becomes "1" again, allowing this new pulse train to pass through gate 19.

Therefore, one pulse train is applied from the output terminal 10d to the data input terminal 4e of the switching means 4 every quart second. The number contained in each pulse train is equal to the number stored in memory 8. For example, in FIG. 2, it is 5. The frequency of these pulses depends directly on the actual frequency of the oscillator 1. The time interval between the beginnings of two consecutive pulse trains also directly depends on the actual frequency of the oscillator 1. As previously mentioned, these pulse trains form the measurement signal applied to the coils of the stepper motor.

FIG. 2 illustrates the case where the memory 8 stores the number "5" and therefore the measurement signal (10d/4e) consists of five pulses in each pulse train.
It will be recalled that in this example, the number "5" stored in the memory 8 represents the number of pulses that are suppressed in the pulses supplied from the oscillator to the frequency divider 2 during each regulation cycle. sea bream.

The progress of this kind of prohibited clock can be calculated from the following formula:

m(s/d)=86400(P-1+N× ^10-6 /4.194304
) Here, m is expressed in seconds per day (s/
d) the rate of advance of the clock, P is the period of the pulse train of the measurement signal 4e, N is the number of pulses included in each pulse train of the measurement signal 4e, i.e. the number of pulses suppressed from the output pulse of the oscillator in each adjustment cycle,
86400 is the number of seconds in 24 hours, 4.194304× ¹⁰⁶ is 3726Hz
(oscillator frequency) and 128s (adjustment cycle period).

For example, in the case of P=0.9999904s and N=50, m=86400 (0.9999904-1 +50×10 ^-6 /4.194304)=0.2s/d. A device for measuring the progress of a clock equipped with the electronic diagram shown in the figure was developed. This measuring device is described in a Swiss patent application dated November 24, 1978.

The method of transmitting the measurement signal outside the watch is different from that described above. For example, the measuring signal can also be transmitted acoustically by an electronic alarm device of the watch. It is also possible to form the measuring signal in a different way, in which the contents of the memory of the adjustment circuit for frequency division factor adjustment are introduced in the form of a code.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is a circuit diagram specifically showing the circuit shown in Fig. 1. be. 1... Quartz oscillator, 2... Frequency divider, 3...
Pulse shaping circuit, 4... Selector switch circuit, 5...
...Control circuit, 6...Step motor, 7...Adjustment circuit, 8...Memory, 9...Interrogation stage, 10...
...Logic circuit, 11...AND gate, 16...Comparator, 17...Counter, 18...Flip-flop, 19...AND gate.

Claims (1)

[Scope of Claims] 1. An electronic timepiece having an oscillator that generates a high frequency time standard signal, an adjustable frequency division ratio, and generating a low frequency time standard signal in response to the high frequency time standard signal. a frequency divider, a memory that stores a value related to the frequency division ratio, a member that generates an inquiry signal in response to manual operation, and a member that generates an inquiry signal in response to a manual operation; An adjustment circuit for adjusting the frequency division ratio is not adjusted when an interrogation signal is present, and a logic circuit coupled to the frequency divider and the memory to generate a measurement signal. The repetition frequency of the pulses of the signal is dependent on the high frequency time standard signal, the number of pulses is dependent on the stored value, and a changeover switch circuit is provided for applying the measurement signal to the transducer in response to the interrogation signal. characterized in that the transducer emits a signal wave representing the measurement signal in response to the measurement signal, and the signal wave is detectable by an external device for measuring the progress of the electronic clock. electronic clock. 2 a pulse shaping circuit connected to the frequency divider and generating control pulses in response to the low frequency time standard signal;
A control circuit is provided for generating drive pulses in response to the control pulses, and the transducer is a step motor, and a coil of the step motor is connected to the control circuit, and the step motor generates time information in response to the drive pulses. further, when the inquiry signal is not present, the changeover switch circuit applies a control pulse to the control circuit;
Claim 1, wherein the duration of the pulse included in the measurement signal is short enough not to rotate the step motor, but long enough to cause the coil to emit a magnetic wave detectable by an external measuring device. electronic clock. 3. An electronic timepiece according to claim 1, wherein the transducer is an electro-acoustic transducer and generates electro-acoustic waves detectable by an external measuring device.