JPS6315626B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a memory access control system, and particularly to a memory access control method for accessing a memory shared area by a plurality of asynchronous processors in a multiprocessor system in an information processing system. Related to memory access control methods.

[Prior art]

In the conventional memory access control system, a single bus system configuration in which a plurality of processors and storage devices are connected to a single common bus is known as one system configuration method for a multiprocessor system.

These processors use the shared area in the storage device while mutually exercising exclusive control. For example, data or a table stored in a storage device can be used and modified by several processors accessing the table at different times.

Exclusive control is normally performed as follows.

When a processor accesses a shared area, it reads and confirms exclusive control information indicating whether the shared area is being used by another processor. The exclusive control information is stored in an area different from each shared area in the storage device, corresponding to each shared area.

If the exclusive control information is not set, the shared area is in an "empty" state that is not used by any processor, that is, the shared area is not locked, so the exclusive control information must be set. prevent processors from accessing the shared area before using the shared area.

When the use of the shared area is finished, the processor resets the exclusive control information in order to make the shared area available to other processors.

If the exclusive control information has been set, the shared area is being used by another processor, that is, the shared area is locked, so use of the shared area is temporarily given up. Thereafter, the exclusive control information is read at an appropriate period and waits until the exclusive control information is reset and the shared area is released.

In these types of systems, when a processor attempts to access a locked shared area, it stores a memory in memory to determine whether the shared area has become ``empty.'' It is necessary to continue reading the exclusive control information periodically.

Therefore, if a shared area is frequently accessed by multiple processors, the read operations of exclusive control information from the processors will be concentrated on the common bus, increasing the load on the common bus and disrupting the normal system performance. This has the drawback of hindering the use of a common bus to perform the functions of the system, thereby degrading the performance of the entire system.

In other words, the conventional memory access control method is
Since the common bus is exclusively used for reading exclusive control information, there is a drawback that the efficiency of using the common bus is reduced.

[Purpose of the invention]

An object of the present invention is to provide a memory access control method that can improve the efficiency of using a common bus.

That is, an object of the present invention is to store exclusive control information regarding a shared area in a storage device accessed by a plurality of processors in a storage unit in each processor in a single bus type multiprocessor system, and to By equipping each processor with a control circuit that synchronizes and updates exclusive control information between processors, it is possible to eliminate the need to inquire whether the shared area is unlocked when the shared area is locked. It is an object of the present invention to provide a memory access control method for a shared area that solves the above-mentioned drawbacks by making it possible to determine exclusive control information by checking the storage section inside a processor, and that allows a common bus to be used effectively as a system. be.

[Structure of the invention]

The memory access control method of the present invention includes: a storage device having at least one shared area accessed by a plurality of processors; and a storage unit storing exclusive control information for exclusive use of the shared area among the processors. a plurality of processors each having a control section that synchronously updates exclusive control information stored in the storage section; and an interrupt circuit that generates an interrupt when the exclusive control information is updated by the control section; and a common bus connecting the plurality of processors.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a bit configuration diagram of an update instruction used in the embodiment shown in FIG. 1.

The memory access control system shown in FIG. 1 is composed of processors 1 and 2, storage devices 3 and 4, a bus control device 5, and a common bus B that connects them.

The storage device 3 has a shared area c3, and the storage device 4 has a shared area c4. Furthermore, since processors 1 and 2 have the same configuration, only processor 1 is shown in detail in FIG. These processors 1 and 2 have shared areas c3 and c4 in storage devices 3 and 4.
a storage circuit 22 that stores exclusive control information for exclusive use between the processors 1 and 2; an update control unit 21 that synchronously updates the exclusive control information stored in the storage circuit 22; Control unit 21
The processor 1 is comprised of an interrupt generation circuit 23 that generates an interrupt when updated by the processor 1 or 2, and a control section 24 that controls the entire processor 1 or 2.

Further, in the common bus B, control signal lines 9 and 10 are 1-bit control signal lines, data line 6 is a 32-bit data line, address line 7 is a 16-bit address line, and control signal line 8 is a processor line. between processors 1 and 2 and between processors 1 and 2 and storage device 3,
This is an 8-bit control signal line for transferring information between data lines 6 and 4 via data line 6.

The update control section 21 in the processor 1 has a reception signal line 9 for receiving control signals supplied through the control signal lines 9 and 10 forming the common bus B.
b, 10b, and transmission signal lines 9a, 1 that perform transmission so as to supply control signals to the control signal lines 9, 10.
0a, a selection signal line 150 for controlling the reading of exclusive control information of the shared area and controlling the selection circuits 103 and 104, and an OR for outputting the logical sum of the control signals supplied from the reception signal lines 9b and 10b. circuit 130, and a write instruction circuit 131 which receives the output of this OR circuit 130, outputs logic "1" in the next step after logic "1" is set, and outputs logic "0" in the subsequent steps. The write signal output from the write instruction circuit 131 causes the write control and selection circuit 10 to control the write to the memory circuit 22.
2, a write signal line 141 for controlling the
Output from the OR circuit 130 and the selection signal line 15
OR circuit 132 whose input is the signal supplied to
, a read signal line 142 that performs read control of the memory circuit 22 by a read signal that is the output of this OR circuit 132, a receive signal line 6b that performs reception from the data line 6 that constitutes the common bus B, and this data line. 6, a 32-bit input register 101 that holds data on the receive signal line 6b, and a 12-bit connection line 120 when the write signal line 141 is at logic "0". a selection circuit 102 which outputs the lower 12 bits on the reception signal line 6b through the input register 101 and outputs the lower 12 bits of the input register 101 through the 12-bit connection line 121 when the logic is "1"; When the line 150 is logic "0", the upper 8 bits and lower 4 bits of the output of the selection circuit 102 are outputted via the 8-bit and 4-bit connection lines 122 and 123, and when the line 150 is logic "1", the 8 bits and 4 bits are output. Bit connection line 1
Selection circuits 103 and 104 respectively output the upper 8 bits and lower 4 bits of the lower 12 bits on the transmission signal line 6a through 24 and 125.
and a decoder circuit 105 that decodes the 4-bit data of this selection circuit 104, and when the reception signal line 9b is at logic "1", the decoder circuit 105
The output of the register 108 is logically ORed with the contents of the register 108 for each bit, and when the received signal line 10b is at logic "1", an exclusive OR operation is performed for each bit, and the 16 bits are stored in the memory circuit 22. an 8-bit address signal line 140 that indicates address information to the storage circuit 22 that is output from the selection circuit 103;
, a 16-bit register 107 that holds the output from the decoder circuit 105, a 16-bit register 108 that holds one word of data read from the memory circuit 22, and this register 107,
AND-OR circuit group 109 which performs an AND operation on the 16-bit data of 108 and takes the logical sum of the result, and the selection signal line 150 and the AND-OR circuit group 109;
AND circuit 1 whose input is the output of circuit group 109
10, and an output signal line 111 from the AND circuit 110 to the control section 24.

Furthermore, the memory circuit 22 is composed of a memory circuit consisting of 256 words, each word being 16 bits, and the interrupt generating circuit 23 is configured to perform a process when the selection signal line 150 is set to logic "1". A 32-bit register 160 that holds the data on the transmission signal line 6a, and an exclusive OR that performs an exclusive OR of the contents of this register 160 and the contents of the input register 101 and notifies the control section 24 of the output. It is composed of a logical OR circuit 161.

In the embodiment shown in FIG. 1, the address line 7 and the control signal line 8 that constitute the common bus B
Configuration within processors 1 and 2 and common bus B
Driver and receiver circuits for transferring information upward are omitted.

In addition, exclusive control information is expressed as 1-bit information for one shared area, and a logic "1" indicates that it is locked, and a logic "0" indicates that the lock has been released. do.

Hereinafter, the operation of each circuit will be explained in accordance with the procedure for accessing the shared area by the processor 1.

From the control unit 24 to the shared area c in the storage devices 3 and 4
When a request for access to 3, c4 occurs, the processor 1 acquires the right to use the common bus B from the bus control device 5, which determines the right to use the common bus B, as a first step.

Next, in order to read the exclusive control information corresponding to the shared areas c3 and c4 stored in the storage circuit 22, the control unit 24 sets the selection signal line 150 to logic "1", and at the same time sets the selection signal line 150 to the transmission signal line 6a, Selection circuits 103 and 10 via connection lines 124 and 125
Update command 2 whose structure is shown in FIG.
Send 00.

The update instruction 200 shown in FIG.
It includes address information 201 consisting of 8 bits 20 to 27, which indicates address information necessary to control writing and reading to a specific word of the storage circuit 22 shown in the figure. Furthermore, the update instruction 200 is decoded by the 4-bit decoder circuit 105 shown in FIG. It includes bit position information 202 consisting of bits.

Therefore, the address information 201 of the update instruction 200
and bit position information 202, the memory circuit 22
Any bit position can be specified.

By setting the selection signal line 150 to logic "1", the read signal line 142 of the storage circuit 22, which is the output of the OR circuit 132, becomes logic "1", and the selection circuits 103, 104 connect the connection lines 124, 1
Update command 200 on transmission signal line 6a via 25
The upper 8 bits and lower 4 bits of the lower 12 bits are selected respectively. The output of the selected upper 8 bits is set to the address signal line 140 to the storage circuit 22. As a result, the memory circuit 2 that the processor 1 is trying to access
The specific word storing the exclusive control information within 2 is read into register 108.

On the other hand, the output of the selected lower 4 bits is
It is decoded by the decoder circuit 105. The decoding result indicating that the bit position corresponding to the exclusive control information in the specific word is logic "1" is stored in register 10.
It is held at 7.

Next, in the second step of determining the operation of processor 1 based on the read exclusive control information, the contents of registers 107 and 108 are AND-ORed.
The calculation is performed by the circuit group 109, and the calculation result is further calculated by the AND circuit 110 with the signal supplied to the selection signal line 150, and the output signal line 11 is
1 to the control unit 24. Since the selection signal line 150 is in the logic "1" state, if the shared areas c3 and c4 are locked, the bit position corresponding to the exclusive control information of the shared areas c3 and c4 in the register 108 will be The logic becomes "1", and the AND-OR circuit group 109 and AND
The output of circuit 110 indicates a logic "1" state.

Further, if the shared areas c3 and c4 are not locked, the bit positions corresponding to the exclusive control information of the shared areas c3 and c4 are in the logic "0" state, so the output of the AND circuit 110 is the logic "0". shows.

In this way, the control unit 24 can know whether or not the shared areas c3 and c4 are locked based on the state of the output signal line 111.

Next, the control section 24 sets the selection signal line 150 to a logic "0" state so that data will not be set in the register 160 thereafter. Further, when the output signal line 111 detects a logic "0" state, the transmission signal line 9a is set to prevent other processors from accessing the shared areas c3 and c4, and the update command 200 is notified to each processor. , if a logic "1" state is detected, the right to use the common bus B is relinquished.

Since the right to use the bus is acquired during the operations of steps 1 and 2 described above, while the exclusive control information stored in the memory circuit 22 is being referred to by the processor 1, it will not be updated by other processors.

Therefore, exclusive access to the shared area can be achieved.

Further, if the shared area is not locked and access to the shared areas c3 and c4 is completed after notifying each processor of the update command, the control unit 24 sets the transmission signal line 10a and repeats the above process again. The same update command 200 is notified to each processor.

As a result, the shared area c by other processors
3 and c4 become possible, and all operations related to access to the shared areas c3 and c4 are completed.

Next, an update command is notified from another processor,
The operation when setting and resetting the exclusive control information will be explained using the processor 1.

The update command indicates information for setting this exclusive control information when the reception signal line 9b is set, and indicates information for resetting this exclusive control information when the reception signal line 10b is set. show.

First, when the receive signal line 10b is set and the update command 200 is notified, the first step is that the receive signal line 10b becomes logic "1" and the update command is set in the input register 101 via the receive signal line 6b. Then, the output of the OR circuit 130 is logic “1”
Therefore, the read signal line 142 that supplies the output of the OR circuit 132 shows a logic "1" state,
This logic “1” is input to the write instruction circuit 131.

Since the write instruction circuit 131 outputs the logic "1" in the next step after the logic "1" state is input, the write signal line 14 is output in this step.
1 indicates logic "0".

Therefore, writing to memory circuit 22 is blocked.

Also, the update command is sent to the lower order 12 via the connection line 120.
Bit data is input to the selection circuit 102, and the selection circuit 10 is controlled by the write signal line 141.
2 selects data on the connection line 120 side. Further, the selection signal line 150 is normally in the state of logic "0", and the selection circuit 103 is connected to the 8-bit connection line 122.
In order to select data on the side, the upper 8 bits of the lower 12 bits of the update command on the received signal line 6b are set on the address signal line 140. As a result, under the control of the read signal line 142, a specific word containing exclusive control information of the shared area that another processor attempts to unlock is read into the register 108.

In the second step, the write instruction circuit 1
31 outputs logic "1". Since the write signal line 141, which is the output thereof, becomes a logic “1” state,
The selection circuit 102 selects the data on the 12-bit connection line 121. Further, since the selection signal line 150 is in the logic "0" state, the selection circuits 103 and 104 select the data on the connection lines 122 and 123. Therefore, this time, the lower order of the update instruction in the input register 101
The upper 8 bits of the 12 bits are the address signal line 140.
Then, the lower four bits are input to the decoder circuit 105.

The decoding result from the decoder circuit 105 is output to the update circuit 106 with the same bit position as the exclusive control information corresponding to the shared areas c3 and c4 in the specific word indicating a logic "1" state. Also, the shared areas c3 and c4 of the register 108 are locked. That is, it holds a specific word in which the bit position corresponding to the exclusive control information is in a logic "1" state. Since the received signal line 10b is at logic "1", the update circuit 106 performs an exclusive OR of the contents of the decoding result and the contents of the register 108. As a result, an output in which the bit position corresponding to the exclusive control information in the specific word is in a logic "0" state, that is, an output in which the shared areas c3 and c4 are unlocked, is input to the storage circuit 22.
Furthermore, the write signal line 141 and the address signal line 1
40, the unlocked data in the shared areas c3 and c4 is written to the same location as the specific word in the memory circuit 22, and the resetting of the exclusive control information by the other processors is completed.

Also, at this time, the contents of the input register 101 and the register 160 are calculated by the exclusive OR circuit 161, and the output thereof is notified to the control unit 24. As described above, in the register 160, when the processor 1 attempts to access the shared areas c3 and c4, the selection signal line 150 is set to logic "1" by the control unit 24, so the transmission signal line 6a is set to logic "1". An update command that specifies exclusive control information for shared areas c3 and c4 is held through the storage area.

On the other hand, the input register 101 holds an update instruction that specifies exclusive control information of a shared area that another processor attempts to unlock.

Therefore, when the output of the exclusive OR circuit 161 indicates logic "0", the control unit 24 indicates that the shared area to be accessed has been unlocked.
Further, when the logic "1" is shown, it can be known that the lock is not released yet. Therefore, if the shared area that the processor 1 attempts to access is locked, it is only necessary to try to access it again if the output of the exclusive OR circuit 161 indicates a logic "0" state. Become.

Next, the operation when an update command is notified from another processor together with the reception signal line 9b will be described.

In this case, the update command is sent to the receiving signal line 10b indicating information for setting exclusive control information corresponding to the shared area that another processor attempts to access.
is replaced with the receiving signal line 9b and the receiving signal line 9b becomes the logic "1" state.
The update circuit 106 performs an OR operation and the output thereof is written to the memory circuit 22, but the same operation as in the case where an update command is notified together with the reception signal line 10b by the other processor described above is performed.

In the above-mentioned OR operation, the register 108 stores the memory circuit 2 that stores exclusive control information corresponding to the shared area that other processors attempt to access.
2 specific words are being read. Further, as the output result of the decoder circuit 106, the same bit position as the exclusive control information corresponding to the shared area that the other processor is trying to access in the specific word is output as logic "1".

Therefore, the bit position is set to a logic "1" state by the OR operation, and data in which exclusive control information corresponding to the shared area is set is output to the storage circuit 22. Then, since the output data is written to the same position as the specific word in the memory circuit 22, the setting of exclusive control information by the other processor is completed.

In the above, the update command shown in FIG. 2 is used as a means for updating the exclusive control information, but if the means can update the desired exclusive control information at the same time, the update command may not be used. It is clear that this is also possible.

Further, in the above embodiment, there are two processors.
Although the case of three or more processors is shown, it is clear that the same method can be applied even if the number of processors is three or more.

〔Effect of the invention〕

In the memory access control method of the present invention, each processor is equipped with a memory circuit that stores exclusive control information regarding the shared area. This has the effect that the common bus can be used effectively as a system without continuing to uselessly occupy the common bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a bit configuration diagram showing the bit configuration of an update instruction used in the embodiment shown in FIG. 1, 2...processor, 3, 4...storage device,
5...Bus control device, 6...Data line, 7...Address line, 8-10...Control signal line, B...Common bus, c3, c4...Shared area, 21...Update control unit, 22 ...Storage circuit, 23...Interrupt generation circuit, 24...Control unit, 6a, 9a, 10a...Transmission signal line, 6b, 9b, 10b...Reception signal line,
101...Input register, 107, 108, 16
0...Register, 102-104...Selection circuit,
106...Update circuit, 105...Decoder circuit,
109...AND-OR circuit group, 110...AND
Circuit, 130, 132...OR circuit, 161...
Exclusive OR circuit, 131...Write instruction circuit, 11
1... Output signal line, 120-125... Connection line,
140...Address signal line, 141...Write signal line, 142...Read signal line, 150...Selection signal line, 200...Update command, 201...Address information, 202...Bit position information.

Claims (1)

[Claims] 1. A storage device having at least one shared area that is accessed by a plurality of processors; a storage unit that stores exclusive control information for exclusive use of the shared area between processors; and a storage unit that stores exclusive control information for exclusive use of the shared area among the processors; A plurality of processors each having a control unit that synchronously updates exclusive control information and an interrupt circuit that generates an interrupt when updated by the control unit, the storage device, and the plurality of processors. A memory access control method characterized by comprising a common bus.