JPS6315678B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a CMOS dynamic read-only semiconductor memory device (hereinafter referred to as CMOS dynamic ROM).
(referred to as ).

Conventional CMOS dynamic ROMs often use N-channel enhancement type transistors in the main memory section (Figure 1 shows a series connection type, but a parallel connection type is also available), as shown in Figure 1. The memory is accessed by making the N-channel transistor conductive in the saturation region. Address signal input terminals 1 to 1
1 is a positive logic input, the address signal is latched by the first address latch group A and the second address latch group B, and its output is input to the first address decoder E and the second address decoder F. . Address decoders E and F perform decoding in synchronization with clocks input from a first synchronizing clock input terminal a and a second synchronizing clock input terminal b, respectively. The output terminal 12 of the first address decoder E is connected to the transistor group G of the main body of the memory section.
As a result, an output is obtained from the ROM output terminal 13. Note that B1 is the output terminal of the first power supply.

FIG. 2 shows a conventional example in which the main body of the storage section is constructed by connecting P-channel enhancement type transistors in series, and is driven by two power supplies. B1,
B2 are output terminals of the first and second power supplies, respectively. The output voltage of the first and second power supplies is set to V
1, V2, and the threshold voltage of the P channel transistor is V _TP , especially |V2|>|V1|+
If each voltage is set so that |V _TP |, the P-channel transistor in the storage section operates in a non-saturation region, so carrier mobility increases and the ON resistance of the transistor decreases. However, the responses of address decoders E and F are slower than when N-channel transistors are used. 1'～1
1' negative logic address signal input terminal. Synchronization clock input terminals a', b', address decoder E output terminal 12', ROM output terminal 13', etc.
These are signal terminals with the opposite logic to the corresponding numbers or symbols in FIG. D is the amplitude of the synchronization clock |
This is a static level shifter for increasing the width of V2.

The present invention selects the advantages of the above-described conventional examples and improves their shortcomings.In principle, it is possible to operate an N-channel depletion transistor in a non-saturation region using two power supplies. It is characterized by
Realizes a fairly small transistor ON resistance,
As a result, the purpose is to significantly shorten access time.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. FIG. 3 shows an embodiment of the present invention in which an N-channel depletion transistor is used in the main body of the storage section, and the same numbers and symbols as in FIG. 1 indicate the same components. Also, the output terminal B of the second power supply
2 and static level shifter D are the same as in FIG. If the threshold voltage of an N-channel depletion transistor is V _TN , then between the output voltages V1 and V2 there is |V2|>|V1|+
There is a relationship of |V _TN |. In particular, in low power consumption systems using silver batteries, the output voltage of the silver battery is set to V1.
The output voltage V2 may be obtained by doubling the output voltage V1 using a booster circuit. The amplitude of the signal applied to address signal input terminals 1 to 7 is
The signal is amplified from |V1| to |V2| by the dynamic level shifter group C, and latched by the address latch group A. The output of address latch group A driven by output voltage V2 becomes the input of address decoder E, which is also driven by output voltage V2. Generally, a large load is applied to the output terminal 12 of the address decoder E, so its drivability has a large effect on the access speed. In particular, when |V2|=2|V1|, simply calculating the drivability of address decoder E becomes four times as large. Furthermore, the transistor group G in the main body of the storage unit operates in a non-saturation region when conductive due to the relationship |V2|>|V1|+|V _TN |. Therefore,
The carrier mobility increases compared to the case in Figure 1,
Furthermore, since the transistor is of a depletion type, it is in a deeper ON state for the same gate potential (ground level) than in the case of FIG. 1. For the above reasons, the transistor group G in the main body of the memory section
The ON resistance can be made much smaller than in the case of FIG. In particular, when |V1|=1.5, |V2|=3V,
ON by setting an appropriate threshold voltage
It is considered that it is not difficult to reduce the resistance to about 1/4. Regarding power consumption, the same capacity
In the case of a ROM, the load on the output terminal 12 of the address decoder E can be reduced by increasing the number of series stages of the transistor group G in the main body of the storage unit, so the increase will not be large. Also,
In terms of area on the pattern, level shifter group C
The ratio of the level shifter D and the level shifter D to the whole is generally very small.

As explained above, according to the present invention, with a slight increase in current consumption and area, efficient
The ROM access time can be shortened, and it can be applied to faster systems, systems that require larger ROM capacity, etc.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional CMOS dynamic ROM, respectively, and FIG. 3 is a block diagram of an embodiment of the present invention. 1 to 11...Address signal input terminal, 12...
First address decoder output terminal, 13...
ROM output terminal, a...first synchronization clock input terminal, b...second synchronization clock input terminal,
A...First address latch group, B...Second address latch group, C...Dynamic level shifter group, D...Static level shifter, E...
First address decoder, F...second address decoder, G...transistor group of the main body of the storage section.

Claims (1)

[Claims] 1. Two power supplies, a first and a second power supply, and a first address of a synchronization input terminal that is connected to the second power supply and receives the output of the first address latch group. a decoder, a second address latch group connected to the first power supply, and a second address with a synchronization input terminal receiving the output of the second address latch group and a second synchronization clock as inputs. a decoder;
a memory main body composed of a group of depletion type transistors, connected to the second address decoder and receiving the output of the first address decoder as input; The depletion type transistor in the memory main body selected by the first address recorder and the second address recorder is operated in a non-saturation region by making the absolute value of the power supply voltage smaller than the absolute value of the power supply voltage. A semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the depletion type transistor is an N-channel type.