JPS6316908B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a one-dimensional or two-dimensional solid-state imaging device.

[Background of the invention]

FIG. 1a shows an example of the basic configuration of a two-dimensional solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 53-122316, etc.
FIG. 1b shows an example of a timing chart of horizontal scanning pulses and vertical scanning pulses. In Fig. 1a, 1 and 2 are horizontal and vertical scanning circuits, respectively, and normally clock pulses CPx, CPy of 2 to 4 phases are provided.
By applying , the input pulses Vsx and Vsy are shifted by a certain timing time of the clock, and the output pulse train Vox1, Vox shown in Fig. 1b is obtained.
2..., Voy1, Voy2... are output to the output lines Ox1, Ox2..., Oy1, Oy2... of each stage of the scanning circuit. This pulse train sequentially opens and closes the switching elements 5 and 6, and the signals from the individual photoelectric conversion elements 3 arranged two-dimensionally are output onto the video output line 4. Since the signal from the photoelectric conversion element corresponds to the optical image projected thereon, a video signal can be extracted by the above operation.

This type of solid-state imaging device requires about 500 x 500 photoelectric conversion elements, switching elements, and scanning unit circuits to obtain high resolution. Therefore, it is usually relatively easy to achieve high integration, and the photoelectric conversion element and switching element can be integrated into one structure.
Manufactured using MOS-LSI technology. Figure 2 shows the schematic structure of a photoelectric conversion element that occupies most of the area of a solid-state imaging IC. 13 is a semiconductor substrate of one conductivity type, and 5 and 6 are switches consisting of insulated gate field effect transistors (hereinafter referred to as MOS transistors) for selecting horizontal and vertical positions, respectively.
It is made up of diffusion layers 7, 10, 15 of the opposite conductivity type to the substrate 13, which form a drain or source, and gate electrodes 9, 14 provided through an insulating oxide film 8. 10 or a photodiode using the source of a MOS transistor 6 which serves as a vertical switch. Output pulses Vox (N) and Voy (N) of scanning circuits 1 and 2 using shift registers made of MOS transistors, etc.
The video voltage 11 charges the diode 10 where the voltage is simultaneously applied to the gate of the MOS switch through the output lines Ox(N) and Oy(N) with the amount of charge that had been discharged in proportion to the amount of incident light. The charging current at that time is detected as a video signal through the load resistor 12.

Now, FIG. 3 again shows a circuit schematic diagram of the conventional solid-state image sensor, which is the same as FIG. 1. In an actual solid-state image sensor, the layout (position) of photodiodes and signal lines (mainly vertical signal line 7) on the semiconductor
Due to this relationship, a parasitic capacitance indicated by Cf in FIG. 3 is sure to occur. The negative effects of this parasitic capacitance Cf will be described below.

FIG. 4 is a schematic diagram of a monitor using a conventional solid-state image sensor.
It is assumed that strong light is irradiated onto a part 41 of the area. At this time, even if the amount of incident light does not exceed the saturation amount of light of the solid-state image sensor, on the image 41 being monitored,
Thin pseudo signal (smear signal) in the lower area 42
is observed. One of the causes of this smear signal is the parasitic capacitance Cf. That is, when light enters the area 41, the potential of the photodiode decreases depending on the amount of light. This potential fluctuation of the photodiode is transmitted to the vertical signal line 7 (FIG. 3) through the parasitic capacitance Cf. Therefore, in FIG.
During the time when the signal of the photodiode in the area 41 is being read out, the change in the photodiode in the area 41 caused by the light irradiation in the area 41 is mixed with the desired signal through the parasitic capacitance Cf, and as a result, a pseudo signal is generated in the area 42. Can be seen.

[Purpose and outline of the invention]

According to a simple calculation, the pseudo signal Ns caused by the parasitic device Cf is expressed by the following equation using the storage capacitance Cs of the photodiode.

Ns∝Cf／Cs＋Cf (1) Here, the capacitance Cv of the vertical signal line is generally Cv≫Cs,Cf (2) So I ignored it.

From equation (1), in order to suppress the pseudo signal Ns mentioned above, a photodiode and a signal line (mainly vertical signal line) are required.
It can be seen that it is effective to reduce the parasitic capacitance Cf between

FIG. 5 is a cross-sectional view of a picture element of a solid-state image sensor. In order to reduce the parasitic capacitance Cf, it is effective to insert an electrical shield plate between the vertical signal line 30 connecting the photodiode 10 and the drain 70 of the vertical switch MOS transistor 6.

The present invention provides a solid-state image sensor in which an electric shield plate is inserted between a photodiode and a signal line to drastically reduce false signals and obtain high-quality images.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 6 to 11.

FIG. 6 shows an embodiment of the invention. In the figure, 10
is a photodiode with an n ⁺ layer, 70 is an n ⁺ layer attached to the vertical signal line, and 30 is a vertical signal line connecting the n ⁺ layer 70 attached to the vertical signal line of each photodiode, and is made of aluminum, for example.
8 and 8' are silicon dioxide, and 13 is a p-type silicon substrate. Further, 61 is a p-type silicon substrate or an n-type silicon substrate. If 61 is n-type silicon, photodiode 10 and p-type silicon 1
3 and n-type silicon 61 constitute an npn bipolar transistor, which functions to absorb excess charge generated in the photodiode. When 61 is p-type silicon, 13 and 61 may be the same or have different impurity concentrations. The same applies to the following drawings, but whether 61 is p-type or n-type has no direct relation to the principle of the present invention.

The key point of the present invention is to insert an electrical shield plate 60 between the photodiode 10 and the signal line 30 in FIG. This shield plate 6
0 is formed of a metal such as aluminum, molybdenum, or tungsten, or a semiconductor such as polycrystalline Si, single crystal Si, or amorphous Si, or a combination thereof. Even if the shield plate 60 is an insulator, if it is made of a material with a low dielectric constant, the coupling capacitance between the photodiode 10 and the signal line 30 will be reduced, and the characteristics of the optical sensor will be improved.

Now, regarding the potential of the seal plate 60, the signal line 3
Even if it is not connected to 0 or the photodiode 10, as long as it is not electrically floating,
In principle, the potential of the shield plate 60 may be any value. For example, it may be connected to a DC voltage, to the vertical gate line 14, or even to the n-type substrate 61.

However, if the shield plate 60 is made of an insulator, it will be in an electrically floating state, but as described above, the parasitic capacitance Cf will be reduced, so the present invention will still be effective.

FIG. 7 shows another embodiment of the invention. In this figure, the shield plate 60 is made of polycrystalline silicon, molybdenum, etc.
After this is formed, the n ⁺ layer 70 accompanying the photodiode 10 and the signal line is formed. In this embodiment, a suitably high DC voltage is applied to the shield plate 60, and the inversion layer 71 formed under the shield plate 60 serves as a photodiode (mainly for storage). Of course, the order of forming the vertical gate line 14 and the shield plate 60 in FIG. 7 may be reversed.

FIG. 8 shows another embodiment of the invention.
FIG. 8a is a sectional view of a sensor for a single-plate color camera. (ISSCC Digest 1980, Aoki, Ohba,
Kubo, et al.) In the figure, 80 is a light shield plate provided between the two signal lines 30 and 30' to prevent direct light from being irradiated, and is made of, for example, aluminum.

FIG. 8b shows an embodiment of the invention. In this embodiment, the signal lines 30, 30' and the optical shield line 80 in the conventional example shown in FIG. It also serves as That is, conventionally (Fig. 8a) signal line 3
0 and 30', the optical shield plate 80 was formed, but in this example (FIG. 8b),
After forming the electrical and optical shield plate 81, the signal line 30 is formed.

FIG. 9 shows another embodiment of the invention. FIG. 9a shows a so-called double-decker optical sensor (IEDM Digest 1979, Tsukada et al.). This is a conventional solid-state image sensor with an electrode 92, an amorphous film 91 such as Sachicon, and a transparent electrode 90. Even in this case, the parasitic capacitance shown by Cf in the figure deteriorates the image quality. ing.

FIG. 9b shows another embodiment of the present invention that improves this, in which an electric shield plate 93 is inserted between the photodiode electrode 92 and the signal line 30.

In the above explanation, an n-channel element has been described, but the effectiveness of the present invention is not lost even in a p-channel element. Furthermore, the present invention is applicable not only to silicon devices but also to germanium devices and compound semiconductor devices. Of course, a one-dimensional optical sensor may also be used.

〔Effect of the invention〕

As described above, in the present invention, the coupling capacitance between the photodiode and the signal line is reduced by inserting an electric shield plate between them, and high image quality can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing a solid-state image sensor, FIG. 2 is a cross-sectional view schematically showing the structure of one bit of the solid-state image sensor, FIG. 3 is a diagram explaining the parasitic capacitance of the solid-state image sensor, and FIG. FIG. 4 is a diagram explaining a smear signal, FIG. 5 is a cross-sectional view showing the pixel structure of a solid-state image sensor, and FIGS. 6, 7, 8, and 9 are solid-state diagrams showing embodiments of the present invention. FIG. 2 is a cross-sectional view of a pixel structure of an image sensor. 13... p-type Si substrate, 10... photodiode (n-type layer), 70... n-type layer, 14... gate electrode, 30... vertical signal output line, 60... shield, 8, 8'... ...Insulating film, 301...Amplifier.

Claims (1)

[Claims] 1 Semiconductor substrate for photodiodes and switches
In a solid-state imaging device having a signal output line consisting of a conductor layer in which a plurality of picture elements consisting of a MOS transistor and the drains of the switch MOS transistors in the same column are commonly connected, between the conductor layer and the photodiode, A solid-state imaging device characterized by being provided with an electrical shield to reduce parasitic capacitance between them.