JPS6317190B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor integrated circuit test and evaluation device (hereinafter referred to as IC tester) that enables a first-fail-stop function in simultaneous parallel measurement of two or more samples (hereinafter referred to as multi-measurement). ).

In general, evaluation tests for semiconductor integrated circuits (hereinafter referred to as IC) include direct current characteristics tests (hereinafter referred to as DC tests), functional tests, and alternating current characteristics tests (hereinafter referred to as AC
In each of these test items, in order to protect the power supply circuit and drive circuit of the IC tester, or to shorten the test time, tests are not performed after a failure occurs, and tests are performed first. - A fail-stop method is used.

This first fail stop means that in the functional test for the above test item, when a defect is detected during pattern running, the subsequent pattern running is interrupted and the process proceeds to the next test item (hereinafter referred to as NGP mode). , consists of two modes (hereinafter referred to as NGS mode) in which the evaluation test of the test object ends when a defect is detected in each test unit (in this functional test, the test unit is the period until the end of all pattern running), For DC tests, AC tests, etc., only NGS mode is used as first fail stop.

The above-mentioned first fail stop is performed when there is only one test object (hereinafter referred to as single measurement).
Commonly used.

Single measurement or multiple measurements are generally possible.
The IC tester must indiscriminately test defective test objects, such as those whose input terminals are connected to the power supply inside the test object or connected to the ground. Therefore, the protection must be sufficient.

The single measurement described above is protected by the first-fail-stop function, but the IC tester capable of multi-measurement measures two or more devices under test with different characteristic states at the same time. The power supply circuit on the side that is defective,
There must be sufficient protection for the drive circuit.

However, in multi-measurement using conventional IC testers, for example, there is no fast-fail-stop function in multi-measurement of two devices. Even if a physical defect is detected,
Because power and drive pulses are applied until all tests are completed, some test objects may be defective.
Overcurrent or overvoltage conditions occur, which accelerates the deterioration of IC tester components, especially those in the power supply circuit and drive circuit, leading to failures.

Furthermore, when measuring component parts other than IC testers, especially wafers, the needles on the probe card oxidize due to overcurrent, etc., causing poor contact and, in turn, turning good samples into defective ones.

FIG. 1 is a circuit diagram of an example of a conventional semiconductor integrated circuit evaluation test device.

This test device is a multi-measurement device that can simultaneously measure two test objects in parallel.
Voltage is applied to the test object 13 by the power supply circuit 1 until all tests are completed.

First, if the test item is a functional test, relay 11
By closing the relay 12 and opening the relay 12, a functional test loop is configured, and the drive control circuit 7 outputs logic “1” based on the information in the pattern memory 4 and I/O memory 5.
or "0", and further determines whether it is an input state (I mode) or an output state (O mode).
By supplying a specified voltage from the drive circuit 8 to the test object 13 using the input data level power supply 3, the output of the sample 13 is input to the comparator circuit 10, where it is compared with the output data level power supply 2, and the comparison is performed. The signal is input to the control circuit 9.

The comparison control circuit 9 uses the expected pattern in the pattern memory 4 and the judgment (Care)/non-judgment (Don't Care) information of the output from the mask memory 6 to
A defect is determined and the result is transmitted to the test end control circuit 14. Even if a defect occurs, all patterns are measured until the pattern end is detected and the process proceeds to the next test item.

Furthermore, in the case of the CD test, the relay 11 used in the functional test is opened and the DC test loop is configured by closing the relay 12.
Current applied voltage measurement (hereinafter referred to as DC measuring device 15)
voltage applied current measurement (hereinafter referred to as VFM) and voltage measurement (hereinafter referred to as VM).
Even if a defect occurs, measurement will continue until all item tests are completed. Therefore, there was a drawback that the power supply circuit 1 and drive circuit 8 on the side of the defective test object were not protected against short circuits with each other or with the ground.

In addition, depending on the condition of the defective test object, an overcurrent or overvoltage state may occur, which may accelerate the deterioration of the IC tester's components and cause IC test failures.

Furthermore, in wafer measurement, the above-mentioned overcurrent etc. oxidizes the needles on the probe card, resulting in poor contact.

The present invention eliminates the above-mentioned drawbacks and provides a semiconductor integrated circuit test and evaluation device that protects the test device in multiple measurements and shortens test time by adding a first-fail stop function.

In order to achieve the object, the present invention creates an inhibit signal for the test object independently from a judgment signal that is the judgment result of the test object and a designation signal of the first fail stop function, thereby detecting a defective test object. By opening the power supply only to the device under test and setting the drive circuit to output mode, all input pins of the device under test are in a high impedance state, and the power supply circuit, drive circuit, and probe·
This protects against the needle on the card and shortens the test time by stopping measurement before the end of all tests if two test objects become defective at the same time or around the same time. It is.

The present invention provides a semiconductor integrated circuit test and evaluation apparatus for simultaneously measuring two or more test objects in parallel, and a function test means for comparing and determining the output waveform of the test object and the expected waveform from a reference power source and a pattern generator. , means for dividing the judgment signal from the functional test into two or more systems of judgment signals independently in the DC characteristic test and the AC characteristic test, and for the test object judged to be defective by the divided judgment signals. The present invention is characterized in that the present invention is characterized in that the present invention is characterized by comprising means for setting the output state of the power supply circuit and drive circuit of the test evaluation apparatus to a high impedance, and means for allowing other test objects to continue testing.

The present invention will be explained by examples.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit test and evaluation apparatus according to an embodiment of the present invention.

Components 1 to 15 are exactly the same as those of the prior art, and 16 is a first fail stop control circuit, 17 is a logic OR gate, and 18 is a first fail stop signal.

First, first fail stop signal 1
When the first fail stop function is recognized by 8, the judgment signal of the comparison control circuit 9 which is the judgment result of the function test and the judgment signal of the DC measuring device 15 which is the judgment result of the DC test are sent to the first fail stop control circuit. By dividing the inhibit signal into two systems at step 16, the power supply circuit 1 connected to the defective test object 13 is kept open until all item tests are completed. By ORing the I/0 signal, which is the output signal of the drive control circuit 7, and the above-mentioned inhibit signal with the logic OR gate 17, if a failure occurs during the functional test, the input mode of the drive circuit 8 is immediately changed to the next pattern. The drive circuit 8 on the defective side remains in output mode until the item test is completed.
This makes it possible to have high impedance, and even if a defect occurs during a DC test, the defective side
Do not perform DC tests such as IFM, VFM, and VM on the DC measurement system until the end of the test.

In addition, if both test objects 13 become defective at the same time or at different times, the first fail control circuit 16 terminates the test for all items.

As explained in detail above, according to the present invention,
By adding a first fail stop function to the semiconductor integrated circuit test and evaluation equipment that performs multiple measurements, it is possible to protect the power supply circuit and drive circuit of the device on the side of the defective device under test, and to shorten the test time. big.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a conventional semiconductor integrated circuit test and evaluation device, and FIG. 2 is a circuit diagram of a semiconductor integrated circuit test and evaluation device according to an embodiment of the present invention. 1...Power supply circuit, 2...Output data level power supply, 3...Input data level power supply, 4...Pattern memory, 5...I/O memory, 6...Mask memory, 7...Drive Control circuit, 8... Drive circuit, 9... Comparison control circuit, 10... Comparison circuit, 1
1... Relay, 12... Relay, 13... Test object, 14... Test end control circuit, 15...
DC measuring instrument, 16...First fail stop control circuit, 17...Logic OR gate, 1
8...First fail signal.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit test and evaluation device that measures two or more test objects simultaneously in parallel, a functional test means for comparing and determining the output waveform of the test object and an expected waveform using a reference power supply and a pattern generator; Means for independently dividing a judgment signal into two or more systems of judgment signals in a DC characteristic test and an AC characteristic test, and only for a test object judged to be defective by the divided judgment signals. A semiconductor integrated circuit test and evaluation device comprising means for setting the output state of a power supply circuit and a drive circuit of the test and evaluation device to high impedance, and means for allowing other test objects to continue testing.