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JPS6317325B2 - - Google Patents
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JPS6317325B2 - - Google Patents

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Publication number
JPS6317325B2
JPS6317325B2 JP57185527A JP18552782A JPS6317325B2 JP S6317325 B2 JPS6317325 B2 JP S6317325B2 JP 57185527 A JP57185527 A JP 57185527A JP 18552782 A JP18552782 A JP 18552782A JP S6317325 B2 JPS6317325 B2 JP S6317325B2
Authority
JP
Japan
Prior art keywords
solder
terminal
terminal piece
electrode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57185527A
Other languages
Japanese (ja)
Other versions
JPS5976413A (en
Inventor
Shinkichi Shimizu
Seiichi Yamada
Toshio Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57185527A priority Critical patent/JPS5976413A/en
Publication of JPS5976413A publication Critical patent/JPS5976413A/en
Publication of JPS6317325B2 publication Critical patent/JPS6317325B2/ja
Granted legal-status Critical Current

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  • Details Of Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は多層セラミツクチツプコンデンサなど
に用いられる、ラジアル型リード端子の電子部品
用端子片の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a terminal piece for an electronic component such as a radial lead terminal used in a multilayer ceramic chip capacitor or the like.

(b) 従来技術と問題点 電気回路が形成されたチツプ部品に設けられる
ラジアル型リード端子は第1図に示すように形成
される。第1図のa,b,cはラジアル型リード
端子の製造工程を示した説明図である。
(b) Prior Art and Problems A radial lead terminal provided on a chip component on which an electric circuit is formed is formed as shown in FIG. 1A, 1B, and 1C are explanatory diagrams showing the manufacturing process of a radial type lead terminal.

aに示すように先づチツプ部品1のAg−Pdな
どの厚膜によつて形成された電極2にコの字型に
曲折された半田めつきが施された線材の端子片3
を挟持させ電極2に先端3Aを重ね合せる。次ぎ
にbに示すように半田5が溶融された半田槽4に
チツプ部品1を浸漬させる。これにより、cに示
すように電極2と先端3Aとは半田5によつて固
着される。その後端子片3の曲折部3Bは切断さ
れ、ラジアル型リード端子3Cが形成される。
As shown in a, first, a wire terminal piece 3 bent in a U-shape and solder-plated is attached to the electrode 2 formed of a thick film such as Ag-Pd of the chip component 1.
The tip 3A is superimposed on the electrode 2 by sandwiching the electrodes. Next, as shown in b, the chip component 1 is immersed in the solder bath 4 in which the solder 5 is melted. Thereby, the electrode 2 and the tip 3A are fixed by the solder 5 as shown in c. Thereafter, the bent portion 3B of the terminal piece 3 is cut to form a radial lead terminal 3C.

かゝる端子片の製造では半田槽4にチツプ1を
浸漬する際、電極2と先端3Aとの重ね合せ部が
位置ずれを生じることなく、確実に固着させるた
めにはずれないようにする必要があり、従来コの
字型に曲折された端子片3に矢印A方向のテンシ
ヨンを持たせることでチツプ部品1を挟圧させる
ように配慮されていた。
In manufacturing such a terminal piece, when the chip 1 is immersed in the solder bath 4, it is necessary to prevent the overlapping part of the electrode 2 and the tip 3A from coming off in order to ensure that they are fixed without any displacement. Conventionally, consideration has been given to compressing the chip component 1 by giving the terminal piece 3 bent in a U-shape a tension in the direction of arrow A.

しかし、このような挟圧力ではずれが生じ易
く、位置ずれによつて端子3Cが曲つて固着され
る欠点を有し、更には完全な固着が行なわれない
問題を有していた。
However, such a clamping force tends to cause the terminal 3C to come off easily, and the terminal 3C is bent and fixed due to the positional shift, and furthermore, there is a problem that the terminal 3C is not completely fixed.

(c) 発明の目的 本発明の目的は半田槽にチツプ部品を浸漬する
際電極と端子片とは仮固着を行うことにより、前
述の問題点を除去したものを提供するものであ
る。
(c) Object of the Invention The object of the invention is to provide a device which eliminates the above-mentioned problems by temporarily fixing the electrode and the terminal piece when the chip component is immersed in a solder bath.

(d) 発明の構成 本発明の目的は、かゝる電子部品用端子片の製
造方法において、端子片に施される。半田被膜は
半田槽の半田より融点の高い高温半田によつて形
成すると共に、電極と先端との重ね合せ部にはフ
ラツクスを塗布して該半田被膜が溶融される所定
時間の熱光線を照射せしめた後半田デイツピング
を行うことを特徴とする電子部品用端子片の製造
方法により達成される。
(d) Structure of the Invention The object of the present invention is to provide a method for manufacturing a terminal piece for electronic components. The solder film is formed using high-temperature solder whose melting point is higher than that of the solder in the solder bath, and a flux is applied to the overlapping portion of the electrode and the tip, and heat rays are irradiated for a predetermined period of time to melt the solder film. This is achieved by a method for manufacturing a terminal piece for an electronic component, which is characterized by performing post-dipping solder.

(e) 発明の実施例 以下本発明を第2図、第3図を参考に詳細に説
明する。
(e) Embodiments of the Invention The present invention will be described in detail below with reference to FIGS. 2 and 3.

端子片3としては0.5±0.05φの線材の外周に
Pb90%、Sn10%の半田によつて12μmの厚さの被
膜が形成されたMLH−122半田メツキ軟銅線
(協和電線製)を用い第1図に示すようにコの字
型に曲折して作成し、この端子片3によつてチツ
プ部品1を挟持させる。次ぎに、電極2と先端3
Aとの重置部にWWロジンのI,P,A希釈フラ
ツクスを塗布し、第2図のグラフに示すH1
H2,H3の予備加熱を行ない、更に、赤外線光源
を用いて照射しFに示す約300℃に達する加熱を
行ない端子片3の被膜を溶融させ、重置部の電極
2と先端3Aとを仮固着させる。この場合の赤外
線加熱による仮固着強度は第3図の赤外線加熱時
間と引張強度の関係グラフに示すようになる。
As the terminal piece 3, attach it to the outer periphery of a wire of 0.5±0.05φ.
It was made by bending it into a U-shape as shown in Figure 1 using MLH-122 solder-plated annealed copper wire (manufactured by Kyowa Electric Wire) with a 12 μm thick coating formed with 90% Pb and 10% Sn solder. The chip component 1 is then held between the terminal pieces 3. Next, electrode 2 and tip 3
Apply I, P, A diluted flux of WW rosin to the overlapping area with A, and apply H 1 , as shown in the graph of Figure 2.
Preheating with H 2 and H 3 is performed, and further heating is performed using an infrared light source to reach approximately 300°C as shown in F to melt the coating on the terminal piece 3 and connect the electrode 2 and tip 3A of the overlapping part. Temporarily fix. In this case, the temporary fixing strength due to infrared heating is as shown in the graph of the relationship between infrared heating time and tensile strength in FIG.

赤外線加熱時間がP1,P2,P3に示すように長
くなるに従つて引張強度は増加される。赤外線加
熱時間が3秒のP3では引張強度が大きくなるが
フラツクスが酸化され、デイツピングに際して
「半田ヌレ」性が劣化される。しかし、2秒のP2
ではフラツクスは酸化されることなく「半田ヌ
レ」性は良好である。この場合フラツクスを塗布
しないと被膜が溶融されても電極2と先端3Aと
は固着されない。
As the infrared heating time increases as shown in P 1 , P 2 , and P 3 , the tensile strength increases. In P3 , where the infrared heating time is 3 seconds, the tensile strength is high, but the flux is oxidized and the "solder wetting" property is deteriorated during dipping. But P 2 for 2 seconds
The flux is not oxidized and has good "solder wetting" properties. In this case, unless flux is applied, the electrode 2 and tip 3A will not be fixed even if the coating is melted.

仮固着された後、Pb40/Sn60の割合にAg3%
が含有された半田融点180〜183℃を用い250±5
℃の半田槽に浸漬させる。この浸漬後半田槽より
取り出されたチツプ部品1の電極2と先端3Aと
の固着不良、位置ずれをチエツクしたがいづれも
発生されなく確実に固着されていた。
After being temporarily fixed, Ag3% is added to the Pb40/Sn60 ratio.
250±5 using a solder with a melting point of 180 to 183℃.
Immerse it in a solder bath at ℃. After this immersion, the chip component 1 was taken out from the solder bath and was checked for poor adhesion or misalignment between the electrode 2 and the tip 3A, but it was found that neither of these problems occurred and they were securely bonded.

このように被膜による融着の温度は半田槽の半
田の融点より高くされているため、赤外線加熱に
よる仮固着はデイツピング時に外れることなく、
また、フラツクスによる「半田ヌレ」性の効果が
加わり良好な半田槽の形成を行うことができる。
In this way, the temperature of the fusion by the coating is set higher than the melting point of the solder in the solder bath, so the temporary bonding caused by infrared heating does not come off during dipping.
In addition, the effect of "solder wetting" caused by the flux is added, and a good solder tank can be formed.

(f) 発明の効果 以上説明したように本発明は端子片3の被膜は
高温半田めつきによつて形成し、電極2と先端3
Aとの重置部はフラツクスを塗布し赤外線加熱に
よつて仮固着してデイツピングを行うようにした
ものである。
(f) Effects of the Invention As explained above, the present invention provides a coating on the terminal piece 3 that is formed by high-temperature solder plating so that the electrode 2 and the tip 3
The overlapping portion with A is coated with flux and temporarily fixed by infrared heating to perform dipping.

これにより、製造工程中のチツプ部品1の移送
時に欠落、位置ずれはなくなり、またデイツピン
グ時における欠落、不完全固着時には位置ずれに
よる端子曲りは防止でき実用効果は大である。
This eliminates chipping and misalignment during transfer of the chip component 1 during the manufacturing process, and also prevents chipping during dipping and bending of terminals due to misalignment during incomplete fixation, which has a great practical effect.

尚、本発明は端子片3はラジアル型で説明を行
つたが、端子片3がチツプ部品1の同軸上に位置
されるアキシヤル型にも適用可能であり同等の効
果は得られる。
Although the present invention has been described using a radial type terminal piece 3, it is also applicable to an axial type where the terminal piece 3 is located coaxially with the chip component 1, and the same effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図のa,b,cはラジアル型リード端子の
製造工程を示した説明図、第2図は本発明による
電子部品用端子片の製造方法による実施例の加熱
温度と時間との関係グラフ、第3図は赤外線加熱
時間と引張強度との関係グラフを示す。 図中において、1はチツプ部品、2は電極、3
は端子片、4は半田槽、5は半田、を示す。
Figures a, b, and c in Figure 1 are explanatory diagrams showing the manufacturing process of a radial lead terminal, and Figure 2 is a graph of the relationship between heating temperature and time in an example of the method for manufacturing a terminal piece for electronic components according to the present invention. , FIG. 3 shows a graph of the relationship between infrared heating time and tensile strength. In the figure, 1 is a chip component, 2 is an electrode, and 3 is a chip component.
indicates a terminal piece, 4 indicates a solder tank, and 5 indicates solder.

Claims (1)

【特許請求の範囲】[Claims] 1 平滑な端子電極に、半田被膜を有するコの字
型に曲折した端子片の端部が重ね合せられた重置
部を半田槽に半田デイツピングすることにより該
端子片は該端子電極より突出されて固着され、ラ
ジアル型リード端子が形成される電子部品用端子
片の製造方法において、前記半田被膜は前記半田
槽の半田より融点の高い高温半田によつて形成す
ると共に、前記重置部にはフラツクスを塗布して
該半田被膜が溶融される所定時間の熱光線を照射
せしめた後前記半田デイツピングを行うことを特
徴とする電子部品用端子片の製造方法。
1. By soldering a stacked part in which the end of a U-shaped terminal piece with a solder coating is overlaid on a smooth terminal electrode in a solder bath, the terminal piece protrudes from the terminal electrode. In the method for manufacturing a terminal piece for an electronic component in which a radial type lead terminal is formed by fixing the solder film with a high-temperature solder having a higher melting point than the solder in the solder bath, 1. A method of manufacturing a terminal piece for an electronic component, comprising applying flux and irradiating the solder coating with heat rays for a predetermined period of time to melt the solder coating, and then performing the solder dipping.
JP57185527A 1982-10-22 1982-10-22 Method of producing terminal piece for electronic part Granted JPS5976413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57185527A JPS5976413A (en) 1982-10-22 1982-10-22 Method of producing terminal piece for electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57185527A JPS5976413A (en) 1982-10-22 1982-10-22 Method of producing terminal piece for electronic part

Publications (2)

Publication Number Publication Date
JPS5976413A JPS5976413A (en) 1984-05-01
JPS6317325B2 true JPS6317325B2 (en) 1988-04-13

Family

ID=16172356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57185527A Granted JPS5976413A (en) 1982-10-22 1982-10-22 Method of producing terminal piece for electronic part

Country Status (1)

Country Link
JP (1) JPS5976413A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06244049A (en) * 1989-11-02 1994-09-02 Taiyo Yuden Co Ltd Method for lead wire connection

Also Published As

Publication number Publication date
JPS5976413A (en) 1984-05-01

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