JPS631757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic induction type semiconductor switching device.

An example of a conventional electrostatic induction thyristor is shown in FIGS. 1 to 4. Figures 1, 3 and 4 are respectively
The cross-sectional structures of different electrostatic induction thyristors are shown. FIG. 2 is a plan view of the conventional example shown in FIG. 1, viewed from the cathode side.

In these figures, 2 is an anode electrode, 3 is a cathode electrode, 4 is a gate electrode, 5 is a SiO ₂ film for passivation, 6 is a P emitter, 7 is an N base, 8 is a P base, and 9 is a P base with 8 as a gate. P ⁺ layer for connecting to electrode 4, N emitter at 10,
11 is an N ⁺ emitter provided in the N emitter 10, and 12 is an emitter short circuit provided in the P emitter 6.

The common feature of these conventional examples is that the diode
A thyristor P ⁺ N ^- PNN ⁺ region is formed around the P ⁺ N ^- NN ⁺ region, that is, the channel region, and this thyristor region is made conductive by a current flowing through the diode region (hereinafter referred to as diode current). The point is that it is configured in such a way that it is easy to do so.

With this configuration, even if the gap between the P bases 8 (hereinafter referred to as channel width) is narrowed so that the main current can be cut off even with a low gate bias voltage, the main current will still flow through the thyristor region, so the current will not be energized. This has the advantage that the main current that can be generated can be increased.

That is, a high anode-cathode voltage (hereinafter referred to as anode voltage) can be blocked with a low gate bias voltage, and a large current can be passed, so a high voltage and large current element can be realized.

In the conventional examples shown in FIGS. 3 and 4, a part of the P emitter 6 in the conventional examples shown in ^FIGS . It is less efficient. As a result, the turn-off operation becomes very fast and high-speed current cutting is possible. Furthermore, the generation of leakage current when high voltage is applied at high temperature can be reduced.

As described above, the conventional examples shown in FIGS. 1 to 4 each have excellent features, but they have the disadvantage that local concentration of current occurs during turn-off, making them susceptible to thermal breakdown.

The reason for this will be explained below.

FIG. 5B shows the R point in the conventional example shown in FIGS. 1, 3, and ⁴ (as shown in FIG. 5A, the r
An example of the distribution of the current iz flowing in the z direction at a position in the z direction is shown.

In the conventional examples shown in FIGS. 1 and 2, the diode (channel) region is larger than the thyristor region.
Since current flows easily, the current iz reaches its maximum at the center of the diode region, as shown by the solid line I in FIG. 5B. On the other hand, in the conventional example shown in FIG. 3, as shown by the curve B in the same figure, the current iz becomes smaller in the peripheral area where the emitter short-circuit part 12 made of the N ⁺ layer is provided, and in the center of the diode area, Current iz becomes maximum.

In any case, in the conventional examples shown in FIGS. 1 and 3, at turn-off, current concentrates in the diode region where current easily flows. Therefore, the channel portion tends to become high in temperature due to generation of Joule heat, and the safe operating voltage and current ranges become narrower.

In the conventional example shown in FIG. 4, in addition to the conventional example shown in FIG.
An emitter shorting section 12 made of an N ⁺ layer is provided to prevent current from concentrating on the channel section.

However, in this conventional example, as can be seen from the curve in FIG. Voltage and current ranges become narrower.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide an electrostatic induction thyristor that is less likely to be thermally destroyed during turn-off and has a large safe operating range. In order to achieve the above object, in the present invention, a highly impurity layer of the opposite conductivity type is provided on the emitter of the first conductivity type of the electrostatic induction thyristor to make the emitter short-circuited, and the emitter of the first conductivity type is connected to the adjacent emitter. The carrier injection efficiency with respect to the opposite conductivity type base increases as the distance from the channel portion of the electrostatic induction thyristor increases.

FIG. 6A is a sectional view of one embodiment of the present invention, and the same reference numerals as in FIG. 4 represent the same or equivalent parts. The feature of this embodiment is that the P emitter sweeps out carriers (holes) from the inside of the device when turned off, from the part directly below the gate electrode 4 to the channel part - in other words, in the r direction in the N base 7 close to the P base 8. As shown in FIG. 6B, local concentration of the current is prevented and the turn-off operation is performed over the entire surface in the r direction by configuring the device so that the maximum value of the current iz decreases as it approaches the channel portion, as shown in FIG. 6B. This is done so that they occur almost at the same time.

This is because the carrier is more likely to be swept out in the region near the gate electrode, so the current iz should be made to decrease as it moves away from the region near the gate electrode or as it approaches the channel region. For example, the turn-off operation can be made to occur almost uniformly within the element.

As one specific measure to achieve such turn-off operation, in the embodiment of FIG. 6A, the widest P ⁺ emitter layer 6-1 is placed closest to the gate electrode 4 - in other words, Provided at the peripheral part farthest from the channel part, this P ⁺ emitter layer 6-
1, an N+ layer 12-1, which is an emitter shorting part, is placed on the side closer to the channel part, and a first ^{P+ layer 12-1 is placed next to this N+ layer} 12-1, on the side closer to the channel part. 2nd P ⁺ layer 6-2 narrower than 6-1
will be established.

Similarly, the N ⁺ layer 12-2, which has the same width as the first N ⁺ layer 12-1, and the second P ⁺ layer 6-
3rd P ⁺ layer 6-3 narrower than 2, first N ⁺
N ⁺ layer 12-3 having the same width as layer 12-1, fourth P ⁺ layer 6-4 having a narrower width than the third P ⁺ layer 6-3,
P ⁺ layers and N ⁺ layers are provided alternately in this order until reaching the center of the channel.

In this way, the N ⁺ layer 12-
When the width of i is constant, as the width of P ⁺ layer 6-i becomes narrower, the maximum value of the current flowing through the region of P ⁺ layer 6-i becomes smaller as shown in Figure 6B. Become. As a result, the current iz decreases as it approaches the center of the channel from the gate electrode 4, that is, as it approaches the channel portion, and the object of the present invention can be achieved.

FIG. 7A shows another embodiment of the invention. 6th
In the embodiment shown in the figure, the P ⁺ layer 6 is provided directly below the channel section, whereas in this embodiment, the P + layer 6 is provided directly below the channel section.
An N ⁺ layer is provided. As a result, as shown in FIG. 7B, the current iz can be minimized at the center of the channel where the current is greatest in the conventional examples shown in FIGS. 1 to 3.

Therefore, the voltage and current ranges of the safe operation region can be made much larger than in the case of the embodiment shown in FIG.

Furthermore, the present invention can be implemented with various modifications as described below.

(1) In the arrangement of Figures 6A and 7A,
When arranging P ⁺ layers 6 and N ⁺ layers 12 alternately, P ⁺
The width of the layer 6 is constant, and the width of the N ⁺ layer 12 is increased as it approaches the channel portion.

(2) Regarding the arrangement of Figures 6A and 7A,
When arranging P ⁺ layers 6 and N ⁺ layers 12 alternately, P ⁺
The distribution ratio of the N ⁺ layer 12 to the layer 6 is made larger as it approaches the channel portion.

(3) ^In the arrangement of FIG ^. 6A and ^{FIG .}
When arranging them alternately, the depth of the P ⁺ layer 6 is made shallower as it approaches the channel portion.

(4) ^In the arrangement of FIG ^. 6A and ^{FIG .}
When arranging them alternately, the depth of the N ⁺ layer 6 is increased as it approaches the channel portion, as shown in FIG. 8A. The current distribution in this case is shown in FIG. 8B. In this case, there is an advantage that there is no reduction in breakdown voltage.

As is clear from the summary of these embodiments, the present invention provides a short-circuited emitter electrostatic induction thyristor with improved carrier injection efficiency (or its maximum value) from the short-circuited emitter layer to the adjacent base layer. is smallest right below the channel part,
The current is configured to increase as it moves away from the channel section and approaches the gate electrode, so that the current flowing through the channel section is the smallest and gradually increases as it moves away from the channel section and approaches the gate electrode. This is what I did.

"Also, in each of the above structures, the N emitter 1
The concentration of 0 may be made equal to that of N base 7. Furthermore, various modifications are possible, such as removing the portion corresponding to the P ⁺ layer 9 and making the gate electrode 4 directly adjacent to the P base 8. As explained above, the present invention has high industrial value because it can realize a high-speed current cutting element with low leakage current at high temperatures and a wide safe operating range.

It should be noted that it will be easily understood that the present invention can be practiced even if the P layer and the N layer are replaced in each of the embodiments described above.

[Brief explanation of the drawing]

1, 3, and 4 are cross-sectional views of conventional electrostatic induction thyristors, FIG. 2 is a plan view of the electrostatic induction thyristor of FIG. 1, and FIG. 5A is a short-circuited emitter of the conventional electrostatic induction thyristor. FIG. 5B is a sectional view of a common part of the electrostatic induction thyristor structure excluding the P emitter, and FIG. 5B is a diagram showing the current distribution in each region of FIG. FIG. 6A is a sectional view of one embodiment of the present invention;
Figure B is a diagram showing the current distribution in the embodiment of Figure A, Figure 7A is a sectional view of another embodiment of the present invention, Figure 7B is a diagram showing the current distribution in the embodiment of Figure A, FIG. 8A is a sectional view of still another embodiment of the present invention, and FIG. 8B is a diagram showing the current distribution in the embodiment of FIG. 8A. 2... Anode electrode, 3... Cathode electrode, 4... Gate electrode, 5... SiO ₂ film for passivation, 6
...P emitter, 7...N base, 8...P base, 9
...P ⁺ layer, 10...N emitter, 11...N ⁺ emitter, 12...N ⁺ layer (emitter short-circuit part).

Claims (1)

[Claims] 1. A first semiconductor layer having one conductivity type;
adjacent to the first semiconductor layer and between the first semiconductor layer and the first semiconductor layer.
A second semiconductor layer of the other conductivity type that forms a PN junction and a semiconductor layer that is formed within the second semiconductor layer so as to be adjacent to the exposed main surface of the second semiconductor layer, and that is lower than the second semiconductor layer. at least one first semiconductor region of the other conductivity type having a high impurity concentration, and a portion of which is included in a peripheral portion of a projected portion formed by projecting the first semiconductor region onto the first semiconductor layer side. at least one second semiconductor region of one conductivity type embedded in the second semiconductor layer and forming a PN junction with the second semiconductor layer; and at least one second semiconductor region of the first semiconductor layer. , metal electrodes formed on the exposed surface of the first semiconductor region and the exposed surface of the portion included in the projected portion along the second semiconductor region, and of the projected portion; In an electrostatic dielectric semiconductor switching element, a portion including the second semiconductor region has a thyristor function, and a portion not including the second semiconductor region has a diode function. The emitter shorting layer is arranged such that carrier injection efficiency from the first semiconductor layer to the second semiconductor layer increases as the distance from the portion having a diode function increases. Inductive semiconductor switching device. 2 The ratio of the width of one conductivity type region in the first semiconductor layer to the width of the emitter shorting layer of the other conductivity type is
2. The electrostatic induction type semiconductor switching device according to claim 1, wherein the size of the electrostatic induction type semiconductor switching device increases as the distance from the portion having the diode function increases. 3. The electrostatic induction type semiconductor switching device according to claim 2, wherein the width of one conductivity type region is constant. 4. The electrostatic induction type semiconductor switching device according to claim 2, wherein the emitter shorting layer of the other conductivity type has a constant width. 5. The electrostatic induction type semiconductor switching device according to claim 1, wherein the depth of the one conductivity type region increases as the distance from the portion having the diode function increases. 6. The electrostatic induction type semiconductor switching device according to claim 1, wherein the depth of the emitter shorting layer of the other conductivity type becomes shallower as the distance from the portion having the diode function increases. . 7. Claims 1 to 6 above, characterized in that an emitter shorting layer of the other conductivity type is provided approximately at the center of a portion of the first semiconductor layer corresponding to a portion having a diode function. The electrostatic induction type semiconductor switching device according to any one of the above.