JPS631766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit, and particularly to a common source type field effect transistor amplifier circuit.

Self-bias circuits are widely used as bias circuits for operating field-effect transistors. FIG. 1 shows a circuit diagram in which the self-bias circuit described above is applied to a common source amplifier of an N-channel junction type depletion FET (field effect transistor).

That is, a bias source resistor R _S is provided between the source and ground of the transistor Q ₁ , a load resistor R _D is connected to the drain, and the gate input is amplified and becomes the drain output. Note that Ri indicates input resistance.

In such a configuration, the drain current I _D causes the source to be positive with respect to ground, and thus the gate is negative with respect to the source, providing a reverse bias. As a result, the following equation holds true.

V _GS = −I _D・R _S ...(1) Here, V _GS indicates the gate-source voltage.

Here, N channel depression type
The input/output transfer characteristic of the FET is as shown by curve A or B in FIG. These two curves A and B are FET
This figure shows an example of how the input/output characteristics (V _GS − _ID characteristics) change due to variations in the elements. The operating point based on the source resistance R _S can be determined by drawing the R _S line in the figure. sell. In other words, from equation (1), I _D =−
Since V _GS /R _S is obtained, it can be seen that the R _S line in FIG. 2 is a straight line passing through the origin.

Therefore, in a FET with characteristic A, the drain current I _D1
If R _S is determined to flow, the drain potential of FETQ ₁ becomes +V _DD −R _D ·I _D1 . On the other hand, if a FET with characteristic B is used in the circuit shown in Fig. 1, the drain current will be I _D2 , and therefore the drain potential will be +
It can be seen that there is a large fluctuation as V _DD −R _D・I _D2 .

As a solution to this problem, if the source resistance R _S is increased, the slope of the R _S line becomes smaller, and as a result, the fluctuation width can be reduced, but this has the disadvantage that the circuit gain decreases accordingly. Furthermore, since R _S also becomes a part of the signal source resistance, if it is made large, the thermal noise of R _S becomes large and the S/N ratio deteriorates. As described above, it has become difficult to control the drain current by correcting variations in the FET elements using the source resistance R _S.

An object of the present invention is to provide a source-grounded FET transistor circuit that can minimize the source resistance, reduce the influence of thermal noise, and increase the circuit gain.

Another object of the present invention is to provide a common source type FET transistor circuit suitable for use in a driver stage of an output push-pull amplifier circuit used in a power amplifier circuit or the like.

The transistor circuit of the present invention is a source-grounded FET circuit having a source resistance, and is characterized in that a constant current source is added to the source resistance to supply a predetermined current other than the drain current,
The present invention is characterized in that the current value of this constant current source can be adjusted in response to deviations in input/output transfer characteristics caused by variations in FETs.

When the transistor circuit of the present invention is used as a driver stage of a push-pull type power amplifier circuit, the sources of the first and second transistors are grounded through the first and second source resistors, respectively, and the transistor circuit of the present invention operates as a common source type. Complementary FET, first and second
a first and a second constant current source that respectively supply a current other than the drain current to the source resistor of the FET, and the drain outputs of the first and second FETs are respectively used as control inputs of the push-pull transistor. It is said that

Preferably, the current values of the first and second constant current sources are adjusted respectively to cover deviations in the input/output transfer characteristics of the FET and to equalize both drain output potentials.

Hereinafter, the present invention will be explained using the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. In this example, a constant current source 1 is further added to the circuit shown in FIG. 1, and a constant current I ₀ is supplied to the source resistor R _S in addition to the drain current _ID .

Therefore, it can be seen that the following equation holds true.

V _GS = - (I _D + I ₀ ) · R _S ...(2) When this formula is transformed to find I _D , the following formula is obtained.

I _D = −V _GS /R _S −I ₀ ...(3) Using equation (3), R _S corrected by current source 1
When a line is drawn in the input/output transfer characteristic curve, it becomes a straight line shown by the solid line in FIG. In this case, when the source resistance R _S is selected so that the drain current of the element having characteristic B becomes I _D1 at a predetermined constant current I ₀ ,
In order to make the drain current of the element with characteristic A equal to I _D1 , the source resistance R _S is left as is, and the constant current value is adjusted to I ₀ ' to increase R _S as shown by the dotted line in Figure 4. It can be seen that this is possible by moving the line in parallel.

In other words, since the voltage drop across the source resistance R _S is caused not only by the drain current but also by (I _D + I ₀ ), the value of the source resistance R _S is set small and the slope of the corrected R _S line is Keep it big,
This means that the output voltage value can be kept constant regardless of FET variations. Therefore, generation of thermal noise and decrease in gain due to the source resistance R _S can be suppressed.

FIG. 5 shows a case where the circuit of FIG. 3 is applied to the driver stage 3 of the push-pull power amplifier circuit 2, and the so-called complementary FETs Q ₁ and Q ₂ whose gates are commonly connected are each connected to a source resistor R _S1 The source is grounded via R and R _S2 , and the drain is connected to the positive and negative power supplies via load resistors R _D1 and R _D2 , respectively. Constant current sources 11 and 12 are provided to supply constant currents I ₀₁ and I ₀₂ to the respective source resistors R _S1 and R _S2 , respectively.
Each drain output serves as the base input of complementary SEPP output transistors Q ₃ and Q ₄ having common collectors and forming the push-pull amplifier circuit 2 .
The emitters of both transistors Q ₃ and Q ₄ are resistors R ₁ and R ₂
are connected to the positive and negative power supplies through the terminals.
Note that R _L indicates the load.

Here, if both source resistances R _S1 and R _S2 are selected to be equally small, even if the characteristics of both FETQ ₁ and Q ₂ vary widely, the drive current I ₀₁ and sink current of constant current sources 11 and 12 By appropriately selecting the value of I ₀₂ , it becomes possible to equalize the absolute values of both drain output potentials, and in addition to having the effect of the circuit shown in FIG. 3, push pull transistors Q ₃ and Q ₄ Since the base biases of both transistors Q ₃ and Q ₄ can be made equal, there is no difference in the output currents of both transistors Q 3 and Q 4 , which has the advantage that no offset output occurs.

FIG. 6 is a circuit diagram showing another embodiment of the present invention, in which the source resistances R _S1 and R _S2 of the circuit of FIG. 5 are made common to form a variable resistor. That is,
The variable terminal of this variable resistor R is grounded, and the divided resistance portions on both sides of the variable terminal correspond to R _S1 and R _S2 , respectively.

Here, if you select the variable terminal at an arbitrary point,
R _S2 =R-R _S1 , and if R _S1 =α·R (α is a coefficient), R _S2 =R-αR=R(1-α).
Therefore, the voltage drop across each resistor is as follows.

Here, the current values of both constant current sources are selected to be equal to I ₀ , and the gate-source voltage of both FETs is
V _GS1 and V _GS2 are used.

Therefore, in the circuit shown in Figure 6, while the currents _I0 of both constant current sources are kept equal, the values of V _GS1 and V _GS2 can be changed inversely proportionally using the variable resistor. , adjustment of the drain current becomes easier than adjustment of the current source shown in FIG. Here, the variable resistor is used to compensate for relative variations in the FET,
Furthermore, by using the current I ₀ as an absolute variation correction of the FET, a wide range of correction becomes possible, which is suitable for mass production.

Fig. 7 shows a so-called NFB (negative feedback) amplifier using the circuit 3 of Fig. 6 together with the push-pull amplifier 2. The same parts as in Figs. 5 and 6 are indicated by the same symbols, and the resistors
R ₃ and R ₄ form the NFB circuit.

The variable resistor R is used to equalize the drain current _ID by changing the _VGS of the FET, and the constant current is adjusted by changing its absolute value to eliminate _variations in the output push-pull transistor. The collector current of is kept constant. Further, the variable resistor R is used for adjusting the midpoint offset, and the constant current source is also used for setting the idle current of the output transistor.

The circuit of FIG. 8 has a resistor _R5 added in parallel to the variable resistor R in the circuits of FIGS. 6 and 7. Generally speaking, a variable resistor R with a very small total resistance value is expensive in terms of cost, so it is possible to reduce the cost by using a variable resistor R with a relatively large resistance value. This is a circuit with small resistance.

That is, if the upper and lower resistances of the variable resistor R are αR and (1-α)R, respectively, as shown in a, and the so-called △-Y (delta star) conversion is performed as shown in b, the following equation is obtained. It will be done.

Therefore, it can be seen that the equivalent values of Ra, Rb and Rc can all be made small.

As described above, according to the present invention, variations in FET elements can be corrected without increasing the source resistance, so there is no reduction in circuit gain or deterioration of S/N. Furthermore, if the circuit of the present invention is used in the driver stage of a push-pull power amplifier, there is an advantage that in addition to the above-mentioned effects, it is also possible to further reduce offset current.

[Brief explanation of the drawing]

Figure 1 shows an example of a conventional circuit, and Figure 2 shows an example of a conventional circuit.
FIG. 3 is a diagram showing the characteristics of the FET element, FIG. 3 is a diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing the characteristics of the circuit in FIG. 3, and FIG. 5 is an example of an application of the circuit in FIG. 3. Figure 6 is a diagram showing another embodiment of the present invention, Figure 7 is a diagram showing another embodiment of the present invention.
The figure shows an example of the application of the circuit in Figure 6, and Figure 8a.
1 is a diagram showing another embodiment of the present invention, and b is an equivalent circuit diagram thereof. Explanation of symbols of main parts, 1...constant current source, Q ₁ ,
Q ₂ ...FET, R _S ...source resistance.

Claims (1)

[Scope of Claims] 1. A source-grounded field effect transistor circuit having a source resistor, which supplies a predetermined current to the source resistor in addition to the drain current by a constant current source whose current value is adjustable. 1. A transistor circuit comprising: a transistor circuit configured to be capable of correcting variations in input/output characteristics of the field effect transistor by adjusting a current value supplied from the constant current source. 2. A transistor circuit comprising first and second complementary field effect transistors whose sources are grounded via first and second source resistors, respectively, and which mutually perform common source type operation, wherein the first and second sources The first and second resistors each have a current value that can be adjusted in addition to the respective drain currents.
A constant current source is configured to supply a predetermined current, and variations in each input/output characteristic of the field effect transistor can be corrected by adjusting the current values supplied from the first and second constant current sources. A transistor circuit characterized by: 3 The absolute values of the currents of the first and second constant current sources are selected to be equal to each other, and the first and second source resistances are selected from a dividing resistance portion of a variable resistor whose variable terminal is grounded. 3. The transistor circuit according to claim 2, wherein the transistor circuit is configured as follows. 4. The transistor circuit according to claim 3, wherein the first and second source resistors further include fixed resistance elements connected to both ends of the variable resistor. 5. The transistor circuit according to claim 4, wherein the total resistance of the variable resistor is selected to be much larger than the resistance of the fixed resistance element.