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JPS631808B2 - - Google Patents
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JPS631808B2 - - Google Patents

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Publication number
JPS631808B2
JPS631808B2 JP3674080A JP3674080A JPS631808B2 JP S631808 B2 JPS631808 B2 JP S631808B2 JP 3674080 A JP3674080 A JP 3674080A JP 3674080 A JP3674080 A JP 3674080A JP S631808 B2 JPS631808 B2 JP S631808B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
output
line
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3674080A
Other languages
Japanese (ja)
Other versions
JPS56133933A (en
Inventor
Hirotsugu Minami
Sadao Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP3674080A priority Critical patent/JPS56133933A/en
Publication of JPS56133933A publication Critical patent/JPS56133933A/en
Publication of JPS631808B2 publication Critical patent/JPS631808B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 (利用分野) 本発明は交流単相3線式配電線或は交流3相4
線式配電線等の中性線を有する配電線の中性線に
断線或はゆるみ等の欠落が生じた際に信号を出力
する中性線欠落検出装置に関する。
Detailed Description of the Invention (Field of Application) The present invention is applicable to AC single-phase three-wire distribution lines or AC three-phase four-wire
The present invention relates to a neutral wire missing detection device that outputs a signal when a missing wire such as a disconnection or loosening occurs in a neutral wire of a power distribution line having a neutral wire such as a wire type power distribution line.

(従来技術の問題点) 一般にこの種中性線欠落検出装置は第8図に示
す如く、配電線L1,L2Nの電圧線L1,L2
間に互いに等しい値のインピーダンス素子イ,ロ
の直列回路を接続しこのインピーダンス素子イ,
ロの接続点である仮想中性点ハと中性線Nとの差
電圧を比較回路ニに入力しており、中性線Nの一
点Aで断線或はゆるみ等の欠落が生じ負荷ホ,ヘ
のバランスが悪いと仮想中性点ハと中性線Nとの
差電圧が発生しこの差電圧が比較回路ニに入力さ
れて時限回路トに信号を出力しこの出力信号に一
定の時限を付与して時限回路トより増幅回路チに
信号を出力しこの出力信号を増幅回路チにて増幅
してスイツチング回路リをスイツチング動作させ
電磁引外し装置ヌを動作させて電圧線L1,L2
の電路接点ル,オと中性線Nの電路接点ワとを開
極するものであつた。
(Problems with the Prior Art) In general, this type of neutral line missing detection device is configured as shown in FIG.
A series circuit of impedance elements A and B with equal values is connected between the impedance elements A and B.
The difference voltage between the virtual neutral point C, which is the connection point of B, and the neutral wire N is input to the comparator circuit D, and if a disconnection or looseness occurs at one point A of the neutral wire N, the load H, If the balance between F and F is poor, a voltage difference will occur between the virtual neutral point C and the neutral wire N, and this voltage difference will be input to the comparator circuit D, which will output a signal to the timer circuit G, which will set a certain time limit on this output signal. Then, a signal is outputted from the time limit circuit G to the amplifier circuit H, and this output signal is amplified by the amplifier circuit H, and the switching circuit RI is operated to operate the electromagnetic tripping device NU, and the voltage lines L1 and L2 are
The circuit contacts L and O of the neutral wire N and the circuit contact W of the neutral wire N were opened.

而して上記の如きものであると、電圧線L1,
L2のいずれか一方、例えば電圧線L1が断線或
はゆるみ等の欠落を生じた際は電圧線L2と中性
線Nとの間の電圧がインピーダンス素子イとイン
ピーダンス素子ロと負荷ホとの直列回路に印加さ
れこれに伴つて仮想中性点ハと中性線Nとの差電
圧が発生し電路接点ル,オ,ワを開極するので、
負荷ヘには何ら異常電圧が印加されないにもかか
わらず動作すると共に例えば仮設現場の如き電圧
線L1,L2のいずれか一方と中性線Nとの間の
みに交流電圧を印加しこの間に負荷を接続して用
いることが出来ないから漏電しや断器或は過電流
しや断器等のしや断器に組込まれた際にこのしや
断器を介して仮設現場で用いる際は電圧線L1,
L2と中性線Nとの両方に電圧を印加しなくては
ならない問題があつた。而もこの配電線L1,L
2,Nに電圧を印加する初期に電圧線L1,L2
のいずれか一方の電圧線の印加が遅れた際にも動
作する問題があつた。
Therefore, if it is as described above, the voltage lines L1,
When either one of L2, for example voltage line L1, is broken or loosened, the voltage between voltage line L2 and neutral line N is connected to impedance element A, impedance element B, and load E in series. When applied to the circuit, a voltage difference between the virtual neutral point C and the neutral wire N is generated, opening the circuit contacts L, O, and W.
It operates even though no abnormal voltage is applied to the load. For example, at a temporary construction site, AC voltage is applied only between one of the voltage lines L1, L2 and the neutral line N, and the load is connected during this period. Since it cannot be connected and used, when it is installed in a circuit breaker such as a circuit breaker or circuit breaker due to electrical leakage, disconnection, or overcurrent, the voltage line is L1,
There was a problem in that voltage had to be applied to both L2 and the neutral wire N. And this distribution line L1,L
At the beginning of applying voltage to 2 and N, voltage lines L1 and L2
There was also a problem that the device would operate if there was a delay in the application of either one of the voltage lines.

さらに配電線L1,L2,Nに雷サージ或は機
器の接点開閉時の開閉サージ等の単発的な電気的
サージが発生した際に時限回路5にて一定時間の
継続を判断し誤動作を少くするのであつてこの一
定時間が長ければ誤動作は少くなるが、中性線N
の欠落の際に動作するのが遅れることがあり好し
くなかつた。
Furthermore, when a one-off electrical surge occurs on the distribution lines L1, L2, N, such as a lightning surge or a switching surge when opening/closing a device contact, the time limit circuit 5 determines whether the surge continues for a certain period of time to reduce malfunctions. Therefore, the longer this certain period of time, the fewer malfunctions occur, but the neutral wire N
It was undesirable that there was a delay in operation when the function was missing.

(本発明の目的) 本発明は上記の様な点に鑑み、電圧線の少くと
も一方が欠落した際に信号を出力することをなく
しさらに電圧線の少くとも一方と中性線との間の
みに交流電圧を印加し負荷を接続しても信号を出
力することをなくし而も配電線に電圧を印加する
初期に電圧線の少くとも一方の電圧線の印加が遅
れた際に信号を出力することをなくして中性線の
欠落の際に信号を出力出来る様にすると共に配電
線に雷サージ或は機器の接点開閉時の開閉サージ
等の単発的な電気的サージが発生した際に誤動作
を少くして中性線の欠落の際の動作の遅れを少く
することを目的としたものである。
(Object of the present invention) In view of the above-mentioned points, the present invention eliminates the need to output a signal when at least one of the voltage lines is missing, and further eliminates the need to output a signal only between at least one of the voltage lines and the neutral line. It eliminates the need to output a signal even when an AC voltage is applied to the distribution line and a load is connected, and it also outputs a signal when the application of voltage to at least one of the voltage lines is delayed in the initial stage of applying voltage to the distribution line. This makes it possible to output a signal even when the neutral wire is missing, and also prevents malfunctions when a one-off electrical surge occurs in the distribution line, such as a lightning surge or a surge when opening/closing a device contact. The purpose of this is to reduce the delay in operation when the neutral wire is missing.

以下本発明を一実施例として掲げた図面第1図
の回路ブロツク図及び第2図乃至第5図の時間動
作特性図に基づいて説明すると、L1,L2,N
は交流単相3線式配電線であつて、中性線Nに対
する電圧線L1,L2の電圧V1,V2は夫々等
しい交流電圧が印加され且つ電圧線L1L2間の
電圧は交流電圧の2倍の電圧が印加されている。
1a,1bは一対の整流器であつて、中性線Nに
対する電圧線L1,L2の電圧を同一方向に整流
して一点Aに出力する。2は基準電圧設定回路で
あつて、平常時の一点Aの中性線Nに対する出力
電圧の最大電圧より高い電圧に基準電圧を設定し
ている。3は比較回路であつて、中性線Nに対す
る一点Aの出力電圧を入力してこの出力電圧と基
準電圧設定回路2の基準電圧とを比較しこの基準
電圧より出力電圧が高くなるときのみ信号を出力
する。4はクリツプ回路であつて、比較回路3の
入力電圧を基準電圧設定回路2の基準電圧より高
い電圧にてクリツプする。5は時限回路であつ
て、比較回路3の出力信号が一定時間継続すると
信号を出力する。6は増幅回路、7はスイツチン
グ回路、8は電磁引外し装置であつて、時限回路
5の出力を増幅回路6にて増幅しこの増幅回路6
の出力信号に応答してスイツチング回路7がスイ
ツチング動作して電磁引外し装置8を動作させ
る。9a,9b,9cは電圧線L1,L2と中性
線Nとに設けた電路接点であつて電磁引外し装置
8にて閉極より開極に引外される。10a,10
bは電圧線L1と中性線Nとの間の電圧線L2と
中性線Nとの間とに接続した負荷である。
The present invention will be explained below based on the circuit block diagram shown in FIG. 1 and the time operation characteristic diagrams shown in FIGS.
is an AC single-phase three-wire distribution line, and the voltages V1 and V2 of the voltage lines L1 and L2 with respect to the neutral line N are applied with equal AC voltages, respectively, and the voltage between the voltage lines L1 and L2 is twice the AC voltage. Voltage is applied.
1a and 1b are a pair of rectifiers, which rectify the voltages of voltage lines L1 and L2 with respect to the neutral line N in the same direction and output them to one point A. Reference numeral 2 denotes a reference voltage setting circuit, which sets the reference voltage to a voltage higher than the maximum voltage of the output voltage to the neutral wire N at one point A during normal operation. 3 is a comparison circuit which inputs the output voltage of one point A with respect to the neutral line N, compares this output voltage with the reference voltage of the reference voltage setting circuit 2, and outputs a signal only when the output voltage is higher than this reference voltage. Output. A clip circuit 4 clips the input voltage of the comparison circuit 3 to a voltage higher than the reference voltage of the reference voltage setting circuit 2. Reference numeral 5 denotes a time limit circuit which outputs a signal when the output signal of the comparator circuit 3 continues for a certain period of time. 6 is an amplifier circuit, 7 is a switching circuit, and 8 is an electromagnetic tripping device, which amplifies the output of the timer circuit 5 in the amplifier circuit 6.
In response to the output signal, the switching circuit 7 performs a switching operation to operate the electromagnetic tripping device 8. Reference numerals 9a, 9b, and 9c are electrical circuit contacts provided on the voltage lines L1, L2 and the neutral line N, which are tripped from a closed state to an open state by an electromagnetic tripping device 8. 10a, 10
b is a load connected between the voltage line L1 and the neutral line N, and between the voltage line L2 and the neutral line N.

尚、第2図は平常時の一点Aの中性線Nに対す
る出力電圧の時間動作特性図、第3図は中性線N
の点Bで断線或はゆるみ等の欠落した際の一点A
の中性線Nに対する出力電圧の時間動作特性図、
第4図は電圧線L1,L2のいずれか一方、例え
ば電圧線L1が欠落した際の一点Aの中性線Nに
対する出力電圧の時間動作特性図、第5図は配電
線L1,L2,Nに雷サージ或機器の接点開閉時
の開閉サージ等の単発的な電気的サージが発生し
た状態であつて、aは中性線Nに対する電圧線L
1,L2のいずれか一方の電圧の時間動作特性
図、bは中性線Nに対する一点Aの出力電圧の時
間動作特性図を示し、図中SVは基準電圧設定回
路2の基準電圧である。
In addition, Fig. 2 is a time behavior characteristic diagram of the output voltage with respect to the neutral line N at one point A under normal conditions, and Fig. 3 is a graph of the output voltage at the neutral line N.
One point A when there is a disconnection or looseness at point B.
A time behavior characteristic diagram of the output voltage with respect to the neutral line N,
Fig. 4 is a time behavior characteristic diagram of the output voltage with respect to the neutral line N of one point A when one of the voltage lines L1 and L2, for example, the voltage line L1 is missing, and Fig. A is a state in which a one-off electrical surge such as a lightning surge or a switching surge when a device contacts is opened/closed, and a is the voltage line L with respect to the neutral line N.
1 and L2, and b shows a time behavior characteristic diagram of the output voltage at one point A with respect to the neutral line N. In the figure, SV is the reference voltage of the reference voltage setting circuit 2.

而してこの動作状態を第1図に基づいて説明す
ると、平常時は電圧線L1,L2と中性線Nとの
夫々の電圧はほぼ等しく一点Aの中性線Nに対す
る出力電圧の最大電圧は第2図の如く基準電圧設
定回路2の基準電圧SVより低く従つて比較回路
3は信号を出力せず電路接点9a,9b,9cは
閉極を継続する。
To explain this operating state based on FIG. 1, under normal conditions, the voltages of the voltage lines L1, L2 and the neutral line N are approximately equal, and the maximum output voltage with respect to the neutral line N at one point A. is lower than the reference voltage SV of the reference voltage setting circuit 2 as shown in FIG.

さらに平常時の状態より中性線Nの点Bで断線
が生じ且つ負荷10a,10bのバランスが悪い
と電圧線L1,L2の中性線に対する夫々の交流
電圧V1,V2のバランスが崩れ一点Aの中性線
Nに対する出力電圧は半周期毎に高い電圧と低い
電圧とが交互に出力されこの高い電圧が第3図の
如く基準電圧設定回路2の基準電圧SVを越え比
較回路3は出力信号を出力し時限回路5にてこの
出力信号が一定時間継続するか否かを判断しこの
出力信号が一定時間継続すると出力信号を出力し
この時限回路5の出力信号を増幅回路6にて増幅
してスイツチング回路7をスイツチング動作させ
電磁引外し装置8を動作させて電路接点9a,9
b,9cを開極し配電線L1,L2,Nをしや断
する。
Furthermore, if a disconnection occurs at point B of the neutral wire N than in normal conditions and the loads 10a and 10b are unbalanced, the balance between the AC voltages V1 and V2 of the voltage lines L1 and L2 with respect to the neutral wire will be lost, and the voltage at point A will be lost. The output voltage to the neutral line N is alternately high and low every half cycle, and when this high voltage exceeds the reference voltage SV of the reference voltage setting circuit 2 as shown in FIG. A time limit circuit 5 determines whether this output signal continues for a certain period of time, and if this output signal continues for a certain period of time, an output signal is output, and the output signal of this time limit circuit 5 is amplified by an amplifier circuit 6. The switching circuit 7 is operated to operate the electromagnetic tripping device 8, and the circuit contacts 9a, 9 are operated.
b, 9c are opened and the distribution lines L1, L2, N are cut off.

而も前述した平常時の状態より電圧線L1,L
2のいずれか一方、例えば電圧線L1が欠落した
際は電圧V2のみが電圧線L2と中性線Nとの間
に印加されて負荷10bに供給され且つ一点Aの
中性線Nに対する出力電圧は第4図の如く基準電
圧発生回路2の基準電圧SVよりも低い半波の脈
流となり比較回路3は出力信号を出力せず電路接
点9a,9b,9cは閉極を継続する。即ち、電
圧線L1,L2の中性線Nに対する電圧V1,V
2のいずれか一方が印加されなくとも比較回路3
は出力信号を出力しないので、電圧線L1,L2
のいずれか一方が欠落した際に信号を出力するこ
とをなくしさらに電圧線L1,L2のいずれか一
方と中性線Nとの間のみに交流電圧を印加し負荷
を接続しても信号を出力することをなくし而も配
電線L1,L2,Nに電圧を印加する初期に電圧
線L1,L2のいずれか一方の電圧線の印加が遅
れた際に信号を出力することをなくして中性線N
の欠落の際に信号を出力出来る様にすることが出
来る。
However, the voltage lines L1 and L are lower than the normal state mentioned above.
2, for example, when the voltage line L1 is missing, only the voltage V2 is applied between the voltage line L2 and the neutral line N, and is supplied to the load 10b, and the output voltage with respect to the neutral line N at one point A. As shown in FIG. 4, there is a half-wave pulsating current lower than the reference voltage SV of the reference voltage generating circuit 2, and the comparator circuit 3 does not output an output signal and the circuit contacts 9a, 9b, and 9c continue to be closed. That is, the voltages V1, V of the voltage lines L1, L2 with respect to the neutral line N
Even if either one of 2 is not applied, the comparator circuit 3
does not output an output signal, so the voltage lines L1 and L2
This eliminates the need to output a signal when either one of the voltage lines L1 or L2 is missing, and in addition, AC voltage is applied only between either voltage line L1 or L2 and the neutral line N, and the signal is output even if a load is connected. In addition, it eliminates the need to output a signal when the application of voltage to one of the voltage lines L1, L2 is delayed in the initial stage of applying voltage to the distribution lines L1, L2, and N. N
It is possible to make it possible to output a signal when a signal is missing.

而も前述した平常時の状態より配電線L1,L
2,Nに雷サージ或は機器の接点開閉時の開閉サ
ージ等の単発的な電気的サージが発生し中性線N
に対する電圧線L1,L2のいずれか一方の電圧
に第5図aの如く電気的サージが重畳すると、一
点Aの中性線Nに対する出力電圧が電気的サージ
の重畳した高い電圧になり比較回路3に入力され
て基準電圧設定回路2の基準電圧SVより高くな
り信号を出力するが、第5図bの如く比較回路3
の入力電圧をクリツプ回路4により基準電圧設定
回路2の基準電圧SVより高い電圧にてクリツプ
しこの電圧以上が比較回路3に入力されない様に
したので時限回路5の一定時間がクリツプ回路4
を用いないものに比し短かくならないから時限回
路5にて電気的サージによる誤動作を少く出来
る。
However, from the normal state mentioned above, the distribution lines L1 and L
2. A one-off electrical surge, such as a lightning surge or a surge when opening/closing a device contact, occurs in the neutral line N.
When an electrical surge is superimposed on the voltage of one of the voltage lines L1 and L2 as shown in FIG. The signal is input to the reference voltage setting circuit 2 and becomes higher than the reference voltage SV of the reference voltage setting circuit 2, and a signal is output.
Since the input voltage of the time limit circuit 5 is clipped at a voltage higher than the reference voltage SV of the reference voltage setting circuit 2 by the clip circuit 4 to prevent a voltage higher than this voltage from being input to the comparator circuit 3, the fixed time of the time limit circuit 5 is
Since the time is not shorter than that without using the circuit, malfunctions due to electrical surges can be reduced in the time limit circuit 5.

さらに本発明を一実施例として掲げた図面第6
図の具体的な回路図に基づいて説明すると、電圧
線L1,L2と一点Aとの間に互いに電圧線L
1,L2側に順方向の整流器2a,2bを接続し
この一点Aと中性線Nとの間に比較回路3の分圧
抵抗R1,R2を接続しこの分圧点に基準電圧設
定回路2の定電圧ダイオードZD1を介して増幅
回路6とスイツチング回路7とを兼ねたサイリス
タSCRのゲートを接続しこのゲートと一点Aと
の間に時限回路5の抵抗R3とコンデンサC1と
を夫々並列接続しサイリスタSCRのカソードを
一点Aに接続しこのサイリスタSCRのアノード
と電圧線L1,L2との間に電磁引外し装置8の
トリツプコイルTCを介して互いにアノード側に
順方向の整流器D1,D2を接続しさらに分圧抵
抗R1,R2の分圧点と一点Aとの間にクリツプ
回路4の定電圧ダイオードZD2を接続しており、
中性線Nの一点Bで断線が生じ負荷10a,10
bのバランスが悪いと電圧線L1,L2の中性線
Nに対する夫々の交流電圧V1,V2のバランス
が崩れ一点Aの中性線Nに対する出力電圧は半周
期毎に高い電圧と低い電圧とが交互に出力されて
分圧抵抗R1,R2に印加されこの分圧点の一点
Aに対する電圧が定電圧ダイオードZD1の基準
電圧を越え時限回路5の一定時間の継続があると
サイリスタSCRがスイツチング動作してオン状
態となり電圧線L1,L2の一方より整流器D
1,D2の一方とトリツプコイルTCとサイリス
タSCRと整流器2a,2bの他方とを介して電
圧線L1,L2の他方に電流が流れトリツプコイ
ルTCが感動して電路接点9a,9b,9cを閉
極する。
Further, drawing No. 6 shows the present invention as an embodiment.
To explain based on the specific circuit diagram in the figure, voltage lines L1 and L2 and one point A are connected to each other.
Forward rectifiers 2a and 2b are connected to the 1 and L2 sides, voltage dividing resistors R1 and R2 of the comparator circuit 3 are connected between this point A and the neutral line N, and the reference voltage setting circuit 2 is connected to this voltage dividing point. The gate of the thyristor SCR, which also serves as the amplifier circuit 6 and the switching circuit 7, is connected through the constant voltage diode ZD1, and the resistor R3 and capacitor C1 of the time limit circuit 5 are connected in parallel between this gate and one point A. The cathode of the thyristor SCR is connected to one point A, and forward rectifiers D1 and D2 are connected between the anode of the thyristor SCR and the voltage lines L1 and L2 on the anode side of each other via the trip coil TC of the electromagnetic tripping device 8. Furthermore, a constant voltage diode ZD2 of the clip circuit 4 is connected between the voltage dividing points of the voltage dividing resistors R1 and R2 and one point A.
A disconnection occurs at one point B of the neutral wire N, and the loads 10a, 10
If b is unbalanced, the balance between the AC voltages V1 and V2 with respect to the neutral line N of voltage lines L1 and L2 will be lost, and the output voltage with respect to the neutral line N of one point A will change between high and low voltages every half cycle. The voltage is alternately outputted and applied to the voltage dividing resistors R1 and R2, and when the voltage at one point A of the voltage dividing point exceeds the reference voltage of the constant voltage diode ZD1 and continues for a certain period of time in the time limit circuit 5, the thyristor SCR performs a switching operation. The rectifier D is turned on from one of the voltage lines L1 and L2.
1. Current flows to the other voltage line L1, L2 through one side of D2, the trip coil TC, the thyristor SCR, and the other side of the rectifiers 2a, 2b, and the trip coil TC is moved to close the circuit contacts 9a, 9b, 9c. .

而も電圧線L1,L2のいずれか一方、例えば
電圧線L1が欠落した際は電圧V2のみが電圧線
L2と中性線Nとの間に印加されて負荷10bに
供給され且つ一点Aの中性線Nに対する出力電圧
は半波の脈流となつて分圧抵抗R1,R2に印加
されこの分圧点の一点Aに対する電圧は定電圧ダ
イオードZD1の基準電圧よりも低い脈流であつ
てサイリスタSCRはスイツチング動作せずオフ
状態を継続し電路接点9a,9b,9cは開極を
継続する。
Moreover, when one of the voltage lines L1 and L2, for example voltage line L1, is missing, only the voltage V2 is applied between the voltage line L2 and the neutral line N, and is supplied to the load 10b. The output voltage to the normal conductor N becomes a half-wave pulsating current and is applied to the voltage dividing resistors R1 and R2. The SCR does not perform any switching operation and remains off, and the circuit contacts 9a, 9b, and 9c continue to be open.

さらに配電線L1,L2,Nに単発的な電気的
サージが発生し中性線Nに対する一点Aの出力電
圧が電気的サージの重畳した高い電圧になると、
分圧抵抗R1,R2の分圧点の一点Aに対する電
圧は定電圧ダイオードZD1の基準電圧を越え且
つ定電圧ダイオードZD2の一定電圧にクリツプ
されるのであつて、このクリツプされた電圧が定
電圧ダイオードZD1を介して抵抗R3とコンデ
ンサC1とにより一定時間の継続を判断するの
で、クリツプされない電圧に比しこの一定時間が
短かくならず誤動作を少く出来る。
Furthermore, if a single electrical surge occurs in the distribution lines L1, L2, and N, and the output voltage at one point A to the neutral line N becomes a high voltage due to the superimposition of the electrical surge,
The voltage with respect to one point A of the voltage dividing point of the voltage dividing resistors R1 and R2 exceeds the reference voltage of the voltage regulator diode ZD1 and is clipped to the constant voltage of the voltage regulator diode ZD2, and this clipped voltage is applied to the voltage regulator diode. Since the continuation of a certain period of time is determined by resistor R3 and capacitor C1 via ZD1, this certain period of time is not shortened compared to a voltage that is not clipped, and malfunctions can be reduced.

さらに他の実施例として掲げた図面第7図の具
体的な回路図に基づいて説明すると、電圧線L
1,L2と中性線との間に夫々分圧抵抗R4,R
5,R6,R7を接続しこの分圧抵抗R4,R5
と分圧抵抗R6,R7との夫々の分圧点と一点A
との間に一点A側に順方向の整流器2a,2bを
接続しこの一点Aと中性線Nとの間に抵抗R8と
基準電圧設定回路2の定電圧ダイオードZD1及
び抵抗R9の直列回路とを接続して比較回路3を
構成しさらにこの一点Aと中性線Nとの間に一点
A側の定電圧ダイオードZD3と中性線N側の抵
抗R10との直列回路を接続しこの一点Aと中性
線Nとの間に定電圧ダイオードZD3と抵抗R1
0との接続点にベースを接続したトランジスタ
TR1のコレクタとエミツタとを一点A側のコレ
クタ抵抗を介して接続してクリツプ回路4を構成
し而も定電圧ダイオードZD1及び抵抗R9の直
列回路の接続点にトランジスタTR2のベースを
接続しこのエミツタを一点Aに接続すると共にこ
のコレクタをホトカプラの発光ダイオードLED
を介して中性線Nに接続しさらにこのホトカプラ
の受光用ホトトランジスタTR3のエミツタをス
イツチング回路7のサイリスタSCRのゲートに
接続しこのサイリスタSCRのゲートとカソード
との間にコンデンサC2と抵抗R12とを並列接
続しさらに電圧線L1,L2間にダイオードブリ
ツジDBの入力を接続しこのダイオードブリツジ
DBの出力の一方に電磁引外し装置8のトリツプ
コイルTCを介してサイリスタSCRのアノードを
接続しこのサイリスタSCRのカソードをダイオ
ードブリツジDBの出力の他方に接続し而もダイ
オードブリツジDBの出力の一方に抵抗R13を
介して定電圧ダイオードZD4のカソードを接続
しこの定電圧ダイオードZD4のアノードをダイ
オードブリツジDBの出力の他方に接続しこの定
電圧ダイオードZD4のカソードとホトトランジ
スタTR3のコレクタとの間に抵抗R13を接続
する。尚、C3は抵抗R9に並列接続したコンデ
ンサであつて、このコンデンサC3とトランジス
タTR2と発光ダイオードLEDとホトトランジス
タTR3とコンデンサC2と抵抗R14とで時限
回路5を介ねる増幅回路6を構成している。
Further, the voltage line L
1, voltage dividing resistors R4, R between L2 and the neutral line, respectively.
5, R6, R7 are connected and this voltage dividing resistor R4, R5
and the respective voltage dividing points of voltage dividing resistors R6 and R7 and one point A
A forward rectifier 2a, 2b is connected between the point A and the neutral wire N, and a series circuit of a resistor R8, a constant voltage diode ZD1 of the reference voltage setting circuit 2, and a resistor R9 is connected between this point A and the neutral wire N. A series circuit consisting of a constant voltage diode ZD3 on the side of point A and a resistor R10 on the side of neutral line N is connected between this point A and the neutral wire N. A constant voltage diode ZD3 and a resistor R1 are connected between the
Transistor whose base is connected to the connection point with 0
A clip circuit 4 is constructed by connecting the collector and emitter of TR1 via a collector resistor on the A side, and the base of the transistor TR2 is connected to the connection point of the series circuit of the constant voltage diode ZD1 and the resistor R9. Connect to one point A and connect this collector to a photocoupler light emitting diode LED.
Furthermore, the emitter of the phototransistor TR3 for light reception of this photocoupler is connected to the gate of the thyristor SCR of the switching circuit 7, and a capacitor C2 and a resistor R12 are connected between the gate and cathode of the thyristor SCR. are connected in parallel, and the input of the diode bridge DB is connected between the voltage lines L1 and L2.
The anode of the thyristor SCR is connected to one of the outputs of the DB via the trip coil TC of the electromagnetic trip device 8, and the cathode of this thyristor SCR is connected to the other output of the diode bridge DB. The cathode of a constant voltage diode ZD4 is connected to one side via a resistor R13, the anode of this constant voltage diode ZD4 is connected to the other output of the diode bridge DB, and the cathode of this constant voltage diode ZD4 and the collector of the phototransistor TR3 are A resistor R13 is connected between them. Note that C3 is a capacitor connected in parallel to resistor R9, and this capacitor C3, transistor TR2, light emitting diode LED, phototransistor TR3, capacitor C2, and resistor R14 constitute an amplifier circuit 6 via a timer circuit 5. There is.

而してこの動作状態を説明すると中性線Nの一
点Bで断線が生じ負荷10a,10bのバランス
が悪いと電圧線L1,L2の中性線Nに対する
夫々の交流電圧V1,V2のバランスが崩れ一点
Aの中性線Nに対する出力電圧は周期的に高い電
圧と低い電圧とが交互に出力されこの高い電圧が
定電圧ダイオードZD1の基準電圧を越えると抵
抗R9と定電圧ダイオードZD1との直列回路に
電流が流れこの抵抗R9に電圧が出力されコンデ
ンサC3を充電しトランジスタTR2がオン状態
となつて発光ダイオードLEDを発光させこの光
をホトトランジスタTR3が受光してオン状態と
なり抵抗R13と抵抗R14とホトトランジスタ
TR3とを介してサイリスタSCRのゲートに電圧
を印加する。さらにこの電圧はコンデンサC2と
抵抗R12とで一定時間の継続を付与してサイリ
スタSCRをスイツチング動作してオン状態にし
ダイオードブリツジDBの一方より他方にトリツ
プコイルTCとサイリスタSCRとを介して電流が
流れトリツプコイルTCが感動して電路接点9a,
9b,9cを開極する。尚、コンデンサC3及び
抵抗R9とはコンデンサC2及び抵抗R12と同
様に一定の時間を付与している。
To explain this operating state, if a disconnection occurs at point B of the neutral wire N and the load 10a, 10b is unbalanced, the balance of the AC voltages V1, V2 of the voltage lines L1, L2 with respect to the neutral wire N becomes unbalanced. The output voltage with respect to the neutral wire N of the collapse point A is periodically outputted as a high voltage and a low voltage alternately, and when this high voltage exceeds the reference voltage of the voltage regulator diode ZD1, the resistor R9 and the voltage regulator diode ZD1 are connected in series. A current flows through the circuit and a voltage is output to this resistor R9, charging the capacitor C3, turning on the transistor TR2, causing the light emitting diode LED to emit light, and the phototransistor TR3 receiving this light, turning on the resistor R13 and the resistor R14. and phototransistor
A voltage is applied to the gate of the thyristor SCR via TR3. Furthermore, this voltage is applied for a certain period of time by capacitor C2 and resistor R12 to switch the thyristor SCR and turn it on, causing current to flow from one side of the diode bridge DB to the other via the trip coil TC and the thyristor SCR. The trip coil TC is moved and the circuit contact 9a,
9b and 9c are opened. Incidentally, a fixed time period is given to the capacitor C3 and the resistor R9, similarly to the capacitor C2 and the resistor R12.

而も電圧線L1,L2のいずれか一方、例えば
電圧線L1が欠落した際は電圧V2のみが電圧線
L2と中性線Nとの間に印加されて負荷10bに
供給され且つ一点Aの中性線Nに対する出力電圧
は定電圧ダイオードZD1の基準電圧より低い脈
流となり抵抗R9には電圧が発生せず且つサイリ
スタSCRはスイツチング動作せずオフ状態を継
続し電路接点9a,9b,9cは閉極を継続す
る。
Moreover, when one of the voltage lines L1 and L2, for example voltage line L1, is missing, only the voltage V2 is applied between the voltage line L2 and the neutral line N, and is supplied to the load 10b. The output voltage to the normal conductor N becomes a pulsating current lower than the reference voltage of the constant voltage diode ZD1, and no voltage is generated across the resistor R9, and the thyristor SCR does not perform a switching operation and continues to be off, and the circuit contacts 9a, 9b, and 9c are closed. Continue the pole.

さらに配電線L1,L2,Nに単発的な電気的
サージが発生し中性線Nに対する一点Aの出力電
圧が電気的サージの重畳した高い電圧になると抵
抗R9と定電圧ダイオードZD1との直列回路に
電流が流れ且つ定電圧ダイオードZD3と抵抗R
10との直列回路に電流が流れて抵抗R10に電
圧が発生しトランジスタTR1がオン状態となり
ほぼ定電圧ダイオードZD3の一定電圧にクリツ
プされるのであつて、このクリツプされた電圧が
定電圧ダイオードZD1を介して抵抗R9とコン
デンサC3とにより一定時間の継続を判断するの
で、クリツプされない電圧に比しこの一定時間が
短かくならず誤動作を少く出来る。
Furthermore, when a single electrical surge occurs in the distribution lines L1, L2, and N, and the output voltage at one point A relative to the neutral wire N becomes a high voltage due to the superposition of the electrical surge, the series circuit of the resistor R9 and the voltage regulator diode ZD1 Current flows through the constant voltage diode ZD3 and the resistor R
Current flows through the series circuit with 10 and a voltage is generated across the resistor R10, turning on the transistor TR1 and clipping it to the constant voltage of the constant voltage diode ZD3. Since the continuation of a certain period of time is determined by the resistor R9 and the capacitor C3, this certain period of time is not shortened compared to a voltage that is not clipped, and malfunctions can be reduced.

さらに上記実施例は交流単相3線式配電線を掲
げたが交流3相4線式配電線でもよく、中性線N
の有する配電線であれば限定しない。
Further, although the above embodiment uses an AC single-phase three-wire distribution line, an AC three-phase four-wire distribution line may also be used, and the neutral line N
There is no limitation as long as it is a distribution line owned by

(効 果) かように本発明は、交流単相3線式配電線或は
交流3相4線式配電線等の中性線を有する配電線
の中性線に対する電圧線の電圧を複数の整流器に
て同一方向に整流して一点に出力し、この一点の
中性線に対する出力電圧を比較回路に入力してこ
の出力電圧の平常時の電圧より高い電圧に設定し
た基準電圧設定回路の基準電圧を前記出力電圧が
越えるときのみ信号を出力したので、電圧線のい
ずれか一方が欠落した際に信号を出力することを
なくしさらに電圧線のいずれか一方と中性線との
間のみに交流電圧を印加し負荷を接続しても信号
を出力することをなくし而も配電線に電圧を印加
する初期に電圧線のいずれか一方の電圧線の印加
が遅れた際に信号を出力することをなくして中性
線の欠落の際に信号を出力出来る。而も比較回路
の入力電圧をクリツプ回路により基準電圧設定回
路の基準電圧より高い電圧にてクリツプし、比較
回路の出力信号が一定時間継続した際に時限回路
にて信号を出力したので、従来のものに比し、配
電線に雷サージ或は機器の接点開閉時の開閉サー
ジ等の単発的な電気的サージが発生した際に時限
回路の一定時間が短くならないから誤動作を少く
出来、中性線の欠落の際の動作の遅れを少く出来
る効果がある。
(Effect) As described above, the present invention can reduce the voltage of a plurality of voltage lines with respect to the neutral line of a distribution line such as an AC single-phase three-wire distribution line or an AC three-phase four-wire distribution line. A reference voltage setting circuit standard in which the voltage is rectified in the same direction by a rectifier and output to one point, and the output voltage for the neutral line of this point is input to a comparator circuit and set to a voltage higher than the normal voltage of this output voltage. Since a signal is output only when the output voltage exceeds the voltage, it is no longer necessary to output a signal when one of the voltage lines is missing, and furthermore, an alternating current is generated only between one of the voltage lines and the neutral line. It eliminates the need to output a signal even when voltage is applied and a load is connected, but it also outputs a signal when there is a delay in the application of voltage to one of the voltage lines at the beginning of applying voltage to the distribution line. Without it, a signal can be output when the neutral wire is missing. In addition, the input voltage of the comparator circuit is clipped at a voltage higher than the reference voltage of the reference voltage setting circuit using a clip circuit, and when the output signal of the comparator circuit continues for a certain period of time, a signal is output by a time limit circuit. In contrast, when a one-off electrical surge occurs on the distribution line, such as a lightning surge or a surge when opening/closing the contacts of equipment, the fixed time of the timer circuit does not shorten, so malfunctions can be reduced, and the neutral line This has the effect of reducing the delay in operation when the data is missing.

【図面の簡単な説明】[Brief explanation of the drawing]

図面第1図乃至第5図は本発明の中性線欠落検
出装置の一実施例を示し、第1図は回路ブロツク
図、第2図は一点Aの中性線Nに対する出力電圧
の平常時の時間動作特性図、第3図は一点Aの中
性線Nに対する出力電圧の中性線欠落時の時間動
作特性図、第4図は一点Aの中性線Nに対する出
力電圧の電圧線のいずれか一方が欠落した際の時
間動作特性図、第5図は配電線に電気的ノイズが
発生した状態であつてaは電圧線L1,L2のい
ずれか一方の中性線Nに対する電圧の時間動作特
性図、bは一点Aの中性線Nに対する電圧の時間
動作特性図、第6図は本発明の中性線欠落検出装
置の一実施例の具体的な回路図、第7図は本発明
の中性線欠落検出装置の他の実施例の具体的な回
路図、第8図は従来の中性線欠落検出装置の回路
ブロツク図を示す。 L1,L2……電圧線、N……中性線、1a,
1b……整流器、A……一点、2……基準電圧設
定回路、3……比較回路、4……クリツプ回路、
5……時限回路、6……増幅回路、7……スイツ
チング回路、8……電磁引外し装置、9a,9
b,9c……電路接点、10a,10b……負
荷、SV……基準電圧、R1乃至R14……抵抗、
C1乃至C3……コンデンサ、D1,D2……整
流器、ZD1乃至ZD4……定電圧ダイオード、
TR1及びTR2……トランジスタ、TR3……ホ
トトランジスタ、SCR……サイリスタ、TC……
トリツプコイル、LED……発光ダイオード、DB
……ダイオードブリツジ。
Figures 1 to 5 show an embodiment of the neutral line missing detection device of the present invention, where Figure 1 is a circuit block diagram and Figure 2 is a normal state of the output voltage with respect to the neutral line N at one point A. Figure 3 is a diagram of the time behavior characteristics of the output voltage with respect to the neutral line N of one point A when the neutral line is missing, and Figure 4 is a diagram of the voltage line of the output voltage with respect to the neutral line N of one point A. Figure 5 shows the time behavior characteristic diagram when one of the voltage lines is missing, where electrical noise is generated in the distribution line, and a is the voltage time with respect to the neutral line N of either voltage line L1 or L2. Fig. 6 is a specific circuit diagram of an embodiment of the neutral line missing detection device of the present invention; A specific circuit diagram of another embodiment of the neutral line missing detection device according to the invention, FIG. 8 shows a circuit block diagram of a conventional neutral line missing detection device. L1, L2... Voltage line, N... Neutral line, 1a,
1b... Rectifier, A... One point, 2... Reference voltage setting circuit, 3... Comparison circuit, 4... Clip circuit,
5... Time limit circuit, 6... Amplifying circuit, 7... Switching circuit, 8... Electromagnetic tripping device, 9a, 9
b, 9c...Circuit contact, 10a, 10b...Load, SV...Reference voltage, R1 to R14...Resistance,
C1 to C3... Capacitor, D1, D2... Rectifier, ZD1 to ZD4... Constant voltage diode,
TR1 and TR2...transistor, TR3...phototransistor, SCR...thyristor, TC...
Trip coil, LED...light emitting diode, DB
...Diode bridge.

Claims (1)

【特許請求の範囲】[Claims] 1 交流単相3線式配電線或は交流3相4線式配
電線等の中性線を有する配電線の中性線に対する
電圧線の電圧を同一方向に整流して一点に出力す
る複数の整流器と、この一点の前記中性線に対す
る出力電圧を入力しこの出力電圧の平常時の電圧
より高い電圧に設定した基準電圧設定回路の基準
電圧を前記出力電圧が越えるときのみ信号を出力
する比較回路と、この比較回路の出力信号が一定
時間継続した際に信号を出力する時限回路と、前
記比較回路の入力電圧を前記基準電圧設定回路の
基準電圧より高い電圧にてクリツプするクリツプ
回路とでなる中性線欠落検出装置。
1 A plurality of AC single-phase three-wire distribution lines or AC three-phase four-wire distribution lines that rectify the voltage of the voltage line with respect to the neutral line in the same direction and output it to one point. A comparison that outputs a signal only when the output voltage exceeds the reference voltage of a reference voltage setting circuit that inputs the output voltage of the rectifier and the neutral wire at this one point and sets the output voltage to a higher voltage than the normal voltage. a time limit circuit that outputs a signal when the output signal of the comparison circuit continues for a certain period of time; and a clip circuit that clips the input voltage of the comparison circuit to a voltage higher than the reference voltage of the reference voltage setting circuit. Neutral line missing detection device.
JP3674080A 1980-03-21 1980-03-21 Neutral wire fault detector Granted JPS56133933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3674080A JPS56133933A (en) 1980-03-21 1980-03-21 Neutral wire fault detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3674080A JPS56133933A (en) 1980-03-21 1980-03-21 Neutral wire fault detector

Publications (2)

Publication Number Publication Date
JPS56133933A JPS56133933A (en) 1981-10-20
JPS631808B2 true JPS631808B2 (en) 1988-01-14

Family

ID=12478119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3674080A Granted JPS56133933A (en) 1980-03-21 1980-03-21 Neutral wire fault detector

Country Status (1)

Country Link
JP (1) JPS56133933A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59135032U (en) * 1983-02-28 1984-09-10 松下電工株式会社 Open phase sensor
JPS63240316A (en) * 1987-03-26 1988-10-06 富士電機株式会社 Leakage breaker
JPH0217823A (en) * 1988-07-01 1990-01-22 Tenpaale Kogyo Kk Abnormal voltage detection breaker

Also Published As

Publication number Publication date
JPS56133933A (en) 1981-10-20

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