JPS63197370A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high density integration, by constituting a dynamic RAM in a structure wherein a stack type and a trench type are unified in a body. CONSTITUTION:On a silicon substrate 11, a trench 13 is formed, in which a drain region 14 serving as a bit line, a p<-> type layer 17 and an n<+> type source region 18 are formed from the bottom. Thereon a stacked capacitor is constituted of a capacitor electrode 21 composed of a polysilicon layer, a capacitor insulation film 22 of SiO2 and a cell plate 23. A word line 27 of Al connected to a gate electrode 12 via a contact window 20 is formed. By applying such a structure, the trenches 13 are arranged as closely as possible, so that the high density integration is enabled.

Description

[Detailed Description of the Invention] [Summary] DR composed of vertical transistors of diffusion layer bit lines
This is a structure in which an AM cell has a stacked capacitor on top of a substrate, and a method for manufacturing the same.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, the present invention relates to a semiconductor device and a method for manufacturing the same.
(memory) cell and its manufacturing method.

[Conventional technology]

Several DRAM cell structures are known.

A DRAM cell called a Brehner type is shown in the cross-sectional view and plan view in FIGS.
is a silicon substrate, 32 and 33 are source and drain regions formed on the same substrate, 34 is a transfer gate that serves as a word line made of polycrystalline silicon (polysilicon), and 35 is a cell made of polysilicon. The plate, 36 is the pinto life (BL) of aluminum (AI) in contact with the drain region 33, and 37 is the gate oxide film (Mf) of silicon dioxide:17 (5iO2).
J thickness is, for example, 300 mm), 38 is a SiO2 capacitor insulating film with a thickness of, for example, 150 mm, and 39 is a phosphorus-silicate glass (PSG) film doped with phosphorus, for example. A cover membrane is made.

FIG. 3) is a plan view of the DRAM cell shown in FIG.

A stacked capacitor type DRAM cell is shown in cross section in FIG. 4, and in this type of DRAM cell, the capacitor 40 in FIG. 3(a) forms a polysilicon film 41 as shown,
The cell plate 35 is stacked on top of the cell plate 35 to increase capacitance.

The trench-type DRAM cell is shown in the cross-sectional view of FIG. 5, and the cell plate 35 is formed in a shape buried in trenches 43 that are dug in the substrate 31 to a depth of 5 μm.

A cell plate type DRAM cell in which the substrate serves as a cell plate and contacts the source side is shown in a cross-sectional view in FIG. .

Recently, a trenched transistor capacitor (TTC) type DRAM cell, which is shown in cross section in FIG. A diffusion layer 44 is formed, a word line 34 is formed above the trench 42, a capacitor is formed in the trench below the word line, and the cell plate is defined by the substrate.

In the trench type DRAM cell described above, a selectively grown epitaxial layer is generally used to form a transistor.

[Problem that the invention seeks to solve]

In DRAM cells, there are problems of increasing the degree of integration and increasing capacitance, and these two demands are mutually contradictory. That is, an important issue is how to increase the capacitance while miniaturizing the DRAM cell.

Regarding the degree of integration, with a 100mm' chip as standard, the limit for brainer-type DRAM cells is 1 megabit, for stacked cabbage it is 4 megabits, and for trench type substrate plate type, it is said that 16 megabits is the limit. This is not known at present, but it is said that a higher degree of integration may be obtained.

Regarding the size of capacitance, the capacitance required for DRAM is generally 30 to 40 fF from the viewpoint of suppressing the soft error rate. The trench type is advantageous in terms of securing capacitance, but as mentioned above, the TTC type requires a trench with a considerable depth of 8 μm, making it difficult to manufacture.

The present invention was created in view of these points, and an object of the present invention is to provide a miniaturized DRAM cell in which the trench depth is shallow and the capacitor is sufficiently large, and a method for manufacturing the same. do.

[Means for solving problems]

FIGS. 1(a) and (g)) show a DRAM which is an embodiment of the present invention.
11 is a semiconductor substrate of one conductivity type, for example, a p-type silicon substrate; 12 is an n-type impurity diffusion region that becomes a gate electrode; 13 is a trench dug in the silicon substrate 11; 14 is an n1 type drain region that will become a bit line, 15 is a CVD 5i02 film deposited by chemical vapor deposition (CVD), and 16 is a 5i02 film that will be an insulating film.
17 is a p- type layer, 18 is an n+ type source region, 19
is a CVD 5iOz film, 20 is a contact window, and 21 is a polysilicon H'i! (capacitor electrode), 22 is an insulating film (5i02 film), 23 is a cell plate formed by depositing polysilicon, 24 is an insulating film (5iOz film), 2
5 is a doped PSG film, 26 is a contact window, and 27 is A! 28 is a cover film made of PSG.

In the DRAM cell according to the present invention, a trench 13 is formed in a silicon substrate 11, and in this trench 13, from below, a drain region 14 which becomes a bit line, a p- type layer 17, an n+
A type source region 1B is formed, on which a capacitor is formed by a polysilicon layer 21, 5iOz N*22, and a cell plate 23, and an AJ word line 27 is provided, which is in contact with the gate electrode 12 through a contact window 26. It is.

[Effect]

In the DRAM cell described above, the depth of the trench 13 is formed shallower than that of the conventional trench capacitor type, and since the capacitor is of a stacked type, the capacitance is large. Since the capacitor is formed on the substrate side above the transistor, the area is smaller than the conventional example, and the manufacturing method is the same as that of a trench capacitor type DRAM cell, but since the trench is shallow, it can be implemented more easily. It is.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The DRAM cell shown in FIG. 1 is shown in FIG.
.

It occupies approximately the same area as the TTC type DRAM cell described above, and is advantageous for high integration. In the TTC type, the trench was about 8 μm, whereas the DRA of the present invention
The M cell is as easy to manufacture as the trench type capacitor described with reference to FIG. 5, and has the advantage of being small in area and easy to manufacture. A drain region 14 that becomes a bit line is provided on the substrate side, that is, in the trench 13, and a capacitor is formed above the transistor formed in the trench 13 using a stacked capacitor type DRA described with reference to FIG.
Since it is made in the same way as the M cell, a sufficiently large capacitance can be obtained.

Next, the present invention will be explained in detail with reference to FIG.

For example, phosphorus is added to a p-type silicon substrate by lXl0''/c
Ions are implanted at a dose of m2 and an acceleration voltage of 150 KeV, and the implanted phosphorus ions are driven in by annealing to form the gate electrode 12 as shown in the cross-sectional view of FIG. 2(a). This method is the same as the method for making wells for CMO5) transistors.

Next, by reactive ion etching (RIE) using SF6, a trench 13 with a depth of 2 to 3 .mu.m is formed through the gate electrode 12 as shown in FIG. 2 (bl).

Subsequently, a 5i02 film is formed to a thickness of 500 nm on the surface of the silicon substrate 11 including the trench 13 by thermal oxidation, and an SiO2 film 16a on the trench wall is formed by anisotropic etching.
Leave only. The 5i02 film removed by this etching is shown by dotted lines in the figure. The trench 13 is formed to be elongated in the direction perpendicular to the plane of the paper, and its state is shown in the right plan view of FIG. 2(C).

Next, by epitaxial growth using silane and H2 gas, the trench 13 is grown as shown in the left cross-sectional view of FIG. 2(C).
An epitaxial layer is formed at the bottom of the wafer, and a drain region 14 shown in FIG. 1 is formed by ion implantation of n-type impurities. Drain region 14 becomes a bit line. The right side of the figure is a plan view showing bit lines.

Next, CVD SiO 15a is embedded as shown by the dotted line in the cross-sectional view of FIG. 2(d), and it is planarized as shown by the solid line in the same figure.

Next, a resist 50 is applied to the entire surface of the substrate, patterned as shown in the plan view of FIG. 2 (el), and CVD
When the SiO□ 15a is etched, the n+ type drain region 14 is exposed as shown in the plan view of FIG.

Next, the surface of the trench 13 is oxidized (gate oxidation) to form 5i02I! l! is formed, and the 5iOz film on the bottom surface, that is, the surface of the drain region 14 is removed by anisotropic etching, leaving the 5iO2 film 16b on the wall surface of the trench. The SiO+ films 16a and 16b constitute a 5iOz film 16 shown in FIG. 1 (al) (FIG. 2 (see)).

Next, a p- type layer 17 is formed by selective epitaxial growth, ions are implanted for vth control to lower the impurity concentration around it, a source region 18 is formed by subsequent selective epitaxial growth, and the same region is made into an n+ type layer by ion implantation. The transistor is then completed.

Next, as shown in FIG. 2(h), a CVD 5iOz film 19 is formed on the silicon substrate 11, and a contact window 20 is opened therein. Note that since there is no change in the transistor formed on the substrate in FIG. 2 (In1 or lower), the same portion is omitted.

Next, polysilicon is grown on the silicon substrate 11 and patterned as shown in FIG. 2(1) to form a capacitor electrode 21 and its surface is oxidized to form a capacitor insulating film 22.

Next, polysilicon is deposited again, buttered to form the cell plate 23, and an insulating film (SiO+ film) 24 is formed on the surface of the cell plate 23 by oxidation.
The capacitor is completed (Fig. 2 (J)).

Next, a doped PSG film 25 is formed, and the PSG film 2
5, a contact window 26 for making contact with the gate electrode 12 is opened (FIG. 2(g)). Subsequently, AE is deposited on the entire surface and patterned to form a word line 27, and a PSG cover film 28 is deposited thereon to form the DRAM cell shown in FIG.

The transistor shown in FIG. 1 can be divided into two and used as two cells.

〔Effect of the invention〕

As described above, according to the present invention, both electrodes and the source of the capacitor are not in contact with the substrate in areas other than the transistor area, so the soft error rate can be kept low, and the capacitor can be easily separated. is easy to use and enables miniaturization.

[Brief explanation of the drawing]

FIG. 1(a) and crest) are a sectional view and a plan view of an embodiment of the present invention,
Figures 2+8) to (k) are diagrams of the process of making an embodiment of the present invention, Figure 3 is a diagram of a Brainer type DRAM cell, and its (a) and crest) are cross-sectional views and plan views, Figure 4 5 is a sectional view of a stacked capacitor type DRAM cell, FIG. 5 is a sectional view of a trench type DRAM cell, FIG. 6 is a sectional view of a cell plate type DRAM cell, and FIG. 7 is a sectional view of a TTC type DRAM cell. 1 and 2, 11 is a silicon substrate, 12 is a gate electrode, 13 is a trench, 14 is a drain region (bit line), and 15 is a CVD film.
5iOz film, 16, 16a, 16b is 5iOz H'As1
7 is a p-type layer, 18 is a source region, 19 is a CVD 5iOz film, 20 is a contact window, 21 is a capacitor electrode, 22 is a capacitor insulating film, 23 is a cell plate, 24 is a 5i02 film, 25 and a PSG film, 26 is a contact window, 27 is a word line, and 2 is a cover membrane. Agent: Patent Attorney Hajime Kuki Agent: Patent Attorney Yoshiyuki Osuga #tT! 14 *nil/+l I? -IX1m 1st flash (b) (Bi-Y trishi) 14 ``I beg for the shi number 0 oysters cum 11 Kama-zukuri gorge i, ako 2nd figure non+!咥岨1'lrih appeals to the Hu Ming side welcome θ11 mosaku) BL area 2nd figure ot E month middle 4 mu to 1 made 1 knee Ti4 2nd figure 2 - Dingma, [)RAMt+ 7+51 Figure 3 Staff Toyota Inozushi 94jlDRAMt! If/grow mFigure 4-e+ref'lay b"l DRAM-grshia@flJ
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Claims (2)

[Claims] (1) In a dynamic random access memory cell, a trench (13) is provided that penetrates a gate electrode (12) of an opposite conductivity type made in a semiconductor substrate (11) of one conductivity type, and a trench (13) is provided inside the trench (13). A transistor consisting of a drain region (14) serving as a bit line of opposite conductivity type, a layer of the same conductivity type (17) and a source region (18) of opposite conductivity type is provided from below, and a capacitor electrode (21) is provided on the transistor. A semiconductor device characterized in that a capacitor consisting of a capacitor insulating film (22) and a cell plate (23) is arranged, and a word line (27) in contact with a gate electrode (12) is arranged above the capacitor. (2) A step of forming a gate electrode (12) of an opposite conductivity type on a semiconductor substrate (11) of one conductivity type by impurity diffusion, forming a trench (13) penetrating the gate electrode (12), and forming a trench (13) penetrating the gate electrode (12); ), a step of forming a transistor comprising a layer (17) of the same conductivity type and a source region (18) of the opposite conductivity type, a capacitor electrode (21) making contact with the source region (18) on the transistor region, and a capacitor insulating film. (22), the step of forming a capacitor consisting of a cell plate (23), a word line (
27) on the capacitor.