JPS6319958B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a control method for a magnetic bubble memory used as a storage device for electronic computing devices and the like.

(2) Background of the technology Magnetic bubble utilization devices that use magnetic bubbles to store information, perform logical operations, etc. are nonvolatile, have high storage density, and low power consumption, and are solid-state devices that do not contain any mechanical elements. Because of its various characteristics, such as extremely high reliability, it is expected to have a promising future as a large-capacity memory.

This magnetic bubble memory element is made by forming a thin film of magnetic garnet by liquid phase epitaxial growth on a Gatrium/Gallium/Garnet single crystal substrate, and then forming a pattern such as a Taber or a half-disk in a matrix using a permalloy thin film. This creates a bubble propagation path.
The bubbles generated by the bubble generator are guided to the propagation path, and if there are bubbles in the pattern, it is “1”.
If there is no such information, the information is stored as "0".

Conventionally, a parity check method has been used to check whether this information has been read without error. For example, in the case of an 8-bit interface, this parity check method includes even number parity and odd number parity. One parity bit is added, and if the parity is even among the total 9 bits, it is considered normal if there is an even number of 1s. If the parity is odd, then if there is an odd number of 1's, it is determined to be normal.

(3) Prior Art and Problems FIG. 1 is a diagram for explaining a conventional magnetic bubble memory control system. In the same figure, 1 is
BUST (operating status display signal) generation circuit, 2 is RDA
(Data read permission signal) generation circuit, 3 is TDRA
(Write data permission signal) generation circuit, 4 is a (command end) generation circuit, 5 is a check bit generation circuit, 6 is a bubble memory controller equipped with the above interface register, 7 is an external device, 8
1 and 2 show parity check circuits in the external device, respectively.

In the status register of such a conventional bubble memory controller, RDA, TDRA,
Signals such as CME and BUSY are generated asynchronously with external devices.

FIG. 2 is a diagram showing a time chart in the bubble memory controller of FIG. 1. In the figure, A is a read signal, B is an external output signal such as BUSY, C is a parity check signal, and arrow P
indicates each inspection point.

When the data changes at the inspection point P as shown in FIG. 2, the parity bit created based on the data is sent out with a slight delay due to the delay. For this reason, conventional control systems sometimes cause parity check errors.

(4) Object of the Invention In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a magnetic bubble memory control system that prevents parity check malfunctions.

(5) Structure of the Invention According to the present invention, in a magnetic bubble memory control device equipped with an interface register with an external device, the output side of the interface register is activated by a read signal from the external device. By providing a magnetic bubble memory control method, the read data of the interface register is output in synchronization with an external device so that the data does not change during read. It is composed of

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a diagram for explaining the magnetic bubble memory control method according to the present invention. In the same figure, 11
is the BUSY (operating status display signal) generation circuit, and 12 is the
RDA (data read permission signal) generation circuit, 13
TDRA (write data permission signal) generation circuit, 14
are CME (command end) generation circuits, 15 to 18
19 is a flip-flop circuit connected to the above circuit, 19 is a check bit generation circuit, 20 is a bubble memory controller equipped with the above interface register, 24 is an external device, and 22 is a parity check circuit in the external device. .

As shown in the figure, the bubble memory controller that can implement the bubble memory control method of the present invention is BUSY.
Flip-flop circuits 15 to 18 which are activated by a read signal from an external device 21 are inserted on the output side of each of the interface registers such as the generation circuit 11, the RDA generation circuit 12, the TDRA generation circuit 13, and the CME generation circuit 14.

FIG. 4 is a diagram showing a time chart in FIG. 3. In the same figure, A is a read signal and B is a read signal.
denotes an input from the BUSY generating circuit etc. to the flip-flop circuit, C denotes an output sent from the BUSY generating circuit etc. to an external device via the flip-flop circuit, D denotes a parity bit, and arrow P denotes a test point.

In FIG. 4, when a signal whose data state may change during reading is output through a flip-flop circuit, the flip-flop circuit is activated at the beginning a of a read signal A from an external device. Therefore, during reading, even if the data changes at the inspection point P, the external output C and parity bit D from the BUSY generating circuit do not change. Malfunctions of the parity check are therefore prevented.

FIG. 5 is a diagram for explaining another embodiment of the magnetic bubble memory control method according to the present invention. In this figure, the same parts as in FIG. 3 are designated by the same reference numerals. This embodiment differs from the previous embodiment in that the previous embodiment uses a read signal from an external device to operate the flip-flop circuit, whereas this embodiment uses a synchronous clock signal from an external device.

FIG. 6 is a diagram showing a time chart in FIG. 5. In the same figure, A is a read signal and B is a read signal.
is the clock signal of the external device, C is the input from the BUSY generation circuit etc. to the flip-flop circuit, and D is the input to the flip-flop circuit.
The outputs sent from the BUSY generating circuit etc. to the external device via the flip-flop circuit, and P indicate the inspection points, respectively.

In this embodiment as well, even if the input C to the flip-flop circuit changes at the test point P, the output D does not change, so malfunction of the parity check is prevented as in the previous embodiment.

(7) Effects of the Invention As explained above in detail, the magnetic bubble memory control method of the present invention makes it possible to prevent parity check malfunctions by outputting the read data of the interface register in synchronization with the external device. This has a great effect in that it contributes to improving the reliability of magnetic bubble memory devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the conventional magnetic bubble memory control method, FIG. 2 is a time chart thereof, FIG. 3 is a diagram for explaining the magnetic bubble memory control method according to the present invention, and FIG. 4 is a diagram for explaining the magnetic bubble memory control method according to the present invention. FIG. 5 is a diagram for explaining another embodiment of the magnetic bubble memory control method according to the present invention, and FIG. 6 is a time chart thereof. In the drawing, 11 is a BUSY generation circuit, 12
is the RDA generation circuit, 13 is the TDRA generation circuit, 14
15 to 18 are flip-flop circuits; 19 is a check bit generation circuit; 20 is a bubble memory controller; 21 is an external device;
2 indicates a parity check circuit, respectively.

Claims (1)

[Claims] 1. In a magnetic bubble memory control device equipped with an interface register with an external device, a flip-flop circuit activated by a read signal from the external device is inserted on the output side of the interface register, and the read data of the interface register is read. A magnetic bubble memory control method characterized by outputting data in synchronization with an external device so that data does not change during reading.