JPS6320049B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a system for digitally processing analog signals that inherently do not contain DC components, such as AM modulated waves.

In recent years, with advances in digital signal processing technology,
Facsimile modulation/demodulation sections, data modems, etc., which were conventionally constructed with analog circuits, have now been constructed with digital circuits. In this case, an A/D converter is required between the digital processing circuit section and the line connection section of the transmission line such as a telephone line, but when processing signals that do not originally contain DC components, such as AM modulated waves, , a DC offset in an A/D converter causes various problems. Therefore, usually A/
Bias adjustment is performed on the input side of the D converter.

For example, taking a facsimile receiver as an example, its circuit block is normally constructed as shown in FIG. The input signal x(t) is, for example, an analog signal of the AGC circuit output, which is input to the sample and hold circuit 1 via the bias circuit 1 composed of a capacitor C and resistors R ₁ and R ₂ , and its output is input to the A/C circuit. It is converted into, for example, an 8-bit digital signal by the D converter 3, and this is converted into a parallel-to-serial conversion circuit 4.
The signal is converted into a serial signal and input to the digital arithmetic unit 5. Parallel-serial conversion circuit 4
is provided because normal digital signal processing is performed by serial calculation.

Now, in the case of AM/DSB modulation, the input signal x(t) in FIG. 1 becomes x(t)=A(t)cos(ωt+θ). If there is a deviation in the bias adjustment of the A/D converter 3, the output of the A/D converter 3 y(nT)
is expressed as y(nT)=A(nT)cos(ω _c nT+θ)+ε, which results in a DC offset ε. If carrier extraction is ideally performed on this output y(nT), then the synchronous detection output ω(nT)
is ω(nT)=y(nT)cos( _ωcnT +θ)=1/2A(t)+εcos( _ωcnT +θ)+1/2A(t)cos( _2ωcnT +θ). This spectrum diagram is as shown in Figure 2a, with a component remaining at the angular frequency _ωc . This is passed through a low-pass filter with characteristics as shown in Figure 2b to obtain a baseband signal as shown in Figure 2c, but the ω _c component remains here as well, and this becomes noise, even if it is a facsimile. Otherwise, it may cause deterioration of image quality. Up to this point, it has been assumed that carrier extraction is performed ideally, but if there is a DC offset in A/D converter 3, it naturally affects carrier extraction.

In order to avoid these inconveniences, a bias circuit 1 is provided as shown in FIG. 1, so that when the input voltage of the A/D converter 3 is 0V, the output sign is
...0". However, in such a conventional method,
The operation of finely adjusting the resistors R ₁ and R ₂ of the bias circuit 1 to remove DC offsets caused by manufacturing variations in the A/D converter 3 itself or unbalance in the power supply voltage is extremely troublesome, and also due to fluctuations in the power supply voltage. It is difficult to completely eliminate DC offset caused by temperature fluctuations.

In view of the above points, the present invention provides a digital processing system that eliminates the above-mentioned disadvantages by removing the DC offset without requiring fine bias adjustment on the input side of the A/D converter. It is.

In digitally processing an analog signal that originally does not contain a DC component, such as an AM modulated wave, through an A/D converter, the output of the A/D converter is filtered by a digital low-frequency filter. The main feature of the present invention is to provide means for removing the DC offset through the filter and limiting the input amplitude of the low-pass filter so as not to exceed the normal operating range of the filter. In the first invention, the means for limiting the amplitude includes means for detecting a code of a predetermined bit from the output of the A/D converter, and the detection result is provided on the output side of the A/D converter. and means for converting an output code whose amplitude exceeds a set value into a code corresponding to the set value. In the second invention, an analog amplitude limiter is provided on the input side of the A/D converter as means for limiting the amplitude.

Before explaining the embodiments of this invention, we will first explain the A/D
The effects and problems of providing a digital low-frequency cutoff filter on the output side of the converter will be explained.

FIG. 3 shows the facsimile receiving device shown in FIG. 1, in which the output signal of the A/D converter 3 is converted into a serial signal by a parallel-to-serial converter circuit 4, and then passed through a digital low-frequency cutoff filter 6 to convert it into a DC signal. The offset is removed and the signal is led to the digital calculation section 5. The output voltage of the bias circuit 1 is adjusted by a capacitor C and resistors R ₁ and R ₂ so that it is near the center of the dynamic range of the A/D converter 3 when the input signal x(t) is 0V. This adjustment may be very rough and does not require fine adjustment as in the conventional case. Therefore, if the center of the dynamic range of the A/D converter 3 is originally around 0V, the bias circuit 1 is not necessary.

It is assumed that the digital low-pass filter 6 is, for example, a digital high-pass filter and has the following transfer function H(Z).

H(Z)=(1-Z ^-1 )/(1-aZ ^-1 ) Here, 1>a>0. The DC gain of this filter is 0, and the passband gain is 2/1
+a. The closer a is to 1, the sharper the filter characteristics become, and the closer the passband gain approaches 1.

An example of the configuration of such a high-pass filter is shown in FIG. An adder 11 adds the input signal and the output of the one-sample delay memory 12 to obtain an output signal.
13 is a multiplier that multiplies the output signal by a constant a; a subtracter 14 subtracts the input signal from the output of the multiplier 13; the output is sent to the delay memory 12 by a correction circuit 15 according to the word length of the delay memory 12; It is now possible to input .

As mentioned above, it is better for the constant a to be close to 1,
Moreover, if that value is selected, the multiplier 13 can be omitted. For example, if the signal is a serial signal starting from the LSB in two's complement representation, by selecting a = 1-2 ^-i (i: a positive integer), an i-bit shift register is used instead of the multiplier 13. Adders can be used.

FIG. 5 shows the frequency characteristics of the digital high-pass filter constructed as described above.

In this way, the operation and problems when a low-pass filter 6, such as a high-pass filter as shown in FIG. 4, is provided on the output side of the A/D converter 3 are concretely shown in FIG. This will be explained next using FIG. 6 shows the input signal Y and output signal _Y0 for the step signal of the high-pass filter shown in FIG. In addition,
The full scale of the A/D converter 3 and the high-pass filter is assumed to be ±1. Now, as in the case of a,
Input signal Y is within full scale and +δ
If a DC offset is included, the high-pass filter stores -δ in the one-sample delay memory 12, thereby obtaining an output signal _Y0 from which the DC offset has been removed.

Incidentally, even if the input signal Y has no transmission distortion, there is an overshoot at the rise of a step, and this overshoot increases as the delay distortion of the transmission path increases. FIG. 6b shows such an input signal Y
This figure shows the case where the current includes a DC offset of +δ. In this case, the output signal Y ₀ has small waveform distortion in the positive half cycle due to the saturation function of the A/D converter 3, but in the negative half cycle, the waveform distortion is extreme due to the overflow of the 1-sample delay memory 12 as shown in the figure. This may occur. Similar waveform distortion can occur in the positive half cycle for negative DC offsets.

Such waveform distortion can occur even when the noise in the transmission path is large, and causes a significant deterioration in the quality of the received image.

Therefore, in this invention, a digital low-frequency filter is provided on the output side of the A/D converter to remove the DC offset, and the amplitude of the input or output of the A/D converter is limited, thereby achieving the above-mentioned effect. solving the problem.

An embodiment of this invention will be explained with reference to FIG.
FIG. 7 specifically shows an embodiment in which an amplitude limiting means is added to the parallel-to-serial converter circuit 4 in FIG. 3. Now, the A/D converter 3 outputs an 8-bit pure binary code, and its full scale is ±1.
Assume that the complement operation is performed. The amplitude setting value ±V _L by the amplitude limiting means is determined by the aforementioned DC offset amount δ and the gain of the low-pass filter 6, and here V _L =0.875.

In FIG. 7, the parallel-to-serial conversion circuit 4 is constructed by cascading seven cells 41 to 47. Cell 41 is a 2-input AND gate 411,4
12 and an OR gate 413 which receives these outputs as inputs, and a 1-bit shift register 414 which receives the selector output as input. Cell 42,4
3 has the same configuration as the cell 41. The cell 44 includes a 2-input AND gate 441, a 3-input AND gate 442 for amplitude limiting, and a 3-input AND gate 443,
A 3-input, 1-output selector consisting of an OR gate 444 that receives these outputs as input, and a 1-bit shift register 445 that receives this selector output as input.
It is composed of. Cells 45-47 are cell 4
It has the same configuration as 4. An A/D converter 3 input from terminals P ₀ to _{P 7} to each cell with such a configuration.
parallel output signal, serial signal from previous cell, shift/load control signal S/L (load with logic 1,
0) and the control signal GL from the code detection circuit 7 are input as shown.

The code detection circuit 7 includes a 4-input AND gate 7
1, a NOR gate 72, a NOR gate 73 which receives the outputs of these gates as input, and an inverter 74 which inverts the output of this NOR gate. The four inputs of the AND gate 71 and the NOR gate 72 of the code detection circuit 7 are the upper four bits of the A/D converter output supplied from the terminals _P0 to _P3 . Further, the output of the NOR gate 73 and a signal obtained by inverting this by the inverter 74 are input to AND gates 443 and 442 of cells 44 to 47, respectively.

The output of the parallel-serial conversion circuit 4 is connected to the terminal S ₀ of the cell 47.
The signal is taken out from the filter and input to the low frequency filter 6.

FIG. 8 is a timing chart showing the amplitude limiting operation according to the configuration shown in FIG. A/D converter 3
is the control signal A/D START at the required timing.
Assume that the conversion is started by , and the data is output sequentially starting from the MSB. Now the top 4 bits are “1 (MSB), 1,
1, 1", at that point the output of the AND gate 71 of the code detection circuit 7 becomes "1", that is, the control signal GL becomes "1", and the parallel The input AND gate 443 is disabled and these cells 44-47
In this case, the signal from terminal P ₀ is inverted by an inverter.
MSB is input. Then, during the period when the control signal S/L is “ ₀ ”, “0 (LSB), 0, 0,
0, 1, 1, 1, 0 (MSB)" are output sequentially,
The amplitude value will be limited to 0.875. Similarly, if the upper 4 bits become "0 (MSB), 0, 0, 0", the NOR gate 7 of the code detection circuit 7
2 becomes "1", and the parallel-to-serial conversion circuit 4 outputs "1 (LSB), 1, 1, 1, 0, 0, 0, 1".
(MSB)" are output sequentially, and the amplitude value is limited to -0.875 (strictly speaking, 2 ^-7 smaller than this). A/
When the D converter output is within the range of ±0.875, the control signal GL from the code detection circuit 7 becomes "0",
The amplitude limiting AND gates 442 in the cells 44 to 47 of the parallel-to-serial conversion circuit 4 are prohibited.

In this way, the amplitude of the input signal to the low-pass filter 6 is limited by ±V _L , and the waveforms of the input signal Y and output signal _Y0 become as shown in FIG.
Even if there is a large overshoot due to delay distortion in the transmission path, by removing the DC offset δ, large waveform distortion will not occur. Of course, this effect also applies to noise on the transmission path.

According to this embodiment, even if the steady input amplitude is increased from the viewpoint of effective use of the dynamic range of the A/D converter, the low-frequency distortion caused by DC offset and transmission line distortion is overflow can be prevented. In other words, while effectively utilizing the dynamic range of the A/D converter,
In addition to removing the DC offset, waveform distortion accompanying the removal of the DC offset can be significantly reduced.

In the above embodiment, the outputs of the A/D converters are parallel,
Although most commonly applied to systems in which a subsequent digital low-pass filter performs serial operations, the invention is applicable to other systems as well.

FIG. 10 shows an embodiment in which the present invention is applied to a system in which the output of an A/D converter is a parallel output, and a subsequent digital low-pass filter performs parallel operations. P ₀ , P ₁ , ..., P ₇ are input terminals for inputting each parallel output of the A/D converter, Q ₀ , Q ₁ , ...,
Q ₇ is an output terminal that outputs each parallel input to the following digital low-frequency cutoff filter;
84) is an amplitude limiting code conversion circuit, and 7 is a code detection circuit similar to the previous embodiment. As in the previous embodiment, the A/D converter outputs an 8-bit pure binary code with a full scale of ±1, and after the low-frequency cutoff filter performs two's complement arithmetic, which is set by the code conversion circuit 8. The value V _L is assumed to be 0.875. The code conversion circuits ₈₁ to ₈₄ have the same configuration. For example, the code conversion circuit 81 inputs a signal from the terminal _P4 and a control signal, an AND gate 811, and a signal obtained by inverting the signal from the terminal _P0 and a control signal GL. It consists of an AND gate 812 as an input, and an OR gate 813 as an input with the outputs of these gates. It can be said that these code conversion circuits 8 are provided independently with the selector portions incorporated in the cells 44 to 47 of the parallel-to-serial conversion circuit in the previous embodiment for amplitude limitation.

Therefore, in this embodiment as well, the output of the A/D converter is limited to a range of ±0.875 using the same logic as in the previous embodiment, and the subsequent low frequency signal is output from terminals Q ₀ to _{Q 7} at the required timing. It will be supplied to the cutoff filter in parallel.

FIG. 11 shows yet another embodiment, in which the amplitude of the A/D converter output is limited in a system in which the output of the A/D converter is serial, and a subsequent digital low-pass filter performs serial calculations. be. P is A/D
This is an input terminal for inputting the converter output, and the signal input here is assumed to be a two's complement code starting from 2's complement, full scale ±1. Q is an output terminal for outputting a signal to a subsequent low frequency shear filter, and after the low frequency shear filter, two's complement arithmetic is performed.
9 is a code detection circuit, 10 is a code conversion circuit, and shows the case where the amplitude limit value V _L =0.875.
91 is a 3-bit shift register into which the output of the A/D converter is input, and its parallel output and A/D
The output from the converter is input to an AND gate 92 and an OR gate 93, and the outputs of these gates are input to an OR gate 94. The signal from shift register 91 is inverted and input to AND gate 92 and OR gate 93. AND GATE 95, 96, OR GATE 97,
A 1-bit shift register 98 constitutes a circuit that holds the output of the OR gate 94 for a required bit length at a required timing using control signals C ₁ and C ₂ . For example, if the A/D converter output is n bits, _C1 is the control signal for the timing at which the 4th bit is output, and _C2 is the control signal for the timing at which the 4th bit is output.
4) Use as a bit length timing control signal. In this way, the output of the shift register 98 becomes the control signal GL from the code detection circuit 9.

The code conversion circuit 10 is an AND gate 101,1
02, OR gate 10 that takes these outputs as input
3. It consists of a hold circuit consisting of a 1-bit shift register 104 whose output is input, and a 2-input, 1-output selector consisting of AND gates 105, 106 and an OR gate 107 whose output is input. The above hold circuit is
The signal of the A/D converter is held for the required bit length (minimum (n-1) bit length) according to the control signal _C4 at the required one-bit timing according to the control signal _C3 .

With this configuration, for example, when the upper 4 bits of the A/D converter output become "0(), 1, 1, 1" or "1(), 0, 0, 0", what happens to the subsequent bits? Regardless, the control signal GL is “1”
In the code conversion circuit 10, the fifth and subsequent bits (n-4) output "0" or "1" determined by the output GN of the shift register 104 to the terminal Q. As a result, the amplitude of the A/D converter output is limited to ±0.875, and if necessary, it is converted into a serial signal starting from the LSB and supplied to the low-pass filter.

Fig. 12 differs from the previous embodiments in that the A/D
This is an embodiment in which amplitude limitation is performed on the input side of the converter. That is, in the configuration shown in FIG. 3, an analog amplitude limiter 11 consisting of diodes D 1 and D ₂ is placed between the bias circuit ₁ and the sample and hold circuit 2.
It has been established. Of course, the magnitude of the power supply voltage ±V _L applied to the amplitude limiter 11 needs to be selected within the dynamic range of the A/D converter 3, so that the same effect as in the previous embodiment can be obtained. .

Although several embodiments have been described, the present invention can also be applied to a system in which the output of an A/D converter is a serial signal starting from the LSB, and can also be used as a digital low-frequency cutoff filter. If the upper limit of the spectrum is determined, a bandpass filter can be used, and various other modifications can be implemented.

As explained above, according to the present invention, A/
By passing the output of the D converter through a digital low-pass filter to remove the DC offset,
For example, in a system in which a facsimile receiver or the like is digitized, the generation of noise due to the DC offset of an A/D converter can be reliably prevented, and carrier extraction can also be performed correctly. Moreover, according to this invention, there is no need for troublesome bias fine adjustment on the input side of the A/D converter, the bias circuit can be omitted, and DC offset due to power supply fluctuations and temperature fluctuations can be automatically compensated for. Can be removed. Furthermore, in the present invention, by providing a means for limiting the input amplitude of the low-pass filter so as not to exceed the operating range of the filter, significant waveform distortion caused by providing the low-frequency filter is reduced. This prevents the occurrence of That is, it is possible to remove the DC offset while effectively utilizing the dynamic range of the A/D converter, and to significantly reduce the waveform distortion that accompanies the removal of the DC offset.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the DC offset removal method in a conventional facsimile receiver, Figure 2 is a spectrum diagram to explain the problem when DC offset cannot be completely removed, and Figure 3 is a diagram showing the digital version of Figure 1. Figure 4 showing an example of adding a low-frequency cutoff filter.
The figure shows a specific example of a digital low-frequency cutoff filter, Figure 5 shows the filter characteristics, and Figure 6
This figure is a diagram for explaining the problem of waveform distortion in the configuration shown in FIG. 4, and FIG. 7 shows an embodiment of the present invention in which an amplitude limiting means is added to the parallel-to-serial conversion circuit in the configuration shown in FIG. 4. Figure 8 is a diagram showing the main part configuration, Figure 8 is its operation timing chart, Figure 9 is its amplitude limiting operation waveform diagram, and Figure 10 is a system in which the A/D converter outputs are parallel and they are processed in parallel. FIG. 11 is a diagram showing an amplitude limiting means in an embodiment to which the invention is applied; FIG. FIG. 12 is a diagram showing an embodiment of the present invention in which amplitude limiting means is provided on the input side of the A/D converter. DESCRIPTION OF SYMBOLS 1... Bias circuit, 2... Sample hold circuit, 3... A/D converter, 4... Parallel-to-serial conversion circuit, 5... Digital calculation unit, 6... Low frequency cutoff filter, 7, 9...Code detection circuit, 8,1
0... Code conversion circuit, 11... Analog amplitude limiter.

Claims (1)

[Scope of Claims] 1. A system for digitally processing an analog signal via an A/D converter, comprising: a digital low-pass filter that removes a DC offset from the output of the A/D converter; and means for limiting the input amplitude to the A/D filter so as not to exceed the normal operating range of the filter.
means for detecting a predetermined bit code of the output of the A/D converter, provided on the output side of the converter;
A digital processing system comprising means for converting an output code whose amplitude exceeds a set value into a code corresponding to the set value in accordance with the detection result. 2. In a system in which an analog signal is digitally processed via an A/D converter, a digital low frequency shear filter that removes a DC offset from the output of the A/D converter, and a digital low frequency shear filter that removes a DC offset from the output of the A/D converter; means for limiting the input amplitude of the filter so as not to exceed the normal operating range of the filter, and an analog amplitude limiter is provided on the input side of the A/D converter as the means for limiting the input amplitude. A distinctive digital processing system.