JPS63215969A - speed detection device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device that detects speed using a pulse generator in speed control, single position control, etc. of an electric motor.

[Conventional technology]

Conventionally, in a motor speed detection device using a pulse generator, a two-phase pulse generator having a phase difference of 90 degrees is used in order to simultaneously detect the rotation direction. In order to improve noise resistance, such speed detection devices are equipped with a filter for the two-phase pulse input waveform, or are equipped with a differential output type pulse generator that combines each two-phase pulse with an inverted pulse. is adopted. However, the former requires optimization of the filter depending on the output characteristics, transmission distance, transmission characteristics, etc. of the pulse generator, and the latter requires a special pulse generator.

FIG. 9 is a block diagram of a conventional example, in which 1 is a two-phase pulse generator, 2 people, 2B are A-phase and B-phase pulse waveform shaping circuits, 3 is a pulse delay circuit, 4 is a rotational direction detection circuit, and 5 is a clock generator.

FIG. 10 shows the waveforms of the signals at each part in FIG. 9. In this Figure 10, A and B are the output pulses of the pulse waveform shaping circuits 2 and 2B, respectively, ^1 is a pulse in the same phase as the A-phase pulse, and ^2 is a pulse delayed by one pulse from the A-phase pulse. Each represents a waveform. The rotation direction detection circuit 4 outputs a forward rotation pulse signal FP and a reverse rotation pulse signal RP depending on the state of the B phase when the A phase rises and falls, respectively.

Figures 5 and 6 show that during forward rotation (phase A leads phase B by 90 degrees) and reverse rotation (phase A lags phase B by 90 degrees), the two-phase pulse waveform is distorted due to noise, resulting in erroneous pulse output. (Signal indicated by broken line) Noise mode MODE 1 to MODE 6
shows.

FIG. 11 is a time chart when noise is applied in noise mode 1 of FIGS. 5 and 6, in which the reverse pulse signal RP is erroneously output due to the noise.

Figure 12 shows the noise mode MODB l -MODE 6.
It is a grudge transition diagram that includes
The forward rotation pulse signal FP disappears and MODE: 1-MO
DE 3 incorrectly outputs the reverse pulse signal RP, M when reversing
ODB 1~MDDE! In 2, an erroneous output of the reverse pulse signal RP and an erroneous output of FP and RP in the Iiguchi DB6 (this has no effect on the speed detection output signal by performing a difference in the counter processing in the subsequent stage), and the respective speed detection The error will be.

[Problem that the invention seeks to solve]

In this way, in the conventional example, when the human power pulse is distorted due to noise in each mode, this causes a speed detection error, and vector control of the motor no longer holds true, resulting in the problem that the output voltage does not increase or the speed does not increase. A dot had appeared.

The present invention has been made in view of these conventional problems, and an object of the present invention is to eliminate erroneous pulse output even when noise is mixed in, and to perform speed detection that is resistant to noise.

[Means for solving problems]

To achieve this objective, the speed detection device of the present invention comprises 9
Equipped with a rotation direction detection circuit that detects the rotation direction of the pulse output from a two-phase pulse generator that outputs pulses with a phase difference of 0 degrees based on the phase order of the two-phase pulse output, and outputs pulses for each rotation direction. In a speed detection device that detects the speed of a rotating body by counting these pulses with a counter, it is detected that the two-phase pulse outputs of the pulse generator become low level or high level at the same time, and the pulse signal at this time is detected. It is characterized by being equipped with a noise prevention circuit that stops the output of the noise.

[Effect]

In the present invention, erroneous pulse output and disappearance due to noise are eliminated by a noise prevention circuit composed of, for example, flip-flops and logic gates, and accurate speed detection is performed. This noise prevention circuit operates to eliminate erroneous pulse output or disappearance when the A phase and B phase are at the same level (low level or high level) at the same time. This results in
Erroneous pulse generation due to noise can be effectively prevented.

〔Example〕

Hereinafter, the present invention will be specifically explained based on Examples.

FIG. 1 shows an embodiment of the speed detection device of the present invention, which differs from the configuration shown in FIG. 9 in that a noise prevention circuit 6 is provided. Since the other configurations are the same as those in FIG. 9, the same reference numerals are given and the explanation will be omitted.

FIG. 2 shows an embodiment of the noise prevention circuit 6, which is composed of a flip-flop 7.8 and a NAND gate 9. Further, FIG. 3 shows an embodiment of another noise prevention circuit, in which a NOR gate 10 is used in place of the NAND gate 9 in FIG.

Referring to FIG. 1, an embodiment of the speed detection device of the present invention employing the noise prevention circuit of FIG. 2 will be described below.

FIG. 4 is a time chart during normal operation of the speed detection device according to the present invention, and shows 1. :B
X (B, and 82 (F) N A N D ) +7)
Depending on the state, a forward rotation pulse signal FP and a reverse rotation pulse signal RP are generated, respectively.

Here, B1 is a signal synchronized with the B phase by a clock, and B2 is a signal delayed by one clock from B1.

Figures 5 and 6 show normal rotation (A phase is 90 degrees faster than B phase), respectively.
0 degree lead), reverse rotation (A phase lags 8 phase by 90 degrees),
MODB1 to 1400 E6 are shown as noise modes in malfunction states (shaded areas) due to noise in two-phase pulse signals.

Noise mode 1 of the noise modes in Figures 5 and 6
A time chart when is applied is shown in FIG. FIG. 7 is a time chart when noise is applied in the noise mode 1 of FIGS. 5 and 6 in the present invention, and there is no erroneous pulse output due to noise.

In the conventional operation shown in FIG. 10, the reverse pulse signal RP is erroneously output under the same conditions.

Figure 8 shows the noise mode MODE 1 to Figure 6 of Figures 5 and 6.
It is a state transition diagram including MODE 6. In FIG. 8, the transition is clockwise during forward rotation, and counterclockwise during reverse rotation. Thin solid lines and broken lines indicate bypass circuits due to noise during forward rotation and reverse rotation, respectively.

Also, A(X,X) and B(X,X) are Al and A2. in FIG. 7, respectively. The logical states of B1 and B2 are shown. As an example,
This will be explained with reference to the time chart in FIG. Normally, moving clockwise from the initial state A(11)B(11),
The transition is from A(01)B(l l) to A(00)B(11).

When noise in noise mode 1 is applied to the initial state A(11)B(11), the state is as follows: A(01)B(01)→A(00)B(OO)
→ A(10) B(10) → A(11) B(11). Here, the forward rotation pulse FP and the reverse rotation pulse RP are:
A(10) B(00) and A(01) B(0
0), therefore, in the present invention, there is no erroneous pulse output for the noise mode MUDε1. In the state transition diagram of the conventional example shown in FIG. 12, the reverse pulse RP is erroneously output under the same conditions. As you can see from Figure 8, this is an erroneous pulse due to noise.

The disappearance is almost gone, and it is a noise mode during normal rotation! A
The only problems are the disappearance of the forward rotation pulse signal FP due to 00ε5 and the erroneous output of the forward rotation pulse signal FP due to the noise mode MO port ε6 during reverse rotation, which is a significant improvement.

The present invention is not limited to the embodiments, but is applied to a speed detection device with a noise prevention circuit that is configured with elements such as flip-flops and logic gates, and achieves the above effects.

〔Effect of the invention〕

As explained above, in the present invention, when the two-phase pulse outputs of the pulse generator become the same level (low level or high level) at the same time due to noise, the noise prevention circuit performs a logical operation and outputs an erroneous pulse. We are trying to prevent this.

This enables speed detection that is resistant to noise, and enables highly accurate speed control when applying vector control or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing an embodiment of the noise prevention circuit shown in FIG. 1, and FIG. 4 is a block diagram showing an embodiment of the noise prevention circuit shown in FIG. 2. FIG. 5 is a time chart when the circuit is implemented. Figure 6 is a waveform diagram showing waveform distortion due to noise in the two-phase pulse output of the pulse generator during forward rotation and reverse rotation, respectively;
FIG. 7 is a time chart when the noise mode 1 in FIG. 5 is applied, and FIG. 8 is a state transition diagram including the noise mode. Figure 9 is a block diagram of the conventional example, Figure 10 is its time chart, and Figure 11 is the noise mode M of Figures 5 and 6.
Time chart when applying noise of ODIli 1, 1st
FIG. 2 is a state transition diagram including the noise mode of the conventional example. 1: Two-phase pulse generator 2A, 28: Pulse waveform shaping circuit 3: Pulse delay circuit 4: Rotation direction detection circuit 5: Clock generator 6: Noise prevention circuit 7.8 = Flip-flop 9: NAND gate 10: NOR gate Patented Kojin Co., Ltd. Anyo Electric Manufacturing Co., Ltd. Representative
Masu Kobori (and 2 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure P Figure 7 CK Danze U 几 -1-- Figure 9 Figure 8 Figure 10 Figure 12

Claims (1)

[Claims] 1. A rotation direction detection circuit that detects the rotation direction of the pulse output from a two-phase pulse generator that outputs pulses with a phase difference of 90 degrees based on the phase order of the two-phase pulse output, and outputs pulses for each rotation direction. A speed detection device that detects the speed of a rotating body by counting these pulses with a counter detects that the two-phase pulse outputs of the pulse generator become low level or high level at the same time. A speed detection device characterized by being equipped with a noise prevention circuit that stops outputting a pulse signal.