JPS6321934B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control memory control method, and more particularly to a control method for a control memory device using a RAM element that can recover from an intermittent failure without affecting normal operation.

BACKGROUND ART Conventionally, a method of storing hardware control information (hereinafter referred to as a microprogram) in a control storage device has been used as a hardware control technique for a computer. This is a method of defining more macroscopic functions by programming instructions (milo instructions) that control functional units that make up subunits, gates, and timing within a computer.

Conventionally, as a memory element of a control memory device,
A ROM (read-only memory) element was used, but the memory element was rewritten to make it easier to deal with defects in micro programs, change micro programs due to specification changes, and convert software into firmware. The general trend in recent large-scale machines is to use available RAM elements.

In order to design a high-performance computer using microprogramming technology, a RAM with short access time and large capacity is required.
High speeds due to limited cooling capacity of the system
In the development of RAM, progress is being made in the direction of keeping the heat generation per chip almost constant, shortening RAM access time, and increasing the capacity per chip. In other words, the electrical energy required to hold one bit of information in a RAM element is becoming smaller, so intermittent failures are more likely to occur in high-speed RAM than in low-speed RAM. For example, bipolar RAM generally consists of flip-flop type static RAM;
The holding current in the RAM information holding state is 256
In a bit×1 RAM, it is about 90 μA per bit, whereas in a 1024 bit×1 RAM, it is about 30 μA per bit.

One cause of RAM failure is, for example, α-ray failure. Alpha ray damage refers to the loss of information stored in a RAM element when alpha rays emitted from the air or from the packaging material collide with the RAM element. For example, the amount of charge required to invert information in a flip-flop static RAM is approximately 0.1 pico coulomb.
However, when α rays (4.5 Mev) collide with a bipolar RAM element, a charge of approximately 0.2 pico-coulomb is generated on the silicon, which causes the stored information to be set to “0”.
to "1" or from "1" to "0".

In this case, what should be noted is that α-ray damage is
The RAM element is not destroyed, only the information is lost, so if you write the information again,
RAM can be used normally. In other words, α-ray damage corresponds to what is called an intermittent error, not a solid error. and,
This α-ray damage is more likely to occur as the electrical energy per bit of RAM becomes smaller.

Therefore, the faster the RAM, the
The reality is that the reliability of RAM deteriorates.

Traditionally, RAM used for control storage
Furthermore, if an intermittent failure such as an α-ray failure occurs, it becomes a major failure and the system goes down, significantly reducing the reliability of the computer system.

The purpose of the present invention is to eliminate the above-mentioned conventional problems by making it possible to recover the contents of a RAM element that has suffered from an intermittent failure such as an α-ray failure without affecting the normal operation of the computer. An object of the present invention is to provide a control storage control method.

The control storage control method of the present invention allows multiple data
It has a means for sequentially instructing the block numbers of a microprogram divided into blocks, and a clock register for measuring the elapsed time to guarantee the original processing time of the computer from the rewriting process of the specified block. During the standby time of the original processing, the microprogram of the designated block number is rewritten into the control storage device, and each time the rewriting is completed, a predetermined value is set in the clock register, and at least the The feature is that the next rewrite process is waited until a predetermined value of time has elapsed.

In the present invention, intermittent RAM failures such as α-ray failures do not mean that the RAM element itself has been destroyed, so rewriting information can
The RAM can operate normally, the address of the RAM element with the alpha fault is unknown and all information must be rewritten, and the information in the control storage will result in an immediate system failure if the fault occurs. Instead, we focused on the fact that system failures occur when the relevant information in the control storage device is used, and we repeatedly write control information to RAM using the computer's free time. That is, in the present invention, (a) the storage control device and its writing/writing are performed during the idle time of the computer, that is, the standby time of the arithmetic processing unit, without stopping the operation of the computer.
(the read control unit is in operation), rewriting the micro program to the control storage device;
(b) Since it is not possible to rewrite the entire microprogram within the waiting time of the arithmetic processing unit, it is necessary to divide the microprogram into multiple blocks and instruct the block number for rewriting for each waiting time. ) If the number of rewrites is repeated frequently, the original processing of the computer will be delayed and performance will deteriorate. Therefore, a time elapsed clock register is provided, and a predetermined value is set in this register every time the rewrite is completed. A new function has been added to make the next rewrite wait until that time has elapsed, in other words, to ensure that the rewrite time interval is longer than a certain period of time, so that the original processing of the computer is not delayed. There is.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, while comparing them with conventional ones.

FIG. 1 is an operational flow chart of a conventional computer, and FIG. 2 is an operational flow chart of a computer showing an embodiment of the present invention.

In a conventional computer, after starting as shown in FIG. 1, the program is executed at stage 52.
When there is no more work to be executed, a standby instruction is issued at stage 53, so the system enters a standby state at stage 54, and when an interrupt occurs at stage 55, the interrupt is processed at stage 56. In this way, the waiting state continues until an interrupt occurs and the next job is input. Interrupts include, for example, input/output interrupts and external interrupts.

In the present invention, the wasted time in the standby state is used to rewrite the microprogram in the control storage (CS).

In general, the amount of data in a microprogram is extremely large, so rewriting information to the control storage device in one go increases the write execution time, which delays the processing of interrupts that occur during that time, which can lead to performance degradation.

Therefore, in the present invention, the microprogram is divided into multiple data blocks, and
Rewriting is performed in units of these divided blocks.

In FIG. 2, stages 51 to 56 are a conventional operation flowchart, and the present invention inserts a stage 57 in which an arbitrary elapsed time is measured by a clock register during the standby state, and the rewriting condition is satisfied. When this happens, the program branches to a subroutine that rewrites the specified block.

This subroutine processes stages 58-63.

FIG. 3 is a block diagram of a control storage device and its control unit showing an embodiment of the present invention, and FIG. 4 is a record format diagram of data recorded on the external recording medium in FIG. 3.

In FIG. 3, the command control unit 1, the test circuit 104 for determining the address of the next microprogram to be executed, and the CS address register (CSAR) 101 from the CS write control unit 4 via the selection circuit 105. The address is set to . The microinstruction read from the control storage device 100 is set in the CG read data register (CSDR) 102, further decoded by the decode circuit 103, and control is performed according to the decoded contents.

As decode signals related to the present invention, decode signal 203 controls plus-one adder 400, decode signal 204 controls clock mechanism 500, and decode signal 202 sets CS rewrite request flip-flop 202. 301,3
02 is a control flip-flop.

A program status word (PSW) is set in the arithmetic unit 2, and the arithmetic unit 2 sends information to the test circuit 104 via the standby bit signal line 22, interrupt generation signal line 23, and arithmetic operations that can be tested by the microprogram. Various information lines 24 of the unit are connected. The external storage medium 3, such as a floppy disk, includes a control storage device 10.
The micro program to be loaded into 0 is stored. A maintenance diagnosis unit 5 is connected to the CS writing control unit 4.

Register 40 in adder 400 that performs plus one
1 is a register that holds the block number of the control storage device 100 to be written next, and the signal line 403 is set to “1” when the contents of the register 401 are N+1 or more.
A signal is supplied. A clock register 501 in a clock mechanism 500 used for a CPU timer, an interval timer, etc. is decremented every unit time, and when the content becomes "0" or less, a signal line 502
“1” is sent to In addition, the clock register 50
1 is set to an arbitrary value by the signal line 204. The clock register 501 stores a unit time, e.g.
Since it is subtracted every 3.3 mS, if the initial value is "303", it will become "0" or less after about 1 second, since 303 x 3.3 mS = 1 second.

As shown in FIG. 4, the external recording medium 3 in FIG. 3 stores the microprogram divided into N data blocks, and rewriting is performed in units of these divided blocks. Ru.

When dividing the data of a micro program into N pieces, it is necessary to consider the data amount of the program and the performance of the computer in determining "N".
For example, if the data amount of a micro program is 4K
If the time required to write one word into the control memory is 1 μS, then N=8. At this time, the time required to write one divided block of data is (4×10 ³ )/8×
1μS=0.5mS. In order to identify each block, a block number (1 to N) is stored at the beginning of each piece of data.

In FIG. 2, the computer enters a standby state at stage 54, and if no interrupt occurs, a microinstruction to execute stage 57 is stored.
The CS address is set in CS address register 101 and its contents are set in read data register 102. This microinstruction instructs to test a signal 502 indicating whether the contents of the clock register 501 are less than or equal to "0" at this time. The signal 502 is a signal that becomes "1" when the contents of the clock register 501 become "0" or less.

A signal 201 from the CS read data register 102 is control information for determining the CS address of the next microinstruction, and is sent to the CS address determination circuit 104.

FIG. 5 is a format diagram of the micro program in FIG.

For example, as shown in FIG. 5, the microinstruction at address X consists of a control field, a test condition, and a storage address for the next microinstruction, and the instruction to be executed next after the microinstruction at address If the test condition is satisfied, the microinstruction at address Y is executed, and if the test condition is not satisfied, the microinstruction at address (X+1) is executed.

The CS address determination circuit 104 determines the next CS address of the stage 57 when the signal 502 is “0”.
If so, return to stage 54 and signal 502 is “1”
If so, stage 58 is determined. Now, if the signal 502 is "0", the microinstruction at stage 54 is executed, and if no interrupt occurs at stage 55, the microinstruction at stage 57 is executed again. If there is an interrupt, stage 56
interrupt processing is executed. Stages 54 → 55 → 57 → 54 → 55 → 5 executed like this
7……or, 54→55→56→52→
The processing of 53→... is the same as the conventional processing flow.

However, the microinstruction in stage 57 causes the signal 5 to
If 02 is "1", the contents of the microinstruction at stage 58 are read from control storage 100 through test circuit 104 and set in register 102. When the contents of the register 102 are decoded by the decoder 103, the CS rewrite request trigger signal 202 becomes "1", the flip-flop 300 is set to "1", and the number indicated by the signal line 402 is sent through the set output line 303. The data block is written to control storage 100. Upon receiving the signal on the output line 303, the CS writing device 4 sends an acceptance completion signal to the signal line 44, and resets the flip-flop 300 to "0".

The flip-flop 301 is set to "1" when the flip-flop 300 at the previous stage becomes "1", and is reset when the completion report signal from the CS writing device 4 via the signal line 45 becomes "1". Flip-flop 302 is a delay flip-flop of flip-flop 301 in the previous stage. Flip-flop 301 is “1”
During this period, the contents of the read register 102 are invalid, so the contents are read from the decoder 10 via the signal line 304.
3 decoding operations are disabled. At the same time, the selection circuit 105 is fixed to the signal line 41 by the signal line 304. While the flip-flop 302 is “1”, the read register 1 is read through the signal line 305.
02 update is prohibited. At this point, the read register 102 has the stage 60 microinstruction set. Also, at this time, the block number of the data block to be rewritten into the control storage device 100 at stage 58 is set in the register 401 of the adder 400.

FIG. 6 is a time chart of the main flip-flop of FIG.

During one machine cycle _TM , the address set in the CS address register 101 is
Control store 100 is accessed and read register 102 is set with the stage 57 microinstruction. When the test conditions of stage 57 are satisfied, flip-flop 300 is set;
As a result, flip-flop 301 is set, and flip-flop 302 is further set. Setting flip-flop 302 inhibits updating of the contents of read register 102. Thereafter, when the flip-flop 301 is reset by the completion report 45 from the CS writing device 4, the CS address register 101 is reset.
The next address is set again.

In FIG. 3, the external recording medium 3 sends a CS address to a signal line 41, write data to a signal line 42, and a write instruction signal to a signal line 43 under the control of a CS writing device 4, and sends a write instruction signal to a signal line 402. Writes the data block indicated by to control storage 100. When data writing is completed, the completion report on the signal line 45 becomes "1" and the flip-flop 301 is reset. When the flip-flop 304 is reset to "0", "0" is sent to the signal line 304, so the decoder 103 becomes valid, and since the microinstruction of stage 60 is already set in the read register 102, This stage 60 is executed and the contents of the register 401 are incremented by one.

Next, stage 61 is executed and register 40
If the content of 1 is (N+1), the signal line 403 becomes "1" and is sent to the test circuit 104, stage 62 is executed, and the register 401 becomes "0".
is cleared, and the process moves to stage 63. If the signal line 403 is "0" at stage 61, the process moves to stage 63. At stage 63, the contents of clock register 501 are reset to an arbitrary fixed value. This is because there is a risk of deteriorating computer performance due to excessive micro program rewriting, so the micro program rewriting time interval is set to a certain period of time (for example, a fixed value of 303).
This is to guarantee at least 1 second).

Next, the process returns to stage 54 and the normal processing flow begins. Then, again at stage 57, the contents of clock register 501 are tested by the microprogram.

FIG. 7 is a detailed block diagram of the CS writing device in FIG. 3.

The CS writing device 4 performs both the initial writing of writing the microprogram to the control storage device 100 at power-on and the writing of the present invention in which the microprogram is rewritten to the control storage device 100 during the standby state.

Since the control storage device 100 is composed of RAM, its contents are not guaranteed when the power is turned on. Therefore, before using the computer, it is necessary to load the microprogram from the external recording medium 3 into the control storage device 100, and this operation is performed via the maintenance diagnosis device 5.

First, when the power is turned on, the maintenance/diagnosis device 5 shown in FIG. 7 initializes the address register 46 to the initial value "0" and the record number holding register 47 to "X" via the signal line 51. Note that block X stores all data of the microprogram. Next, the maintenance diagnosis device 5 activates the control circuit 49 via the signal line 52. The control circuit 49 sends a data read request to the external recording medium 3 via the signal line 410. The external recording medium 3 reads the data of the block "X" specified by the control circuit 49 word by word, and sets it in the register 48 via the data line 31. The control circuit 49 sets the CS address in the CS address register 101 via the address line 41,
At the same time as the write data is sent to the control storage device 100 via the data line 42, a write instruction signal is sent via the signal line 43, thereby completing the write of one word. When writing of one word is completed, address register 46 is incremented by one. Thereafter, by repeating this operation, writing of all data in block "X" is completed. Upon completion, address register 4
6 has become "0".

Next, when rewriting to the control storage device 100 according to the present invention, a block number is designated to the external recording device 3 via the signal line 402, and the block number is set in the record number holding register 47.
As a result, an instruction to read data from the external recording device 3 and write it to the control storage device 100 is issued via the signal line 303 instead of the signal line 52. The subsequent rewrite operation is the same as the write operation at power-on.

In this manner, the present invention rewrites the microprogram in the control storage device 100 by utilizing the waiting time when the computer has no more work to execute. The wait rate of the calculator is expressed as (waiting time)/(actual elapsed time).
This value varies depending on each job, and since there is normally a waiting time of several tens of milliseconds in one second, the value is several percent.

As explained below, according to the present invention, it is possible to periodically maintain information in the control storage device by utilizing idle time of the computer without degrading performance. system failures can be almost completely prevented, and system reliability can be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is an operation flow chart of a conventional computer, Fig. 2 is an operation flow chart of a computer showing an embodiment of the present invention, and Fig. 3 is a control storage device and its control unit showing an embodiment of the present invention. Block diagram, 4th
The figure is a record format diagram of data recorded on the external recording medium in Figure 3, Figure 5 is a format diagram of the micro program in Figure 3, and Figure 6 is a time chart of the main flip-flops in Figure 3. , 7th
The figure is a detailed block diagram of the CS writing device of FIG. 3. 1: Instruction control unit, 2: Arithmetic unit,
3: External recording medium, 4: CS writing device, 5:
Maintenance diagnosis device, 21: PSW (program status word),
46: Address register, 47: Record number holding register, 48: Register, 49: Control circuit, 100: Control storage device, 101: CS address register, 102: CS read register,
103: Decoder, 104: Test circuit, 10
5: selection circuit, 300-302: flip-flop, 400: adder, 401: register, 50
0: Clock mechanism, 501: Clock register.

Claims (1)

[Claims] 1. In an electronic computer that stores and controls microprograms in a rewritable control storage device, a means for sequentially indicating the block numbers of a microprogram divided into a plurality of data blocks, and a means for reproducing the instructed blocks. It has a clock register for measuring elapsed time to ensure the original processing time of the computer from the writing process, and stores the microprogram of the specified block number in the control storage device during the standby time of the original processing of the computer. , and each time the rewriting ends, a predetermined value is set in the clock register, and the next rewriting process is waited for at least until the predetermined value elapses. Memory control method.