JPS6322076B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a new configuration of a charge injection device (hereinafter abbreviated as CID) used for two-dimensional imaging. The present invention relates to a charge injection type solid-state imaging device having a pixel configuration that enables miniaturization, miniaturization, and low power consumption.

As shown in Figure 1, the CID is
A pixel 1 consisting of a pair of insulated electrodes 2X and 2Y to which voltages of about 10 V and 20 V are applied is two-dimensionally arranged on a semiconductor substrate covered with an insulating film.
The charges 4 in the semiconductor substrate generated from the optical excitation of the imaging light projected onto the light receiving surface 50 are first transferred to a potential well (hereinafter simply referred to as well) 3b directly under the electrode 2Y.
accumulated inside. Then, by controlling the voltage from the horizontal shift register 20, for example, Y ₁
If the well directly under the electrode 2Y connected to the bus bar is made to disappear at any time, the charge 4 will be transferred all at once to the well 3a directly under the electrode 2X, but the state at this time is as shown in the first column in FIG. It can be seen in the pixels of the eye. At the moment this charge 4 is transferred, an image charge is generated on the electrode 2X, and the image charge is
It is read out to the output terminal of the charge amplifier 7 via the busbar and electronic switches 11, 12, 13, and 14. Here, 10 is a vertical shift register, 9 is a reset switch that applies a voltage Vs to the electrode 2X of each pixel, and X ₁ to X ₄ and Y ₁ to Y ₄ represent an X bus group and a Y bus group, respectively.

When imaging of one frame of the CID is completed, the wells holding charges generated by the above-mentioned photoexcitation are made to disappear. In this way, the charges are injected into the substrate and disappear, so that in a new well created in preparation for the next frame of imaging, a significant amount of charge due to photoexcitation is accumulated again.

For this reason, hereinafter, the electrode 2Y will be referred to as a storage electrode, and the electrode 2X will be referred to as a detection electrode. And again, the CID shown in Figure 1
The light-receiving surface of is actually made integral with the vertical and horizontal generatrix lines as shown in FIG. For this purpose the busbar
Y ₁ to _{Y 4} will be called vertical bus lines, and bus lines X ₁ to _{X 4} will be called horizontal bus lines.

The CID pixel shown in Figure 1 above is actually constructed by first forming a thick insulating layer in the shaded area using the well-known LOCOS method, as shown in Figure 2, and then forming the active area surrounded by the dotted line. are the parts of the vertical generatrix R ₁ , R ₂
It is formed near the intersection of C ₁ and C ₂ of the horizontal generatrix. Part of the vertical bus bar R ₁ for specifying the address,
The horizontally spreading part of R ₂ and the part surrounded by the above dotted line covered by C ₁ and C ₂ of the horizontal generatrix where pixel charges are detected as image charges constitute one pixel. The photoelectric charge is transferred to the storage electrode 2Y in the pixel.
When accumulating directly below, some of the vertical busbars R ₁ and R ₂ are set to V
Parts of the horizontal bus bars C ₁ and C ₂ are biased to a voltage of V/2.

Now, if part _C1 of the horizontal bus bar is connected to the detection system and part _R1 of the vertical bus bar is set to zero voltage, the signal charge is transferred from directly under the storage electrode 2Y to directly under the detection electrode 2X, so that part of the vertical bus bar C1 is connected to the detection system. The pixel signal at the intersection of R ₁ and part C ₁ of the horizontal bus line is read out.

Such a system requires M vertical busbars and N horizontal busbars, M unit drive circuit stages, and N readout switches (corresponding to 11 to 14 in FIG. 1). Incidentally, the minimum size of the conventional CID is determined by the size per stage of each shift register in the vertical and horizontal directions, and power consumption is also controlled by the shift registers 10 and 20. This is because a minimum of six insulated gate transistors (hereinafter referred to as MOST) are required for each shift register stage, and these occupy a very large area on the same semiconductor substrate as the CID's light-receiving surface. It is. However, if the CID is to perform normal television scanning, the general odd-even switching of the horizontal busbars can be performed, so the number of stages of the vertical shift register can be halved. On the other hand, it is not possible to reduce the number of stages of horizontal shift registers, and as a result, the area occupied by the horizontal shift registers increases, which limits the ability to reduce power consumption. There were flaws.

The present invention has been made in view of these drawbacks, and involves forming pixel groups having mutually different impurity concentrations directly below the storage electrode, and switching the voltage applied to the storage electrode by the number of stages corresponding to the pixel group. The idea is to sequentially read out the charges of each pixel in the sensor from a common detection electrode to solve the above-mentioned problems, and will be described in detail with reference to FIG. 3 and subsequent drawings.

FIG. 3a is a diagram showing the main structure and operation of the novel CID according to the present invention, and similarly to FIG.
A thick insulating layer is formed by the LOCOS method on the diagonally shaded area outside of the unit pixel 51 surrounded by the dotted line to form the active region of the unit shown surrounded by the dotted line, that is, the pixels 21, 22, 23. and 24... are defined so that they are adjacent to each other. Of these, pixel 2
2 and 24 are not particularly processed, but the portion 21 directly below the storage electrode 2Y in pixels 21 and 23
a, 23a are doped with impurities by means such as implantation of boron B, as shown at 31 in FIGS. As shown by curve A in the figure, the voltage is shifted in the positive voltage direction to a value of _V2 . On the other hand, the threshold voltage Vt at the portions 22 and 24 is at the zero voltage V ₀ as shown by curve B in FIG. However, the vertical axis _φs in FIG. 4 is the surface potential of the p-type semiconductor substrate, and the horizontal axis V is the third
This is the voltage applied to the storage electrode 2Y shown in the cross-sectional view of the figure.

The charges generated by photoelectric conversion are transferred to pixels 21, 22,
To store data in 23 and 24, first keep the detection electrode 2X at a voltage of V ₁ as shown in Figure 4, and then turn the storage electrode 2Y on.
Keep the voltage at _V3 .

FIG. 3c shows the cross section from X to Y in FIG. 3a, and as a result of the above voltage application, the pixel 24
A fairly deep well 43a is located in the upper half part 24a.
However, a shallower well 43b is formed in the lower half portion 24b. In the upper half portion 21a of the pixel 21, there is a slightly deep well 41a.
In addition, a shallower well 4 is located in the lower half portion 21b.
It can be seen from FIG. 3c that 1b occurs respectively. However, in FIGS. 3a and 3b, 30 is an insulating layer for defining an active region, 31 is boron B ion-implanted for impurity doping, and 32 is an electrode 2.
The electrodes 2X and 2Y shown in FIG.
It is insulated by an insulating film (not shown) formed on X. Note that 40 is the aforementioned p-type semiconductor substrate.

Further, FIG. 3b shows a cross section from A to B in FIG. 3a, and since boron B is implanted directly under the upper half 23a of the pixel 23, a well 45 is formed directly under it. It has been shown that The deep well 43a in FIG. 3b is the same as the well 43a directly below the electrode 2Y shown in FIG. 3c.

In the following, when describing the operation of the main parts shown in Figure 3a, we will focus on Figure 3c, d, d, following Figure 3c, rather than Figure 3b.
Since e and f are easier to understand, we will follow them. Further, the explanation will be made using the time chart shown in FIG.

First, it is assumed that one horizontal row at the top of FIG. 3a is designated by the closing operation of an electronic switch similar to that shown in FIG. In this case, a well 41a is formed in the region 21a of the pixel 21 as shown in FIG. 3c, and at the same time, a well 43a as shown in FIG.
Wells having the same depth are formed, and charge q generated from photoelectric conversion is accumulated in each well.

Now, as shown in FIG. 5a, if the voltage V of the storage electrode 2Y to which the voltage V ₃ is applied is lowered from V ₃ to V ₂ (time t ₁ in FIG. 5), the threshold voltage V _t is
In the region directly under the electrode 2Y of the pixel 21, which is V ₂ , that is, in the upper half region 21a of the pixel 21, as shown in FIG.
The well 41a seen in FIG. 3 disappears as seen in FIG. 3d. As a result, the charge q in the well 41a directly under the storage electrode 2Y is transferred to the well in the region 21b in the lower half of the pixel 21, that is, in the region directly under the electrode 2X to which the voltage V ₁ is applied, as shown in FIG. 5b. 41
b. On the other hand, in the pixel 22, like the pixel 24, the region 22a is not doped with impurities such as implantation of boron B directly under the electrode 2Y, and therefore the region 22a has a threshold voltage V _t
Since there is no shift in the positive voltage direction, even if the voltage V of the storage electrode 2Y decreases from V ₃ to V ₂ as described above, the well directly under the region 22a does not disappear, but simply The depth only becomes shallower, and the charges q therein are not transferred to the well directly below the region 22b. In this case, the condition is exactly the same as that of wells 43a and 43 shown in FIG. 3d.
It will be drawn exactly the same as state b.

In this way, in the pixel 21, since the charge q moves from the region 21a directly under the storage electrode 2Y to the region 21b directly under the detection electrode 2X, an image charge is generated on the detection electrode 2X due to the charge q, and the fifth
As _shown in the period t ₁ to _{t 2} in FIG. The signal reading of only the pixel 21 is completed, and the pixel 22 remains in a so-called half-selected state.

However, the voltage of the storage electrode 2Y is changed from the value V ₂ to V ₀ ,
In other words, when it is further changed to zero (Fig. 5a)
At time t ₂ ), the well directly below the electrode 2Y in the pixel 22 also disappears. Here, since a well exists directly below the detection electrode 2X, the area 22 of the pixel 22
From a to the region 22b, the well 4 shown in FIG.
Transfer of charge q is performed in exactly the same manner as the transfer of charge q from well 3a to well 43b, and as a result, an image charge is generated on detection electrode 2X, as shown in period _t2 to _t3 in FIG. 5d. Thus, signal readout of the pixel 22 is completed. Then the period t ₃ to _{t 4} of FIG. 5 a and b
As shown, the significant electrode 2Y and the detection electrode 2X
Both voltages are V ₀ (0 volt), so Fig. 3 f
Charge q is injected into the substrate as shown by the arrow. This completes the processes of charge accumulation (period T ₁ ), readout (periods T ₂ , T ₃ ), and injection (period T ₄ ) of charges in pixels 21 and 22, but during this period, other pixels connected to bus line R ₁ do the same. However, since the electronic switch is not closed, there is no output to the charge amplifier.

Next, when the second closing operation of the electronic switch similar to that shown in FIG. 1 specifies the lower (second) horizontal row in FIG. The voltage applied to _C2 and the detection signal at that time are shown in Figures 5c and e. Therefore, if each horizontal row of the 3rd...nth row not shown in FIG. pixel signals are first read out, and then pixel signals not doped with impurities are read out. This means Y ₁ bus line in Figure 1 (in Figure 3
This means that all pixels in the first and second columns connected to R ₁ ) have been read out. Next, the horizontal register selects the _Y2 bus line, and similarly to the above, the vertical register sequentially selects pixels in the vertical direction to read out the pixels in the third and fourth columns, and similarly, the pixels in the m-1th column are read out. is read out, and the reading of all pixel signals for one frame is completed.

In order to sequentially read out the signals of two pixels by one selection designation of _one horizontal row, _the A stepwise switching voltage may be applied to the first and second values.

Furthermore, in the above embodiment, a structure was shown in which the signals of two pixels are sequentially read out by one selection designation of one horizontal row, but this is designed so that not only two pixels but three or four pixels can be sequentially read out. This may be done by increasing the number of pixels covered with 2Y and 2X electrodes that are connected in a strip shape in the horizontal direction. However, in this case, as described above, it is necessary to sequentially change the concentration of impurities doped into the semiconductor substrate surface of each pixel arranged in the horizontal direction, and to sequentially read out pixel signals, the number of stages corresponding to the number of pixels described above is required. It is necessary to apply a stepped voltage to the storage electrode 2Y.

As described above, by creating a structure in which multiple pixel signals are sequentially read out by specifying selection in one horizontal row, it becomes possible to read out multiple pixel signals arranged in one horizontal row with one stage of horizontal shift register. , the number of stages of the shift register can be reduced to that extent, and therefore the CID can be made smaller and the power consumption can be reduced, and great practical effects can be expected.

[Brief explanation of drawings]

Figure 1 is a schematic diagram showing the entire conventional CID, Figure 2
The figure shows the actual main part structure of a conventional CID, Figure 3 is a diagram for explaining the main part structure of the CID according to the present invention and its operation, and Figure 4 shows two lines arranged in the horizontal direction of the CID. FIG. 5 is a time chart for explaining the operation of the CID of the present invention. 21, 22, 23, 24: pixel, 30: insulating layer, 31: ion-implanted boron, 32: insulating film, 40: semiconductor substrate, 41a, 41b, 43
a, 43b, 45: well.

Claims (1)

[Claims] 1. In a charge injection type imaging device having a plurality of pixels defined by adjacent detection electrodes and storage electrodes, at least two adjacent pixels are considered as one group,
The storage electrodes and the detection electrodes of each pixel in the group are commonly connected to the vertical busbar and the horizontal busbar, respectively, and the impurity concentrations in the pixels directly under the commonly connected storage electrodes are made to be different from each other,
Applying a stepped voltage according to the impurity concentration to the storage electrodes of the commonly connected group of pixels,
A solid-state imaging device characterized in that charges of each pixel in the one group of pixels are sequentially read out from a common detection electrode.