JPS6322149B2 - - Google Patents
Info
- Publication number
- JPS6322149B2 JPS6322149B2 JP55132814A JP13281480A JPS6322149B2 JP S6322149 B2 JPS6322149 B2 JP S6322149B2 JP 55132814 A JP55132814 A JP 55132814A JP 13281480 A JP13281480 A JP 13281480A JP S6322149 B2 JPS6322149 B2 JP S6322149B2
- Authority
- JP
- Japan
- Prior art keywords
- effect transistor
- terminal
- circuit
- voltage
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
- H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
- H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Description
【発明の詳細な説明】
本発明は２端子化電界効果トランジスタ整流回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-terminal field effect transistor rectifier circuit.
従来、この種の回路は例えばＮチヤネル型絶縁
ゲート電界効果トランジスタ（以下MOSFETと
略記する）を整流素子として用い、第１図ｄに示
すように構成されていた。図において１０１は交
流電源、１０２はトランス、１０３は整流用
MOSFET、１０４は負荷である。交流電源１０
１からの交流電圧はトランス１０２によつて負荷
供給用電圧（端子１，２間）と整流用MOSFET
１０３の駆動用電圧（端子２，３間）とに分けら
れる。ここでトランスの出力電圧の極性は、端子
１を基準とした場合、端子２，３が同極性になる
ように結線しておく。したがつて、先ず端子１が
負、端子２が正の極性の半サイクルにおいては、
整流用MOSFET１０３のゲートＧに接続されて
いる端子３には正極性の電圧が発生し、整流用
MOSFET１０３のソースＳ、ドレインＤ間はオ
ン状態となり負荷１０４に電圧が印加される。逆
の半サイクルにおいては整流用MOSFET１０３
は、オフ状態となり、負荷１０４には電圧が印加
されない。以上の動作により整流用MOSFET１
０３のソースＳ、ドレインＤは、通常のダイオー
ドのアノードＡ、カソードＣと等価になり、整流
動作が可能となる。しかし、かかる回路において
は、整流用MOSFET１０３が３端子素子である
ためソースＳ、ゲートＧ間に、電圧を印加する特
殊なトランス１０２が必要となる。したがつて、
トランス１０２のヒステリシス損失が無視でき
ず、回路全体の効率に影響を及ぼす。トランスを
用いるため回路全体の体積が大きく、また重くな
る。整流できる周波数の上限はトランスの周波数
特性によつて決まり、高々数百ＫHz程度止まりと
なる等の欠点を有していた。 Conventionally, this type of circuit has been constructed as shown in FIG. 1d using, for example, an N-channel type insulated gate field effect transistor (hereinafter abbreviated as MOSFET) as a rectifying element. In the figure, 101 is an AC power supply, 102 is a transformer, and 103 is for rectification.
MOSFET 104 is a load. AC power supply 10
The AC voltage from 1 is connected to the load supply voltage (between terminals 1 and 2) by the transformer 102 and the rectifier MOSFET.
103 driving voltages (between terminals 2 and 3). Here, regarding the polarity of the output voltage of the transformer, when terminal 1 is used as a reference, terminals 2 and 3 are connected so that they have the same polarity. Therefore, in the first half cycle in which terminal 1 is negative and terminal 2 is positive,
A positive voltage is generated at the terminal 3 connected to the gate G of the rectifying MOSFET 103, and the rectifying MOSFET 103 is connected to the gate G.
The source S and drain D of the MOSFET 103 are turned on, and a voltage is applied to the load 104. In the opposite half cycle, the rectifier MOSFET103
is in an off state, and no voltage is applied to the load 104. By the above operation, rectifier MOSFET1
The source S and drain D of 03 are equivalent to the anode A and cathode C of a normal diode, and rectification operation is possible. However, in such a circuit, since the rectifying MOSFET 103 is a three-terminal element, a special transformer 102 for applying a voltage between the source S and the gate G is required. Therefore,
The hysteresis loss of the transformer 102 cannot be ignored and affects the efficiency of the entire circuit. Since a transformer is used, the overall volume of the circuit becomes large and heavy. The upper limit of the frequency that can be rectified is determined by the frequency characteristics of the transformer, and has drawbacks such as being limited to several hundred KHz at most.
また、第１図ｂは別の従来例であり、第１図ｃ
は第１図ｂに示した従来例の動作特性図である。
これらの図において、整流用MOSFET１１３は
しきい値電圧VT11を、MOSFET１１２はしきい
値電圧VT22をもつ。さらに、抵抗１１１と
MOSFET１１２は制御回路１１５を構成してい
る。このように構成されているため、端子Ａ−Ｃ
間の負荷電圧において整流用MOSFET１１３、
MOSFET１１２はオフとなり、電流は流れな
い。低い正電圧Ｖに対し、整流用MOSFET１１
３はそのしきい値電圧VT11において抵抗１１１お
よびゲート端子を経てオン状態となる。その結果
端子ＡおよびＣの間に電流が流れ始める。電圧Ｖ
の上昇により、電流もMOSFET１１２のゲート
端子における電位もしきい値電圧VT22に達し
MOSFET１１２がオン状態に至るまで上昇す
る。その結果、整流用MOSFET１１３のゲート
端子の電位は端子Ｃの電位とほぼ同じくなり、整
流用MOSFET１１３はオフ状態に移行する。こ
のため、端子ＡおよびＣ間の電圧Ｖが引続き上昇
する際に、これらの端子間の電流は再び減少し、
０となるものである。 Further, Fig. 1b is another conventional example, and Fig. 1c
is an operating characteristic diagram of the conventional example shown in FIG. 1b.
In these figures, the rectifying MOSFET 113 has a threshold voltage V T11 and the MOSFET 112 has a threshold voltage V T22 . Furthermore, the resistor 111
MOSFET 112 constitutes a control circuit 115. Because of this configuration, terminals A-C
Rectifying MOSFET 113 at a load voltage between
MOSFET 112 is turned off and no current flows. For low positive voltage V, rectifier MOSFET11
3 is turned on through the resistor 111 and the gate terminal at its threshold voltage V T11 . As a result, current begins to flow between terminals A and C. Voltage V
Due to the rise in , both the current and the potential at the gate terminal of MOSFET 112 reach the threshold voltage V T22 .
The voltage increases until MOSFET 112 turns on. As a result, the potential of the gate terminal of the rectifying MOSFET 113 becomes almost the same as the potential of the terminal C, and the rectifying MOSFET 113 shifts to the off state. Therefore, when the voltage V between terminals A and C continues to rise, the current between these terminals decreases again,
0.
しかし、この従来例においては、制御回路１１
５の電源として整流用MOSFET１１３が導通状
態（オン状態）時におけるソース・ドレイン間の
電圧（オン電圧VON）をそのまま使用するもので
ある。したがつて、第１図Ｃから明らかなよう
に、オン電圧VONはMOSFET１１２のしきい値
電圧VT22より大とする必要がある（VON≧VT22＞
０）ため、本整流回路における損失電力Ｉ×VON
は大きな値となる欠点がある。 However, in this conventional example, the control circuit 11
The source-drain voltage (ON voltage V ON ) when the rectifier MOSFET 113 is in a conductive state (ON state) is used as the power supply for the MOSFET 5. Therefore, as is clear from FIG. 1C, the on-voltage V ON needs to be higher than the threshold voltage V T22 of the MOSFET 112 (V ON ≧V T22 >
0), the loss power I×V ON in this rectifier circuit
has the disadvantage of being a large value.
本発明はこれらの欠点を解決するため提案され
たもので、電界効果トランジスタを用いた整流回
路を、トランスによる駆動方式を用いずに等価的
に２端子化することを目的とするものである。次
に本発明の実施例を、Ｎチヤネル型絶縁ゲート電
界効果トランジスタ（以下MOSFETと略記す
る）を整流素子として用いた例について説明す
る。 The present invention has been proposed to solve these drawbacks, and aims to equivalently convert a rectifier circuit using field effect transistors into two terminals without using a drive method using a transformer. Next, an embodiment of the present invention will be described using an N-channel type insulated gate field effect transistor (hereinafter abbreviated as MOSFET) as a rectifying element.
第２図は本発明の整流回路の一実施例であり、
２０１は交流電源、２０３は整流用MOSFET、
２０４は負荷、２０５は制御回路である。 FIG. 2 shows an embodiment of the rectifier circuit of the present invention,
201 is an AC power supply, 203 is a rectifier MOSFET,
204 is a load, and 205 is a control circuit.
交流電源２０１の出力端子１１は負荷２０４の
一方の端子に接続され、交流電源２０１の他の出
力端子１２は整流用MOSFET２０３のソース
Ｓ、ゲートG1に接続され、ドレインＤは負荷の
他方の端子に接続される。なお整流用MOSFET
２０３のソース端子ＳをアノードＡ、ドレイン端
子Ｄをカソードとする。２０５は整流用
MOSFET２０３の制御回路であつて、この制御
回路の一方の端子をアノードＡに、他の端子をカ
ソードＣに接続する。しかしてこの制御回路２０
５は次のように構成される。Ｎチヤネル型
MOSFET２０６及びＰチヤネル型MOS２０７に
よつてインバータ回路を構成する。すなわち、
MOSFET２０６のソースＳ、ゲートG1は共にア
ノードＡに接続され、ドレインＤはMOSFET２
０７のソースＳに接続され、MOSFET２０７の
ゲートG1、ドレインＤは１つはコンデンサ２０
９を介してアノードＡに接続され、他はダイオー
ド２０８を介してカソードＣに接続され、整流用
MOSFET２０３のゲートG2は、MOSFET２０
６のドレインＤと、２０７のソースＳに接続さ
れ、MOSFET２０６と２０７のゲートG2は共に
カソードＣに接続される。 The output terminal 11 of the AC power supply 201 is connected to one terminal of the load 204, the other output terminal 12 of the AC power supply 201 is connected to the source S and gate G1 of the rectifier MOSFET 203, and the drain D is connected to the other terminal of the load. connected to. In addition, rectifier MOSFET
The source terminal S of 203 is an anode A, and the drain terminal D is a cathode. 205 is for rectification
This is a control circuit for the MOSFET 203, and one terminal of this control circuit is connected to the anode A, and the other terminal is connected to the cathode C. However, the lever control circuit 20
5 is constructed as follows. N channel type
The MOSFET 206 and the P-channel MOS 207 constitute an inverter circuit. That is,
The source S and gate G1 of MOSFET206 are both connected to anode A, and the drain D is connected to MOSFET206.
The gate G 1 and drain D of MOSFET 207 are connected to the source S of MOSFET 207, and one is connected to the capacitor 20.
9 is connected to the anode A, and the other is connected to the cathode C through the diode 208, for rectification.
The gate G 2 of MOSFET203 is MOSFET20
The gates G2 of MOSFETs 206 and 207 are both connected to the cathode C.
次に動作について説明する。 Next, the operation will be explained.
上記の回路において、先ずアノードに負、カソ
ードに正の電圧が印加される半サイクルを考え
る。アノード、カソード間の電圧はダイオード２
０８を通つてコンデンサ２０９に充電されると同
時にインバータ回路の電源電圧となる。同時にイ
ンバータのゲート入力電圧はカソード電圧と等し
くなり、Ｎチヤネル型MOSFET２０６はオン、
Ｐチヤネル型MOSFET２０７はオフの各状態と
なる。したがつて整流用MOSFET２０３のゲー
ト入力電圧はアノード電圧とほぼ等しくなり、整
流用MOSFET２０３はオフ状態となる。一方、
上記とは逆の半サイクルにおいてはアノードＡが
正、カソードＣが負極性となる。この場合、コン
デンサ２０９の電荷はダイオード２０８によつて
流出が阻止され、コンデンサ２０９の両端の電圧
はほぼ一定に保たれる。また、インバータ回路の
ゲート入力電圧はカソード電圧に等しいため負極
性となり、したがつてＮチヤネル型MOSFET２
０６はオフ、ＰチヤネルMOSFET２０７はオン
の各状態となる。このため整流用MOSFET２０
３のゲート電圧はコンデンサ２０９の両端の電圧
にほぼ等しくなり、整流用MOSFET２０３はオ
ン状態となり、負荷２０４に電圧が印加される。
以上の回路動作によりアノードＡ、カソードＣ間
は２端子の通常のダイオードと同じ整流動作を行
なうことになる。制御回路として第２図に示すよ
うな相補型MOSインバータ回路を使用すること
により制御回路で消費する電力は極めて少なくす
ることが可能であり、また、動作の高速化も容易
となる。 In the above circuit, first consider a half cycle in which a negative voltage is applied to the anode and a positive voltage is applied to the cathode. The voltage between the anode and cathode is diode 2
08, the capacitor 209 is charged, and at the same time becomes the power supply voltage of the inverter circuit. At the same time, the gate input voltage of the inverter becomes equal to the cathode voltage, and the N-channel MOSFET 206 is turned on.
The P-channel MOSFET 207 is in each off state. Therefore, the gate input voltage of the rectifier MOSFET 203 becomes approximately equal to the anode voltage, and the rectifier MOSFET 203 is turned off. on the other hand,
In a half cycle opposite to the above, the anode A has positive polarity and the cathode C has negative polarity. In this case, the charge in capacitor 209 is prevented from flowing out by diode 208, and the voltage across capacitor 209 is kept approximately constant. Furthermore, since the gate input voltage of the inverter circuit is equal to the cathode voltage, it has negative polarity, and therefore the N-channel MOSFET 2
06 is off, and the P-channel MOSFET 207 is on. For this reason, rectifier MOSFET20
The gate voltage of No. 3 becomes approximately equal to the voltage across the capacitor 209, the rectifier MOSFET 203 is turned on, and a voltage is applied to the load 204.
Through the above circuit operation, the rectification operation between the anode A and the cathode C is performed in the same way as a normal two-terminal diode. By using a complementary MOS inverter circuit as shown in FIG. 2 as the control circuit, the power consumed by the control circuit can be extremely reduced, and the operation speed can be easily increased.
第３図は本発明の他の実施例を示すものであ
り、３０１は交流電源、３０３は整流用
MOSFET、３０４は負荷、３０５は制御回路、
３０９は昇圧回路、３１０は位相調整回路であ
る。昇圧回路は例えばコツククロフト回路等の周
知の回路で容易に構成できるものである。第３図
のように構成することにより、交流電源３０１の
電圧が小さく、従つて整流用MOSFET３０３が
オフの状態において、アノードＡ、カソードＣ間
の電圧が小さい場合においても昇圧回路３０９に
より、その電圧は増幅され、従つて整流用
MOSFET３０３のゲート電圧も大きくなり整流
用MOSFETを確実に動作させることができる。
また位相調整回路３１０は制御回路３０５および
整流用MOSFET３０３の動作遅れ時間を補正
し、交流電源３０１と整流用MOSFET３０３の
オン、オフの位相差をなくし、整流動作の確実化
と、電流断続の過渡時の損失を少なくする効果を
もたせるために設けたものであり、本回路の採用
により数百ＫHz以上の高周波についても整流が可
能となる。なお上述の実施例の外に昇圧回路を制
御回路のインバータ出力端子と整流用MOSFET
のゲート端子間に設けることも可能であり、同様
に位相調整回路３１０についても制御回路のイン
バータ出力端子と整流用MOSFETのゲート端子
間に設けることも可能である。更に周知の技術に
より上記制御回路、昇圧回路、位相調整回路を整
流用MOSFETと一体化することも容易である。 FIG. 3 shows another embodiment of the present invention, where 301 is an AC power supply and 303 is a rectifier.
MOSFET, 304 is load, 305 is control circuit,
309 is a booster circuit, and 310 is a phase adjustment circuit. The booster circuit can be easily constructed using a known circuit such as a Kotscroft circuit. By configuring as shown in FIG. 3, even if the voltage between the anode A and the cathode C is small when the voltage of the AC power supply 301 is low and the rectifier MOSFET 303 is off, the booster circuit 309 can increase the voltage. is amplified and therefore for rectification
The gate voltage of MOSFET 303 also increases, allowing the rectifier MOSFET to operate reliably.
In addition, the phase adjustment circuit 310 corrects the operation delay time of the control circuit 305 and the rectifying MOSFET 303, eliminates the phase difference between on and off of the AC power supply 301 and the rectifying MOSFET 303, and ensures reliable rectifying operation and during transient periods of intermittent current. This circuit is designed to have the effect of reducing loss, and by adopting this circuit, it is possible to rectify even high frequencies of several hundred KHz or more. In addition to the above-mentioned embodiments, the booster circuit is connected to the inverter output terminal of the control circuit and the rectifier MOSFET.
Similarly, the phase adjustment circuit 310 can also be provided between the inverter output terminal of the control circuit and the gate terminal of the rectifying MOSFET. Furthermore, it is easy to integrate the control circuit, booster circuit, and phase adjustment circuit with a rectifier MOSFET using well-known techniques.
第４図も本発明の回路を集積化した場合の一実
施例である。４１１は内部に上述の整流用
MOSFETおよび制御回路等を有する整流主回路
であり４１２は大容量コンデンサ、４１３はアノ
ードＡ、ドレインＤ端子である。上記整流主回路
４１１を混成集積回路、あるいは半導体集積回路
等により構成し、集積化が困難である大容量コン
デンサを半田付けなどにより上記整流主回路４１
１に接続したものである。かかる構造となつてい
るため、電界効果トランジスタを用いた整流回路
は、最終的にダイオードのアノードＡ、カソード
Ｃに相当する２端子で構成されることになり、汎
用性があり、小型、軽量で、整流効率の高い２端
子化電界効果トランジスタ整流回路を実現するこ
とができる。 FIG. 4 also shows an embodiment in which the circuit of the present invention is integrated. 411 has the above-mentioned rectifier inside.
The rectifier main circuit includes a MOSFET, a control circuit, etc., 412 is a large capacitor, and 413 is an anode A and drain D terminal. The rectifier main circuit 411 is configured by a hybrid integrated circuit, a semiconductor integrated circuit, etc., and a large capacitor that is difficult to integrate is soldered to the rectifier main circuit 411.
It is connected to 1. Because of this structure, a rectifier circuit using field effect transistors will ultimately consist of two terminals corresponding to the anode A and cathode C of a diode, making it versatile, compact, and lightweight. , it is possible to realize a two-terminal field effect transistor rectifier circuit with high rectification efficiency.
以上説明したように、本発明によれば、オン抵
抗が低く、整流効率の高い電界効果トランジスタ
整流回路を容易に２端子化できる。したがつて、
従来、同期駆動用として用いて来たトランスが不
要となり、小型軽量化とともに使い易くなる利点
がある。さらに本発明によれば、従来のPN接合
ダイオードを用いていた回路に何らの改造を行な
うことなく代替でき、整流素子自体の損失の低減
化を容易に図れる利点がある。 As described above, according to the present invention, a field effect transistor rectifier circuit with low on-resistance and high rectification efficiency can be easily converted into two terminals. Therefore,
The transformer that has conventionally been used for synchronous drive is no longer required, which has the advantage of being smaller and lighter and easier to use. Further, according to the present invention, there is an advantage that a circuit using a conventional PN junction diode can be replaced without any modification, and the loss of the rectifying element itself can be easily reduced.
第１図ａ及びｂは従来の回路図、第１図ｃは第
１図ｂの回路の動作説明図、第２図、第３図は本
発明の実施例の回路図、第４図は本発明の実施例
の概念図である。
１０１，２０１，３０１……交流電源、１０２
……トランス、１０３，１１３，２０３，３０３
……整流用MOSFET、１０４，２０４，３０４
……負荷、１１１……抵抗、１１２……
MOSFET、１１５，２０５，３０５……制御回
路、２０６……Ｎチヤネル型MOSFET、２０７
……Ｐチヤネル型MOSFET、２０８……ダイオ
ード、２０９……コンデンサ、３０９……昇圧回
路、３１０……位相調整回路、４１１……整流主
回路、４１２……大容量コンデンサ、４１３……
アノードＡ、カソードＣ端子。
1A and 1B are conventional circuit diagrams, FIG. 1C is an explanatory diagram of the operation of the circuit in FIG. 1 is a conceptual diagram of an embodiment of the invention. 101, 201, 301... AC power supply, 102
...Trans, 103, 113, 203, 303
... Rectifier MOSFET, 104, 204, 304
...Load, 111...Resistance, 112...
MOSFET, 115, 205, 305... Control circuit, 206... N-channel MOSFET, 207
...P channel type MOSFET, 208 ... diode, 209 ... capacitor, 309 ... booster circuit, 310 ... phase adjustment circuit, 411 ... rectifier main circuit, 412 ... large capacity capacitor, 413 ...
Anode A, cathode C terminal.
Claims (1)
し、かつ前記の電界効果トランジスタの制御回路
を有する整流回路において、前記電界効果トラン
ジスタの電流阻止状態における該電界効果トラン
ジスタのソース、ドレイン間の電圧を前記制御回
路の電源電圧および同期駆動用電圧として使用
し、かつ前記制御回路の出力電圧を前記電界効果
トランジスタのゲート電圧とすることを特徴とす
る２端子化電界効果トランジスタ整流回路。 ２ ２端子化電界効果トランジスタ整流回路にお
いて、電界効果トランジスタのドレイン、ソース
電極端子と前記制御回路の電源電圧入力端子間、
あるいは該制御回路の出力端子と該電界効果トラ
ンジスタのゲート入力端子間の少なくとも一方に
昇圧回路を設けたことを特徴とする特許請求の範
囲第１項記載の２端子化電界効果トランジスタ整
流回路。 ３ ２端子化電界効果トランジスタ整流回路にお
いて、電界効果トランジスタのドレイン、ソース
端子と該制御回路の同期駆動電圧入力端子間、あ
るいは該制御回路の電圧出力端子と該電界効果ト
ランジスタのゲート端子間の少なくとも一方に、
位相調整回路を設けたことを特徴とする特許請求
の範囲第１項記載の２端子化電界効果トランジス
タ整流回路。[Scope of Claims] 1. In a rectifier circuit that uses a field effect transistor as a rectifying element and has a control circuit for the field effect transistor, the distance between the source and the drain of the field effect transistor in a current blocking state of the field effect transistor. A two-terminal field-effect transistor rectifier circuit, characterized in that the voltage is used as a power supply voltage and a synchronous drive voltage of the control circuit, and the output voltage of the control circuit is used as the gate voltage of the field-effect transistor. 2. In a two-terminal field effect transistor rectifier circuit, between the drain and source electrode terminals of the field effect transistor and the power supply voltage input terminal of the control circuit,
Alternatively, the two-terminal field effect transistor rectifier circuit according to claim 1, further comprising a step-up circuit provided at least on one side between the output terminal of the control circuit and the gate input terminal of the field effect transistor. 3. In a two-terminal field effect transistor rectifier circuit, at least between the drain or source terminal of the field effect transistor and the synchronous drive voltage input terminal of the control circuit, or between the voltage output terminal of the control circuit and the gate terminal of the field effect transistor. On the one hand,
2. A two-terminal field effect transistor rectifier circuit according to claim 1, further comprising a phase adjustment circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13281480A JPS5759475A (en) | 1980-09-26 | 1980-09-26 | Field effect transistor rectifying circuit with 2-terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13281480A JPS5759475A (en) | 1980-09-26 | 1980-09-26 | Field effect transistor rectifying circuit with 2-terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5759475A JPS5759475A (en) | 1982-04-09 |
| JPS6322149B2 true JPS6322149B2 (en) | 1988-05-10 |
Family
ID=15090191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13281480A Granted JPS5759475A (en) | 1980-09-26 | 1980-09-26 | Field effect transistor rectifying circuit with 2-terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5759475A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59112728U (en) * | 1983-01-19 | 1984-07-30 | 武内プレス工業株式会社 | Tape type open end |
| US5173849A (en) * | 1987-09-19 | 1992-12-22 | Magellan Corporation (Australia) Pty. Ltd. | Integratable synchronous rectifier |
| US5107227A (en) * | 1988-02-08 | 1992-04-21 | Magellan Corporation (Australia) Pty. Ltd. | Integratable phase-locked loop |
| DE19537920C2 (en) * | 1995-10-12 | 1999-08-19 | Temic Semiconductor Gmbh | Integrated circuit arrangement with diode characteristics |
| WO1997047071A1 (en) | 1996-06-05 | 1997-12-11 | Ntt Data Corporation | Electric circuit |
| JP3231003B2 (en) * | 1996-06-05 | 2001-11-19 | 株式会社エヌ・ティ・ティ・データ | electric circuit |
| US6421262B1 (en) * | 2000-02-08 | 2002-07-16 | Vlt Corporation | Active rectifier |
| US7030680B2 (en) * | 2003-02-26 | 2006-04-18 | Integrated Discrete Devices, Llc | On chip power supply |
| DE102015011718A1 (en) * | 2014-09-10 | 2016-03-10 | Infineon Technologies Ag | Rectifier device and arrangement of rectifiers |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2638086A1 (en) * | 1976-08-24 | 1978-03-02 | Siemens Ag | INTEGRATED POWER SUPPLY |
-
1980
- 1980-09-26 JP JP13281480A patent/JPS5759475A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5759475A (en) | 1982-04-09 |
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