JPS6322348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention is based on a logic circuit drawing in which logic symbols drawn along lattice axes are mixed with characters indicating connections between the symbols, symbol names, etc. The present invention relates to a system for automatically recognizing symbols in a drawing, and attempts to prevent symbols in the drawing from being extracted in an overlapping manner, and to separate symbol information from characters and connection information.

BACKGROUND OF THE TECHNOLOGY Conventionally, inputting logic circuit drawing information into a computer has been done manually using a card punching method or a digitizer, which is extremely time-consuming, monotonous, and painful work for the operator. Therefore, automatic input methods are being intensively developed, and the present inventors also proposed the "Line pattern automatic recognition method" (Japanese Patent Application No.
``Recognition method for line figures having circular shapes'' (Japanese Patent Application 1982-201465, JP 58-103074),
"Pattern matching method" (Patent application 1986-43954,
He has filed numerous applications, including JP-A-58-161088).

Prior art and problems By the way, in these methods, one symbol in a logical figure may be extracted as two or more recognition results, and some logical figures have characters added, but these are not symbols. and may be confused with part of the wiring information.

Purpose of the Invention The present invention uses a dictionary for "a code indicating line segment information compressed into lattice points" used to recognize logical symbols, and determines whether the lattice point code indicates pattern information of a logical symbol. By setting bit S, logical symbols and other graphical information such as characters are separated. Further, the bits are set only once and are not set again to avoid double selection of logical bits and erroneous recognition.

Structure of the Invention The present invention reads a logic circuit diagram in which characters and wiring are mixed in logic symbols drawn along a lattice axis using an input device, and uses the obtained video signal to indicate the direction of a line segment at each lattice point. A lattice point label code including a direction code is obtained, and the lattice point label code within the scanning window area is added to a dictionary created in advance (including a four-way code corresponding to the shape of a logical symbol and information on don't care bits for comparison). ), the lattice point label code is provided with an area for storing symbol area bits, and the lattice point label code is recognized by a comparison operation between the four-way code of the lattice point label code and a dictionary. logical symbol recognition result storage means for storing recognition results of the logical symbols read out, and logical symbol recognition information is sequentially read from the logical symbol recognition result storage means, and a dictionary corresponding to the read logical symbols is read out. symbol area bit detection means for detecting whether or not a symbol area bit of a lattice point label code corresponding to a line segment constituting a logical symbol has already been set; When it is determined that the logical symbol recognition result is present, a means for invalidating the recognition result of the logical symbol stored in the logical symbol recognition result storage means and currently being read out, and a means for invalidating the recognition result of the logical symbol that is currently being read out, and a means for determining whether the symbol area bit is unset by the symbol area bit detecting means. When it is determined that there is, the setting of the symbol area bit of the grid point label code corresponding to the line segment constituting the logical symbol that is currently being read is changed to the don't care setting of the dictionary that is currently being read that corresponds to the logical symbol. The present invention is characterized by comprising a symbol area bit setting means executed based on bits, and separating logical symbol information from character and wiring information.This will be explained below with reference to embodiments.

Embodiments of the invention Logic symbols appearing in logic circuit drawings have a second
As shown in the figure, there are a rectangular flip-flop a, a bowl-shaped NAND gate b and an exclusive-OR gate d, and a triangular inverter c. These have input/output lines, and are marked with O marks to indicate signal inversion, as necessary. These are handwritten along the predetermined lattice axes, that is, the vertical and/or horizontal lines of a lattice strip consisting of a large number of equally spaced parallel vertical and horizontal lines, and together with similarly handwritten characters, etc., they form a logic circuit. The video signal is then automatically recognized and input to a computer, but prior to that, it is read by a reading device such as a facsimile, and the information contained in the obtained video signal is used as a grid point to express the graphical structure near the grid point. Compress into label code. This process is performed using techniques such as the above-mentioned "automatic line pattern recognition method" and "recognition method for line figures with circles," but
The format of the resulting grid point label code is shown in FIG. Using the "line pattern automatic recognition method", the 0th bit, 3rd to 15th bit of the grid point label code
The bit information is set, the inverse logic symbol is recognized by the "recognition method for line figures with circles", and the second bit of the grid point label code indicates whether an inverse logic symbol exists at that grid point. Information about the presence or absence of the reverse logic symbol is set.

As shown, this code consists of 16 bits,
The 12th to 15th bits are a 4-way code, and the corresponding grid point (view it as a rectangular area by making the field of view a little larger)
This shows whether the line runs up, down, left, or UDLR. For example, if it starts from the grid point and extends to the right, R=1 and U, D, and L are set to 0. If it extends vertically, U and D are 1 and L and R are 0. The 8th to 11th bits indicate an ambiguous direction, with bit 1 indicating "like a character". This corresponds to a four-way code, and for example, R=1, but if it is determined from the line width that this is likely a line element constituting a character, F _R =1. The 7th bit is a shift flag. This flag F ₁ has a deviation,
The direction of the deviation is indicated by the third to sixth bits. Specifically, the line segments drawn along the vertical and horizontal lines (lattice axes) are not on the line correctly, so the upper
If it is shifted down, to the left, or to the right, F ₁ =1,
If it is shifted to the right, Z _R =1. This has the purpose of preventing double selection. In other words, the field of view is widened so that the line segment can be detected even if it shifts, so if it shifts to the right, the next grid point may appear to shift to the left (if it shifts to the center between the grid points) ), double selection will occur, but this is to prevent this. The second bit is a bit indicating the presence or absence of an inverse logic symbol, and if this bit is "1", it indicates the presence of the small circle or rotation mark shown in FIG. The first bit is a symbol area bit provided in the present invention, which will be described later. The 0th bit is an ambiguity flag, and if this bit _F2 is 1, the 8th to 11th bits are set to "1", specifically indicating that the grid point information is likely to be a character rather than a line segment.

The lattice label code is extracted from the entire video signal of the logic circuit diagram developed in memory, and the above-mentioned "pattern matching method" is applied to the result to generate logic symbols as shown in Figure 2. The logical symbol classification table shown in FIG. 3 is created. As shown in FIG. 4, i and j in FIG. 3 indicate the grid point coordinates of the representative point of the logic symbol (indicated by a * mark), and NO indicates the number of the logic symbol.
SDRCT also indicates the direction of the logical symbol. Here, the direction refers to the right direction as shown in Figure 4 a, the upward direction as shown in Figure 4 b, the left direction as shown in Figure 4 c, and the downward direction as shown in Figure 4 d (this is determined by the scanning direction), respectively.
SDRCT is 0, 1, 2, 3. Further, SNO is a column for storing the logical symbol recognition result (finally determined symbol name), but it is not used in the present invention. The last one is FLAG, but here it is all set to 0 (details will be explained later). 1 arranged vertically,
2, 3, . . . indicate the order of logical symbols extracted and stored in the classification table, and TOTAL is the number of logical symbols stored here. The present invention is applied from the stage when the logical symbol classification table shown in FIG. 3 is created.

The most basic codes for recognizing logical symbols are the aforementioned four-way codes D, L, U, and R.
Figure 5b graphically shows the four-way code for the logic symbol in figure a, where "•" indicates "0000", that is, no symbol pattern, and "" indicates 1001, that is, the left corner of the symbol. Logic symbols may have characters written as shown in Figure 6a, and in this case the four-way code will be as shown in Figure 6b.Graphic element E within the rectangular frame corresponds to the character A82FDD. (converted to grid point label code).Recognition of logical symbols is shown in Figure 5b.
This is done by preparing and comparing dictionary patterns with the same contents as , and giving the logical symbol name of the matching (smaller distance) dictionary pattern to the logical symbol. There are large and small handwritten logical symbols, but since they are written along the grid axis, the unit is the grid pitch, and large and small dictionary patterns are prepared according to the grid pitch. However, since the characters in logical symbols are not prepared in the dictionary, the degree of inconsistency is large for logical symbols such as the one shown in FIG. 6a.

In the above-mentioned "pattern matching method", a dictionary shown in FIG. 7, that is, a dictionary pattern that takes ambiguity into account, is used to deal with such logical symbols. This only shows what corresponds to column _P4 in FIG. 6b. In this column, as can be estimated from Figure 6a, there is no pattern in the first row, so the 4-way code is 0000, and in the second row there is a line segment extending left and right, so the 4-way code is 0101, and the 4-way code is 0101 from the 3rd row to the 11th row. There is no pattern up to the row 0000, the 12th row has line segments on the left, right and bottom, so 1101, and the 13th row has line segments on the top and bottom, so
1010, the above data group is stored in the standard code column SC of the dictionary in column _P4 of FIG. 7b, and in addition, a don't care code DC is prepared. This consists of 4 bits N ₁ - _{N 4} corresponding to DLUR. Also, prepare don't care bits N _T for the whole. The area inside the rectangular frame indicating the flip-flop is not necessary for symbol recognition, so this part, that is, the third
It is assumed that N _T =1 between rows to the 11th row, and even if any four-way code is extracted, it will be ignored.
The second line has a logical symbol line segment, so it is not ignored, but the characters written in the frame may be close to each other or touch each other, so set the _N1 bit of the don't care code DC to 1 and push it downward (4 D bit of the direction code) is ignored. Similarly the 12th
There is a logical symbol line segment in the line, so do not ignore it,
It is possible that the characters inside the frame will stick out upwards (the U bit of the 4-way code), so to deal with this, you can set the _N3 bit to 1, but it is normal to write the characters at the top or center of the frame. So, it is not written at the bottom, and here it is set as DC=0, that is, there is nothing to ignore. In this way, a dictionary is created according to the logical symbols to be recognized. 7th
Figure a shows the contents of Figure b in the form of marks.

Here, we will provide additional explanations regarding the creation of classification tables.

(a) Regarding the creation of a "classification table": Create and prepare symbol classification dictionaries corresponding to the logical symbols to be recognized and classified according to the number of logical symbols to be recognized and classified, according to the above idea. , the four-way code of the grid point label code extracted from the input drawing, the four-way code SC written in the symbol classification dictionary, and the don't care code.
Logical symbols are recognized, classified and created by similarity calculation between DC and don't care bit N _T.

The similarity calculation starts from the grid point in the upper left corner (address is 1, 1), and first, from the grid point position 1, 1 in the upper left corner, the symbol corresponding to the dictionary described in the symbol classification dictionary is calculated. size
4 of grid point label code of size MX, MY
Calculate the similarity with the direction code. If this degree of similarity is high, 1 and 1 are stored in the i and j columns of the symbol classification table shown in FIG. 3, and the logical symbol number corresponding to the dictionary is stored in the NO column. If the degree of similarity is low, a degree of similarity calculation is performed with the next dictionary (dictionary for another logical symbol). That is, for one grid point, matching with all logical symbol dictionaries is performed until one with a high degree of similarity appears. After completing the similarity calculation for grid point address 1, 1, move to the next grid point address 2, 1, perform similarity calculation, and if there is one with high similarity, perform symbol classification in the same way. Store the address and logical symbol number in the table. In this way, similarity calculations are performed on all grid points to create a symbol classification table.

For details, see “Pattern matching method (Special application)
57-43954, Japanese Patent Application Laid-open No. 58-161088).

(b) Concerning the specific aspects of "logical symbol recognition": Basically, the four-way code described in the symbol classification dictionary and the four-way grid point label code are used.
By calculating the degree of similarity with the direction code, logical symbols are classified into those having a high degree of similarity. However, in doing so, we make good use of Don't Care Bits N _T and Don't Care Codes DC to ensure that the symbols to be classified (recognized) can be classified without any problems even if there are characters written inside or around them.

For details, see "Pattern matching method (Special application
57-43954, Japanese Unexamined Patent Publication No. 58-161088).

(c) Concerning the specific meaning of "don't care bits N _T for the whole": As mentioned above, symbol classification dictionaries are designed so that characters are written within logical symbols to prevent the dictionary from becoming too large. Since the same classification dictionary is used for cases where the symbol is not written or not, when calculating the similarity between the symbol classification dictionary and the four-way code of the grid point label code, the original shape of the logical symbol and its The four-way code for that part may be different to distinguish it from other parts of the character. In other words, N _T is the bit used to express that even if they are different, they can be considered to match.

Overall means don't care code DC
(N ₁ - _{N 4} ) is a don't care bit corresponding to each SC (DLUR), whereas don't care bit _NT is a don't care bit for all SCs.

(d) Regarding the creation mode of "don't care bits N _T for the whole": Created by a human (system developer or system user).

By the way, when setting a symbol area based on the symbol classification table of FIG. 3 extracted by calculating the similarity between the symbol classification dictionary created in this way and the four-way code of the grid point label code, simply use the coordinates i, If all the grid point label codes within the symbol size MX and MY are placed within the symbol using j as the reference, in the example shown in Figure 6, the characters inside the symbol frame will be included in the symbol area, so the characters must be cut out separately. This is inconvenient for recognition (character search is not performed because it is inside the symbol).

Furthermore, since a part of the logic symbol as shown in FIG. 2d is the same as NOAH, it tends to be recognized as either a or b in FIG. This is because when recognizing a logical symbol, the pattern that appears in the window W is the recognition target, and this window W moves in a grid bit and the pattern within the window at _each position is compared with the dictionary pattern. This is because the symbol in Figure 8a becomes the symbol in Figure _8b at the W2 position.

The present invention aims to solve such a problem, and the above-mentioned don't care bits of a symbol recognition dictionary are
N ₁ to N ₄ and N _T are used. First, the symbol addresses i, j are sequentially determined from the symbol classification table in FIG.
and its symbol NO, read out the symbol NO,
Read the classification dictionary pattern corresponding to . Then i,
The size of the symbol area based on j is MX＊MY
The symbol area bits of each lattice point label code, that is, the first bit S in FIG. 1, are set to 1 or 0. To make this decision, check all don't care bits N _T in the symbol classification dictionary, and if N _T = 1, unconditionally set S = 0,
This grid point information clearly indicates that it is not a logical symbol pattern. If N _T =0 and any bit of the standard code SC is 1, S=1. In this way, if only those with S=1 are extracted from the lattice point label code group in the MX*MY rectangular area, it is exactly the same as the dictionary pattern, and wiring, characters, etc. are erased. In other words, through this operation, the pattern information of the recognized logical symbol is corrected and purified using the dictionary pattern, so that symbol patterns and others are clearly separated.

When setting the above symbol area bit S, if there is something already set in the bit S of the lattice point label code, the symbol is considered to have been extracted redundantly, and the FLAG of the logic symbol classification table is
is set to 1 (meaning that this symbol is duplicated), and the symbol area bit S is not set. This makes it possible to avoid double extraction and recognition as described with reference to FIG. Note that if the S bit has already been set, it will not be reset, so the faster the processing, the higher the priority. Therefore, the dictionary patterns are recognized in order from large patterns to small patterns. In this way, the dictionary pattern for window W ₁ in Figure 8 is
Since it is larger than the dictionary pattern for W ₂ (specifically, a match can be achieved only with a narrow dictionary pattern), extraction of the symbol in FIG. 8b is avoided.

As described above, according to the present method, it is possible to avoid detection of duplicate symbols, and to strictly separate character parts and connections from logical symbols.

FIG. 9 shows an example of the above processing. A is a hand-drawn logic circuit diagram, and b is a two-dimensional graphical representation of a data group obtained by compressing the logic circuit diagram into a grid point label code. Since the grid spacing is relatively large, the arc portions are straightened as shown in the figure, and the characters are deformed to the point that they are unreadable. The thick line part is S by the above process.
This is the part with the lattice point label code set to =1, and as is clear from looking at only the thick lines, the characters and wiring have been erased, leaving only logical symbols.

10 and 11 show an outline of an embodiment of the present invention. 10 is an image input device such as a facsimile; 12 is an image memory into which the output video signal of the device 10 is written; 14 is an address control unit that generates an address signal for accessing the memory;
15 is an overall control unit, 16, 18, 20, 22,
and 24 are a verification circuit 16, a reference point detection circuit, a lattice conversion circuit (horizontal), a lattice conversion circuit (vertical), and an LB3 generation circuit which receive the readout output of the memory 12. 26 is a table storing the grid points detected by the reference point detection circuit 18; 28 and 30 are grid point label code generation circuits (horizontal) and the same (vertical);
32 is LBL table, 34, 36, 38 are LB1
~LB3 table, 40 is the verification window W setting circuit,
42 and 44 are SX1 and SY output by the verification circuit 16
1, a table for storing SX2, SY2; 46 is an address conversion circuit; 52, 54, 56, 58, and 60 are pair processing circuits that perform processing by inputting labels from the label table 50 in FIG. 11; They are a correction circuit, a character removal circuit, a misalignment correction circuit, and an ambiguity correction circuit. Furthermore, 6 in Figure 11
2 is a symbol classification dictionary memory, 64 is a similarity calculation circuit, 66 is a classification table for storing the logical symbols recognized by the circuit, 68 is a symbol area detection circuit, 70 is a symbol classification dictionary memory, 72
is a symbol area setting circuit. Note that the symbol classification dictionary memory 62 and the symbol classification dictionary memory 70 are the same. Most of these are the same as the "pattern matching method",
In the present invention, the symbol area detection circuit 6
8 and a symbol area setting circuit 72 are added.
The method of setting the symbol area, that is, the S bit, is as described above, and the symbol area detection circuit 68 is as follows.
The logical symbols stored in the symbol classification table 66 and their addresses are read out, and the dictionary corresponding to the logical symbols is read out from the symbol classification dictionary memory 70, and based on all don't care bits N _T written in the dictionary. When setting a symbol area, it is detected whether the first bit S of the grid point label code is 1 or not. If S = 1 (already set), the current symbol area on the symbol classification table is Set the FLAG of the symbol you are trying to set to 1. If S=0 (not set), the symbol area setting circuit 72 is activated. Further, the symbol area setting circuit 72 sets the first bit S of the lattice point label code for which the symbol area is to be set, based on all don't care bits N _T of the symbol classification dictionary.

Effects of the Invention As explained above, in the present invention, a symbol area bit is provided in the lattice point label code to indicate whether or not the lattice point information is related to a logical symbol pattern, and when a logical symbol is recognized, a dictionary pattern is set. Since the symbol area bits are set according to the following, wires, characters, etc. attached to the logic symbol can be separated from the logic symbol, and the logic symbol can be read accurately and automatically. Since the symbol area bits are set only once and are not reset, there is an advantage that the same logical symbol will not be mistakenly recognized as a plurality of different logical symbols.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the grid point label code, Figure 2 is an illustration of an example of a logical symbol, Figure 3 is an explanatory diagram of a logical symbol classification table, and Figure 4 is an explanation of the direction and representative point of the logical symbol. Figure 5 is an explanatory diagram of the standard pattern, Figure 6 is an explanatory diagram of a modified pattern, Figure 7 is an explanatory diagram of a dictionary pattern that takes into account ambiguity, Figure 8 is an explanatory diagram of duplicate symbols, and Figure 9 is an explanatory diagram of a dictionary pattern that takes into account ambiguity. FIGS. 10 and 11 are explanatory diagrams showing processing examples, and are block diagrams showing embodiment circuits. In the drawing, DLUR is a 4-way code, W is a scanning window,
S is a symbol area bit.

Claims (1)

[Claims] 1. A logic circuit drawing in which characters and wiring are mixed in logic symbols drawn along a grid axis is read by an input device, and the direction of a line segment at each grid point is indicated from the obtained video signal. A lattice point label code including a 4-way code is obtained, and the lattice point label code within the scanning window area is added to a dictionary created in advance (4-way code corresponding to the shape of the logical symbol and don't care bit information for comparison). In this method, logical symbols are automatically recognized and separated by comparing the 4-way code of the lattice point label code with a dictionary by providing an area for storing symbol area bits in the lattice point label code a logical symbol recognition result storage means for storing recognition results of recognized logical symbols; sequentially reading logical symbol recognition information from the logical symbol recognition result storing means; and reading a dictionary corresponding to the read logical symbols; symbol area bit detection means for detecting whether a symbol area bit of a lattice point label code corresponding to a line segment constituting the logical symbol has already been set; When it is determined that the logical symbol recognition result is stored in the logical symbol recognition result storage means and is currently being read out, means for invalidating the recognition result of the logical symbol currently being read out, and means for determining whether the symbol area bit is not set by the symbol area bit detection means When it is determined that 1. An automatic recognition and separation method for logical symbols, comprising a symbol area bit setting means executed based on don't care bits, and separating logical symbol information from character and wiring information. 2. The automatic recognition/separation method for logical symbol areas according to claim 1, wherein the symbol area bits are set only once, and the bits that have already been set are not reset.